Cyrix 6x86-P200+ free download

File name 6xP200DB.pdf

6x86-P200+ PROCESSOR ® Advancing the Standards Sixth-Generation Superscalar Superpipelined x86-Compatible CPU 6x86-P200+ PROCESSOR DATA BOOK ADDENDUM Sixth-Generation Superscalar Superpipelined Architecture - Operating frequency of 150 MHz core, 75 MHz bus - Optimized to run both 16-bit and 32-bit software applications - Dual 7-stage integer pipelines - High performance 80-bit FPU with 64-bit interface - 16-KByte unified write-back L1 cache Best In-Class Performance Through Superior Architecture - Register renaming - Out-of-order completion - Data dependency removal - Multi-branch prediction - Speculative execution X86 Instruction Set Compatible - Runs Windows 95, Windows 3.x, Windows NT, DOS, UNIX, OS/2, Solaris, and others The Cyrix 6x86TM -P200+ has an identical architecture compared to previous 6x86 processors, but operates at a core frequency of 150 MHz. The 6x86 series of CPUs are superscalar, superpipelined sixth generation CPUs that offer the highest level of performance available for desktop personal computers. Optimized to run both 16-bit and 32-bit software applications, the 6x86 processor is fully compatible with the x86 instruction set and delivers industry-leading performance running Windows® 95, Windows, Windows NT, OS/2®, DOS Solaris, UNIX® and other operating systems. The 6x86 processor achieves top performance through the use of two optimized superpipelined integer units and an on-chip floating point unit. Additionally, the integer and floating point units are optimized for maximum instruction throughput by using advanced architectural techniques including register renaming, out-of-order completion, data dependency removal, branch prediction and speculative execution. These design innovations eliminate many data dependencies and resource conflicts to achieve high performance when executing existing 16-bit and future 32-bit software applications. Instruction Address IF Sequence Control Lines ID1 ID2 AC1 AC2 EX WB FPU OpCode X Pipe Instruction Data 128 ID2 AC1 AC2 EX WB Y Pipe 32 Address A31-A3 BE7#-BE0# X Data 32 Y Data 32 256-Byte Instruction Line Cache 32 Bus Interface Unit Floating Point Queue Integer Unit 32 32 Y Linear Address 16- KByte Unified Cache Data Cache Unit 64 D63-D0 64 Floating Point Processor X Linear Address CLK Floating Point Unit 64 32 Memory Management Unit X Physical Address Y Physical Address Control 32 Bus Interface 1738502 May 13, 1996 2:31 pm c:\dataoem\!m1p200\m1p200.fm Revision 1.2 ADVANCE INFORMATION May 1996 Order Number: 941xx-01 1 ® Electrical Connections Advancing the Standards 1.0 OVERVIEW The Cyrix 6x86-P200+ Processor operates at a frequency of 150 MHz, and interfaces to a system with a 75 MHz bus. This document includes the electrical specifications for the 6x86-P200+ devices. The 6x86-P200+ timing information is included for refrence. Refer to the 6x86 Processor Data Book for complete information on the achitecture, programming interface and bus interface