Atmel AT90S2313 free download

File name 90S2313.PDF

AT90S2313 Features · · · · · · · · · · · · · · · · · · · · · Utilizes the AVR ® Enhanced RISC Architecture AVR - High Performance and Low Power RISC Architecture 120 Powerful Instructions - Most Single Clock Cycle Execution 2K bytes of In-System Reprogrammable Downloadable Flash - SPI Serial Interface for Program Downloading - Endurance: 1,000 Write/Erase Cycles 128 bytes EEPROM - Endurance: 100,000 Write/Erase Cycles 128 bytes Internal RAM 32 x 8 General Purpose Working Registers 15 Programmable I/O Lines VCC: 2.7 - 6.0V Fully Static Operation, 0 - 20 MHz Instruction Cycle Time: 50 ns @ 20 MHz One 8-Bit Timer/Counter with Separate Prescaler One 16-Bit Timer/Counter with Separate Prescaler and Compare and Capture Modes Full Duplex UART Selectable 8, 9 or 10 bit PWM External and Internal Interrupt Sources Programmable Watchdog Timer with On-Chip Oscillator On-Chip Analog Comparator Low Power Idle and Power Down Modes Programming lock for Software Security 20-Pin Device 8-Bit Microcontroller with 2K bytes Downloadable Flash Preliminary AT90S2313 Description The AT90S2313 is a low-power CMOS 8-bit microcontroller based on the AVR ® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S2313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. (continued) Pin Configuration 0839A 3-5 Block Diagram Figure 1. The AT90S2313 Block Diagram 3-6 AT90S2313 AT90S2313 Description (Continued) The AT90S2313 provides the following features: 2K bytes of Downloadable Flash, 128 bytes EEPROM, 128 bytes SRAM, 15 general purpose I/O lines, 32 general purpose working registers, flexible timer/counters with compare modes, internal and external interrupts, a programmable serial UART, programmable Watchdog Timer with internal oscillator, an SPI serial port for Flash Memory downloading and two software selectable power saving modes. The Idle Mode stops the CPU while allowing the SRAM, timer/counters, SPI port and interrupt system to continue functioning. The power down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. The device is manufactured using Atmel's high density non-volatile memory technology. The on-chip Downloadable Flash allows the program memory to be reprogrammed in-system through an SPI serial interface or by a conventional nonvolatile memory programmer. By combining an enhanced RISC 8-bit CPU with Downloadable Flash on a monolithic c