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Voltage Regulators
AN1149NFHK
6-ch DC-DC Converter
I Overview Unit: mm
4 channels of step-up, 1 channel of step-down and 1 9.0±0.2
7.0±0.1
channel of step-up/down voltage, 6 channels in total have 36 25
been integrated onto a single chip. Each channel can be 24
37
remote-controlled and work with two dry cells. A high
(0.75)
precision output voltage can be obtained thanks to the
7.0±0.1
9.0±0.2
accurate reference of VREF ±1%.
48 13
I Features
1 12
· Low voltage operation (1.5 V min.) (0.75) 0.5 0.20±0.05
0.10 M (1.0)
· High precision reference voltage (±1%)
(1.0)
0.15±0.05
1.20 max.
· Remote control for each channel
0.10+0.10
0.05
0° to 8°
I Applications 0.5±0.1
· Digital still cameras
TQFP048-P-0707B (Lead-free package)
Publication date: May 2002 SDH00014BEB 1
AN1149NFHK
I Block Diagram
PVCC1 PVCC2 SVCC VREF RT CT CTL 1 S.C.P.1
PV
10PV 26 32 40 39 38 46 VBAT
CC1 CC2 41 14
VCC Start-up VBAT Latch
37 OSC circuit U.V.L.O. RQS
SCP U.V.L.O. Reference voltage
supply 1.26 V ± 1%
R
LATCH
S Q
SVCC VREF
3 PVCC1
EO 1
2 Error-amp.1
PWM1
IN-1 Out 1
13
VREF
PGND1
S.C.P. comp. VREF
SRFB
REG-amp.1 47
SRIN
1
0.9 V SRDV
VREF
48
SS 1
PVCC1 12
EO 2 6 PWM2
Out 2
16
Error-amp.2
4 PGND1
IN-2 CTL VREF
VREF VREF comp.2
CTL 2 45
15 SS 2
9
EO 3 Boot-up UDSW
7 /step-down PVCC1 36
FB 3 VREF
PWM3 switch
8 Error-amp.3
IN-3 Out 3
VREF
18
PGND1
SS 3
17
35
EO 4 PVCC2
34
FB 4 Error-amp.4 VREF
33 PWM4
IN-4 Out 4
19
VREF CTL
comp.4 PGND2
44
CTL 34
SS 4
VREF 20
30 PVCC2
EO 5
31 Error-amp.5 VREF
PWM5
IN-5 Out 5
21
VREF CTL
VREF comp.5 PGND2
43
CTL 5 SS 5
22
27
EO 6 PVCC2
Error-amp.6 VREF
29 PWM6
IN-6 Out 6
IN+6 23
28 CTL
VREF comp.6 PGND2
CTL 6 SS 6
42 24
5 11 25
SGND PGND 1 PGND 2
2 SDH00014BEB
AN1149NFHK
I Pin Descriptions
Pin No. Symbol Description Pin No. Symbol Description
1 SRIN Regulator amplifier input pin 27 EO 6 Output pin for part-6 error amplifier
2 IN-1 Inverse input for part-1 error amplifier 28 IN+6 Non-inverted input pin for part-6 error amplifier
3 EO 1 Output for part-1 error amplifier 29 IN-6 Inverted input pin for part-6 error amplifier
4 IN-2 Inverse input for part-2 error amplifier 30 E 5 Output pin for part-5 error amplifier
5 SGND Signal GND pin 31 IN-5 Inverted input pin for part-5 error amplifier
6 EO 2 Output for part-2 error amplifier 32 SVCC Supply voltage application pin for signal block
7 FB 3 CH 3 output voltage detection pin 33 IN-4 Inverted input pin for part-4 error amplifier
8 IN-3 Inverse input for part-3 error amplifier 34 FB 4 CH 4 output voltage detection pin
9 EO 3 Output for part block-3 error amplifier 35 EO 4 Output pin for part-4 error amplifier
10 PVCC1 Voltage application pin 1 for output block 36 UDSW Step-down output setup pin for CH 3
11 PGND1 Output GND pin 1 37 SCP Short-circuit protection time constant
12 SS-1 CH 1 soft start setting pin setup capacitance connection pin for CH 2-6
13 Out-1 Push-pull output pin for out-1 block 38 CT Oscillator frequency setup capacitor
14 VBAT Battery voltage application pin connection pin
15 SS-2 CH 2 soft start setting pin 39 RT Oscillator frequency setup resistor
16 Out-2 Totem pole output pin for out-2 block connection pin
17 SS-3 CH 3 soft start setting pin 40 VREF Reference voltage output pin
18 Out-3 Totem pole output pin for out-3 block 41 SCP 1 Output short-circuit protection time constant
19 Out-4 Totem pole output pin for out-4 block setup capacitor connection pin for CH 1
20 SS-4 CH 4 soft start setting pin 42 CTL 6 CH 6. on-off control pin
21 Out-5 Totem pole output pin for out-5 block 43 CTL 5 CH 5. on-off control pin
22 SS-5 CH 5 soft start setting pin 44 CTL 34 CH 3, CH 4. on-off control pin
23 Out-6 Totem pole output pin for out-6 block 45 CTL 2 CH 2. on-off control pin
24 SS-6 CH 6 soft start setting pin 46 CTL 1 CH 1. on-off control pin
25 PGND2 Output GND pin 2 47 SRFB Regulator amplifier output voltage detection pin
26 PVCC2 Voltage application pin 2 for output block 48 SRDV Regulator amplifier drive pin
I Absolute Maximum Ratings
Parameter Symbol Rating Unit
Supply voltage SVCC 9.2 V
Power VCC1 allowable application voltage PVCC1 9.2 V
Power VCC2 allowable application voltage PVCC2 9.2 V
Battery input allowable application voltage VBAT 9.2 V
Allowable application voltage to regulator VSRFB SVCC V
output voltage detection input pin
Note) 1. Do not apply external currents or voltages to any pins not specifically mentioned.
For the circuit currents, '+' denotes current flowing into the IC, and '-' denotes current flowing out of the IC.
2. Except for the power dissipation, operating ambient temperature and storage temperature, all ratings are for Ta = 25°C.
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I Absolute Maximum Ratings (continued)
Parameter Symbol Rating Unit
Step up / down switch input VUDSW SVCC V
allowable application voltage *2
Allowable application voltage to VFB3 SVCC V
output voltage detection input 3
Allowable application voltage to VFB4 SVCC V
output voltage detection input 4
Allowable application voltage to VCTL1 VBAT V
control input 1
Allowable application voltage to VCTL2 SVCC V
control input 2
Allowable application voltage to VCTL34 SVCC V
control input 3, 4
Allowable application voltage to VCTL5 SVCC V
control input 5
Allowable application voltage to VCTL6 SVCC V
control input 6
Error amplifier allowable application VIN - 0.2 to SVCC V
voltage to input pin
Supply current ICC mA
Output 2 allowable peak current IOP2 ±400 mA
Output 3 allowable peak current IOP3 ±400 mA
Output 4 allowable peak current IOP4 ±400 mA
Output 5 allowable peak current IOP5 ±400 mA
Output 6 allowable peak current IOP6 ±400 mA
Output 1 allowable sequence current IO1 -50 mA
Output 2 allowable sequence current IO2 ±100 mA
Output 3 allowable sequence current IO3 ±100 mA
Output 4 allowable sequence current IO4 ±100 mA
Output 5 allowable sequence current IO5 ±100 mA
Output 6 allowable sequence current IO6 ±100 mA
Reference voltage allowable application IREF -5 mA
current
Power dissipation *1 PD 160 mW
Operating ambient temperature Topr -20 to +85 °C
Storage temperature Tstg -55 to +125 °C
Note) 1. Do not apply external currents or voltages to any pins not specifically mentioned.
For the circuit currents, '+' denotes current flowing into the IC, and '-' denotes current flowing out of the IC.
2. Except for the power dissipation, operating ambient temperature and storage temperature, all ratings are for Ta = 25°C.
3. *1: Ta = 85°C. For the independent IC without a heat sink. Note that applications must observe the derating curve for the
relationship between the IC power consumption and the ambient temperature.
*2: Allowable application voltage shall be 8.2 V or less when SVCC 8.2 V.
4 SDH00014BEB
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I Recommended Operating Range
Parameter Symbol Range Unit
Supply voltage VBAT 1.5 to 9 V
SVCC 4.5 to 9 V
I Recommended Operating Conditions
Parameter Symbol Range Unit
Out-1 source current IOUT1 30 (max.) mA
Out-2 to Out-6 peak current IOUT2 to 6 -400 to 400 mA
Timing resistance RT 8 to 100 k
Timing capacitance CT 560 (fixed) pF
Oscillation frequency fOUT 100 to 1 000 kHz
Short-circuit protection time CSCP1, 2 1 000 (min.) pF
constant setting capacitance
I Electrical Characteristics at VBAT = 3 V, SVCC = PVCC1 = PVCC2 = 5 V, CREF = 0.1 µF, Ta = 25°C
Parameter Symbol Conditions Min Typ Max Unit
Reference voltage
Reference voltage VREF IREF = - 0.1 mA 1.247 1.26 1.273 V
Line regulation Line VCC = 4.5 V to 9 V 3 20 mV
Load regulation Load IREF = - 0.1 mA to -1 mA -20 -5 mV
SVCC low voltage protection
Circuit operation start voltage SVCCON 3.9 4.1 4.3 V
Circuit operation stop voltage SVCCOFF 3.7 3.9 4.1 V
VBAT low voltage protection
Circuit operation start voltage VBATON 1.36 1.43 1.5 V
Circuit operation stop voltage VBATOFF 1.33 1.39 1.45 V
Oscillator
CH 1 oscillation frequency at startup fST CT = 560 pF 55 80 105 kHz
SVCC = PVCC1 = PVCC2 = 1 V
CH 1 to CH 6 oscillation frequency fOUT1 to 6 RT = 20 k 490 540 590 kHz
CT = 560 pF
Output block
CH 1 to CH 6 output maximum DU1 to 6 RT = 20 k CH 4 78 84 90 %
duty ratio CT = 560 pF except CH 4 82 88 94 %
CH 1 output duty ratio at startup DUST CT = 560 pF 60 68 76 %
SVCC = PVCC1 = PVCC2 = 1 V
Output high voltage 1 (CH 1) VOH1 IOUT1 = 20 mA VCC - 2 V
Output source current IOL1 VOUT1 = 0.7 V 20 mA
Output high voltage 2 to 6 (CH 2 to CH 6) VOH2 to 6 IOUT2 to 6 = - 0.1 mA VCC - 1 V
Output low voltage 2 to 6 (CH 2 to CH 6) VOL2 to 6 IOUT2 to 6 = 0.1 mA 1 V
SDH00014BEB 5
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I Electrical Characteristics at VBAT = 3 V, SVCC = PVCC1 = PVCC2 = 5 V, CREF = 0.1 µF, Ta = 25°C (continued)
Parameter Symbol Conditions Min Typ Max Unit
Output block (continued)
Output high voltage at standby VOHS3, 4 IOUT3, 4 = - 0.1 mA VCC - 1 V
(CH 3, CH 4)
Output low voltage at standby VOLS2 to 6 IOUT2, 3, 5, 6 = 0.1 mA 1.0 V
(CH 2, CH 3, CH 5, CH 6)
CH 3 output setup block
Threshold voltage VCTH 1.56 1.96 2.36 V
Error amplifier (CH 1 to CH 6)
Input threshold voltage 1 to 6 VTH1 to 6 1.241 1.26 1.279 V
Input bias current 2, 5, 6 IB2, 5, 6 - 0.22 - 0.12 µA
High-level output voltage 1 to 6 VEH1 to 6 1.0 V
Low-level output voltage 1 to 6 VEL1 to 6 0.2 V
Output source current 1 to 6 ISO1 to 6 -45 -38 -32 µA
Output sink current 1 to 6 ISI1 to 6 0.5 mA
CH 6 offset voltage VOFF6 -6 6 mV
CH 1, CH 3, CH 4 output detection RO1, 3, 4 -1 1 %
resistance division ratio
CH 1 short-circuit protection circuit block
Pin voltage at standby VSTB1 0.1 V
Latch threshold voltage VLTH1 0.27 0.3 0.33 V
Pin voltage at latch operation VSLT1 0.1 V
Charge current ICHG1 VSCP1 = 0 V -3.1 -2.4 -1.7 µA
CH 2 to CH 6 short-circuit protection circuit block
Pin voltage at standby VSTB1 0.1 V
Latch threshold voltage 2 to 6 VLTH2 to 6 0.8 0.9 1.0 V
Pin voltage 2 to 6 at latch operation VSLT2 to 6 0.1 V
Charge current ICHG1 VSCP = 0 V -1.53 -1.2 - 0.87 µA
Control
Pin current ICTL2 to 6 -1.53 -1.2 - 0.87 µA
(CH 2, CH 34, CH 5, CH 6)
CH 1 threshold voltage VCTL1 1.0 1.5 V
CH 2, CH 34, CH 5, CH 6 VCTL2 to 6 1.07 1.26 1.45 V
threshold voltage
Regulator amplifier
Output high voltage VHRA VCC = 5 V 1 V
ISRDV = 10 mA
Pin voltage when external PNP VRA SVCC = 5.5 V to 7.5 V 4.9 5.0 5.1 V
transistor is connected
Output detection resistance division ratio ROR -1 1 %
6 SDH00014BEB
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I Electrical Characteristics at VBAT = 3 V, SVCC = PVCC1 = PVCC2 = 5 V, CREF = 0.1 µF, Ta = 25°C (continued)
Parameter Symbol Conditions Min Typ Max Unit
Current consumption
Current consumption at startup IBAT VBAT = 3 V 440 655 µA
SVCC = 1 V
Average current consumption ICC(AV) Duty = 50% 9 12 mA
Standby current ISB VBAT = 3 V, SVCC = 1 V 34 42 50 µA
VCTL1 = 0 V
· Design reference data
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter Symbol Conditions Min Typ Max Unit
Reference voltage
VREF temperature characteristics VREFdT Ta = -20°C to 85°C -1.5 +1.5 %
RT pin voltage VRT 0.7 V
SVCC low voltage protection
Voltage difference between operation SVCC SVCCON - SVCCOFF > 0 0.2 V
start and stop
VBAT low voltage protection
Voltage difference between operation VBAT VBATON - VBATOFF > 0 0.04 V
start and stop
Error amplifier (CH 1 to CH 6)
VTH temperature characteristics VTHdT Ta = -30°C to 85°C -1.5 +1.5 %
Open loop gain AV 80 dB
Oscillator
Frequency supply voltage fdV VCC = 4.5 V to 9 V -16 +16 %
characteristics RT = 20 k, CT = 560 pF
Frequency temperature characteristics fdT Ta = -30°C to 85°C -3 +3 %
RT = 20 k, CT = 560 pF
Short-circuit protection circuit
Comparator threshold voltage VTHS 1.26 V
Control (CTL 1)
CTL 1 pin current ICTL1 VCTL1 = 3 V 230 µA
SDH00014BEB 7
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I Terminal Equivalent Circuits
Pin No. Equivalent circuit Description I/O
1 SRIN : I
SVCC
Output voltage detection pin / inverting input pin
SRFB for regulator amplifier.
12.6 k built in between SRIN and SGND, 37.4
37.4 k VREF k between SRIN and SRFB.
1
12.6 k
2 SVCC IN-1 : I
Non-inverting input pin for CH 1 error amplifier 1.
12.6 k built in between IN-1 and SGND, and
37.4 k 37.4 k between IN-1 and SVCC. Set CH 1, DC-
VREF DC output to 5 V.
2
12.6 k
3 EO 1 : O
VREF Output pin for CH 1 error amplifier.
Source current: -38 µA, sink current: min. 0.5
VREF 38 µA
mA.
3
IN-1 0.5 mA
4 IN-2 : I
SVCC
Non-inverting input pin for CH 2 error amplifier.
VREF
4
5 SGND :
5 Signal GND pin.
6 EO 2 : O
VREF Output pin for CH 2 error amplifier.
Source current: -38 µA, sink current: min. 0.5
VREF 38 µA
mA.
6
IN-2 0.5 mA
8 SDH00014BEB
AN1149NFHK
I Terminal Equivalent Circuits (continued)
Pin No. Equivalent circuit Description I/O
7 FB 3 : I
SVCC CH 3 output voltage detection pin.
12.6 k built in between IN-3 and SGND, and
7 20.4 k between IN-3 and FB 3. DC-DC output
20.4 k of CH 3 is set to 3.3 V.
VREF
8
8 IN-3 : I
12.6 k Non-inverting input pin for CH 3 error amplifier 3.
9 EO 3 : O
VREF Output pin for CH 3 error amplifier.
Source current: -38 µA, sink current: min. 0.5
VREF 38 µA
mA.
9
IN-3 0.5 mA
10 PVCC1 :
10 CH 1, CH 2 power supply pin for output block.
11 PGND1 :
11 CH 1, CH 2 output block GND pin.
12 SS 1 : I
CH 1 soft start time setting pin. Connect a capaci-
VREF EO 1 CT
tor between this pin and GND. CH 1 max. duty
43.8 k ratio is set to 88% (in-house), but max. of on
PWM1
12 period can be adjusted by connecting a resistor
56.2 k between this pin and VREF pin.
See Application Notes [3] 8.
13 Out 1 : O
VREF SVCC1 Output SW Tr. driver pin at start-up and push-
pull output pin at PWM control.
Absolute maximum rating of output source cur-
13
13 rent at PWM is -50 mA.
OSC
a) at start-up b) at PWM control
14 VBAT :
14 Battery voltage application pin.
SDH00014BEB 9
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I Terminal Equivalent Circuits (continued)
Pin No. Equivalent circuit Description I/O
15 SS 2 : I
EO 2 CT CH 2 soft start time setting pin. Connect a capaci-
VREF
tor between this pin and GND. CH 2 max. duty
43.8 k ratio is set to 88% (in-house), but max. of on
PWM2
15 period can be adjusted by connecting a resistor
56.2 k between this pin and VREF pin.
See Application Notes [3] 8.
16 Out 2 : O
SVCC1 Totem pole type output pin.
Normal output current ±100 mA and a peak cur-
rent ±400 mA can be taken out.
16
17 SS 3 : I
CH 3 soft start time setting pin. Connect a capaci-
VREF EO 3 CT
tor between this pin and GND. CH 3 max. duty
43.8 k ratio is set to 88% (in-house), but max. of on
PWM3
17 period can be adjusted by connecting a resistor
56.2 k between this pin and VREF pin.
See Application Notes [3] 8.
18 Out 3 : O
SVCC2 Totem pole type output pin.
Normal output current ±100 mA and a peak cur-
rent ±400 mA can be taken out.
18
19 Out 4 : O
SVCC2 Totem pole type output pin.
Normal output current ±100 mA and a peak cur-
rent ±400 mA can be taken out.
19
20 SS 4 : I
VREF EO 4 CT CH 4 soft start time setting pin. Connect a capaci-
tor between this pin and GND. CH 4 max. duty
43.8 k
PWM4 ratio is set to 84% (in-house), but max. of on
20 period can be adjusted by connecting a resistor
56.2 k
between this pin and VREF pin.
See Application Notes [3] 8.
10 SDH00014BEB
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I Terminal Equivalent Circuits (continued)
Pin No. Equivalent circuit Description I/O
21 Out 5 : O
SVCC2 Totem pole type output pin.
Normal output current ±100 mA and a peak cur-
rent ±400 mA can be taken out.
21
22 SS 5 : I
VREF EO 5 CT CH 5 soft start time setting pin. Connect a capaci-
tor between this pin and GND. CH 5 max. duty
43.8 k
PWM5 ratio is set to 88% (in-house), but max. of on
22
period can be adjusted by connecting a resistor
56.2 k
between this pin and VREF pin.
See Application Notes [3] 8.
23 Out 6 : O
SVCC2
Totem pole type output pin.
Normal output current ±100 mA and a peak cur-
rent ±400 mA can be taken out.
23
24 SS 6 : I
VREF EO 6 CT CH 6 soft start time setting pin. Connect a capaci-
tor between this pin and GND. CH 6 max. duty
43.8 k
PWM6 ratio is set to 88% (in-house), but max. of on
24 period can be adjusted by connecting a resistor
56.2 k
between this pin and VREF pin.
See Application Notes [3] 8.
25 PGND2 :
25 CH 3 to CH 6 output block GND pin.
26 PVCC2 :
26 CH 3 to CH 6 power supply pin for output block.
27 EO 6 : O
VREF
Output pin for CH 6 error amplifier.
38 µA Source current: -38 µA, sink current: min. 0.5
IN+6
mA.
27
IN-6 0.5 mA
SDH00014BEB 11
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I Terminal Equivalent Circuits (continued)
Pin No. Equivalent circuit Description I/O
28 IN+6 : I
SVCC
Inverting input pin for CH 6 error amplifier.
29 IN-6 : I
29 28
Non-inverting input pin for CH 6 error amplifier.
30 EO 5 : O
VREF Output pin for CH 5 error amplifier.
Source current: -38 µA, sink current: min. 0.5
VREF 38 µA
mA.
30
IN-5 0.5 mA
31 SVCC IN-5 : I
Non-inverting input pin for CH 5 error amplifier.
VREF
31
32 SVCC :
32 Power supply pin for signal block.
33 IN-4 : I
SVCC Non-inverting input pin for CH 4 error amplifier.
34
34 FB 4 : I
12.4 k CH 4 output voltage detection pin.
VREF
33 12.6 k built in between IN-4 and SGND, and
12.6 k 12.4 k between IN-4 and FB 3. DC-DC output
of CH 4 is set to 2.5 V.
35 EO 4 : O
VREF
Output pin for CH 4 error amplifier.
38 µA Source current: -38 µA, sink current: min. 0.5
VREF
mA.
35
IN-4 0.5 mA
12 SDH00014BEB
AN1149NFHK
I Terminal Equivalent Circuits (continued)
Pin No. Equivalent circuit Description I/O
36 UDSW : I
SVCC
CH 3 step down / step-up output setup pin.
Step up N-channel drive and voltage step-up operation
Step down
with UDSW of SVCC potential, P-channel drive
and voltage step-down operation with UDSW of
VREF 36
GND potential.
37 SVCC SCP : O
1.2 µA A capacitor connecting pin to set a time constant
LACH of timer latch short-circuit protection circuit to
S R Q
Output
cutoff protect from CH 2 to CH 6 output short circuit.
Use within 1 000 pF or more of capacitance.
Charged current ICHG is 1.2 µA typ.
37
38 at start-up CT : O
VBAT Frequency setting capacitor connecting pin for
start-up and for PWM control.
80 kHz fixed inside at startup, and use in the range
38 of 100 kHz to 1 MHz by setting up the resistor at
RT pin in PWM control. Here, use the 560 pF
fixed capacitor.
at PWM control
SVCC
LACH
38 S R Q
0.3 V
39 RT : O
Dischavging current
Frequency setting resistor connection pin at PWM
circuit
control.
Use within 100 kHz to 1 MHz of oscillation
frequency using a 8 k to 100 k resistor in
0.7 V combination with the capacitor at CT pin.
39
40 VREF : O
SVCC Inner reference voltage output pin. Reference
voltage is 1.26 V±1% at IREF = - 0.1 mA, and
SVCC = 5 V. Connect a capacitor of 0.1 µF or more
40
between VREF and GND for phase compensation.
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I Terminal Equivalent Circuits (continued)
Pin No. Equivalent circuit Description I/O
41 SCP1 : O
VBAT
A capacitor connecting pin to set the time con-
2.4 µA
LACH
stant of a timer latch short circuit protection cir-
Output
S R Q
cut-off cuit at CH 1 output short circuit.
0.3 V Use the IC within 1 000 pF or more of capaci-
tance. Charged current ICHG1 is 2.4 µA typ.
41
42 CTL 6 : I
SVCC CH 6 on-off control pin.
1.2 µA By connecting a capacitor between this pin and
High GND, you can make delay for a rise time. Input
CH 6
operating voltage range at on / off control by outer signal is
VREF
0 to SVCC.
42
43 CTL 5 : I
SVCC CH 5 on-off control pin.
1.2 µA By connecting a capacitor between this pin and
High GND, you can make delay for a rise time. Input
CH 5
operating voltage range at on / off control by outer signal is
VREF
0 to SVCC.
43
44 CTL 34 : I
SVCC CH 3, CH 4 on-off control pin.
1.2 µA By connecting a capacitor between this pin and
High GND, you can make delay for a rise time. Input
CH 3, 4
operating voltage range at on / off control by outer signal is
VREF
0 to SVCC.
44
45 CTL 2 : I
SVCC CH 2 on-off control pin.
1.2 µA By connecting a capacitor between this pin and
High GND, you can make delay for a rise time. Input
CH 2
operating voltage range at on / off control by outer signal is
VREF
0 to SVCC.
45
14 SDH00014BEB
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I Terminal Equivalent Circuits (continued)
Pin No. Equivalent circuit Description I/O
46 CTL 1 : I
On / off control pin for all CHs and CH 1.
46
Inner circuit and CH 1 output start at VCTL1 1 V
20 k Inner circiut typ.
start/stop
Standby current at VCTL1 of off is 42 µA typ. at
10 k VBAT = 3 V.
Input voltage range of CTL 1 pin is 0 to VBAT.
47 SVCC SRDV : O
External PNP transistor driving pin for a regula-
tor amplifier.
SRIN 47 The sink current capability is more than 10 mA
and a pull-up resistor of 200 k to SVCC is built in.
VREF
48 SRFB : I
48 Output voltage detection input pin in regulator
37.4 k amplifier.
SRIN There are built in 12.6 k between SRIN and
12.6 k SGND, 37.4 k between SRIN and SRFB and
VREF
regulator output is set to 5 V.
I Application Notes
[1] PD Ta curves of TQFP048-P-0707B
PD T a
0.900
Mounted on standard board
0.800 (glass epoxy: 50 mm × 50 mm × t0.8 mm)
0.772 Rth(j-a) = 129.5°C/W
0.700
Power dissipation PD (W)
0.600
0.500
0.400
0.399
0.300
Independent IC
0.200 without a heat sink
Rth(j-a) = 250.6°C/W
0.100
0.000
0 25 50 75 100 125
Ambient temperature Ta (°C)
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I Application Notes (continued)
[2] Usage Notes
1. CH 1 operates first and steps up input voltage to 5 V allowing a low input power operation from 1.5 V. This 5 V
for CH 1 is used as supply voltage for entire IC. Since the protection circuit is designed for the above operation,
you are required to refrain from using for other than the application circuit. For instance, do not use in applying
the voltage directly to SVCC.
2. Power dissipation
Power dissipation PD is proportionate to supply voltage and varies according to CH 1 output load, FET input
capacitance of CH 1 to CH 6 and oscillation frequency, etc. On use, refer to the PD Ta curve and be careful not
to exceed power dissipation of the package, according to the following equation:
VOUT1 × IOUT1 × ROUT (VOUT1 - VBAT) × IOUT
P = (SVCC - VBEQ1 - )× + 5 × SVCC × Ciss × f
hfeQ1 × VBAT hfeQ1 × VBAT
+ SVCC × ICC + VBAT × IBAT < Pd
VBEQ1 : Base-emitter voltage of CH 1 NPN transistor
HfeQ1 : Current amplification ratio of CH 1 NPN transistor
ROUT : Bias current limit resistance to CH 1 NPN transistor
Ciss : Input capacitance of CH 2 to CH 6 output connecting FET
f : Oscillation frequency
ICC : SVCC, PVCC1, PVCC2 pin current
IBAT : VBAT pin current
[3] Function descriptions
1. Reference voltage block
The reference voltage block is constructed with a band gap circuit and it outputs temperature-compensated
reference of 1.26 V typ. and of precision ±1%. The reference voltage is stabilized with 4.5 V or more of supply
voltage. It is also used as reference for an error amplifier 1 to 6 and the regulator amplifier as well.
2. The triangular wave generator block
a) At start-up
Due to the capacitor 560 pF connected to CT pin (pin 38), a triangle wave of approx. 0.76 V high, 0.69 V
low and frequency of 80 kHz is generated.
b) A PWM operation
When SVCC potential reaches 4.1 V typ. by start of CH 1, the oscillation switches to a saw-tooth wave of
approx. 0.76 V high and approx. 0.3 V low from start oscillation due to a timing capacitor and RT pin (pin 39)
connection resistor. And it is connected to non-inverting input of PWM comparator IC inside. An oscillation
frequency abruptly can be set 100 kHz to max. 1 MHz by the external RT pin-connected resistor.
VCTH
0.76 V
VCTL
0.69 V
VCTL
0.3 V
t1
t2
(dischavging)
Frequency 80 kHz T
Startup oscillation PWM oscillation
Figure 1-1. Triangular oscillation waveform
16 SDH00014BEB
AN1149NFHK
I Application Notes (continued)
[3] Function descriptions (continued)
2. The triangular wave generator block (continued)
CTL 1 pin voltage
Supply voltage
VCC low voltage protection reset voltage (VCC)
Battery voltage
(VBAT)
Internal reference
voltage
Triangular wave (CT)
SS pin voltage
Error amplifier output
(EO)
Out pin waveform
Startup oscillation operation Soft start The maximum duty
Figure 1-2. The operation from startup to PWM control
Moreover, please calculate the oscillation frequency from below equation.
4 × VRT 1.09 × 1010
f [Hz]
RT × CT × (VCTH - VCTL) RT
*VRT 0.7 V, CT = 560 pF, VCTH - VCTL 0.46 V
As the above formula is intended t