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Multiscanning Color Monitor
TECHNICAL SERVICE MANUAL
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L50A(L50C)
Multiscanning Color Monitor
TECHNICAL SERVICE MANUAL
http://hyundaiQ.com http://monitor.hei.co.kr
L50A(L50C) Technical Service Manual
Safety Precaution
WARNING Service should not be attempted by anyone unfamiliar with the necessary precautions on this monitor. The followings are the necessary precautions to be observed before servicing. 1. When managing this monitor , cover with shield plate to avoid to scrach on LCD surface. 2. When replacing a chassis in the cabinet, always be certain that all the protective devices are put back in place, such as nonmetallic control knobs, insulating covers, shields, isolation resistor capacitor network etc. 3. Before returning the monitor to the customer, always perform an AC leakage current check on the exposed metallic parts of the cabinet, such as signal connectors, terminals, screw heads, metal overlays, control shafts etc, to be sure the monitor is safe to operate without danger of electrical shock.
General Information
1. Description
This 15" LCD color display monitor is operated in R, G, B drive mode input.
2. Operating instructions
2-1. Front Power Switch , Menu, Select, Down, Up, DPMS (Power) LED 2-2. Rear Input connector (AC & Signal Cable) 2-3. OSD Controls H/V Position, Clock Phase, Brightness, Contrast, Recall,Color Control, Language, Auto Adjust, Miscellaneous
3. Electrical Characteristic
3-1. Power Supply AC/DC - Input Voltage : 90V~264V Input Current : 1.0 A Max Input Ferquency : 50 ~ 60Hz - Output Voltage 12V/5V Output Vurrent 2A/2A 3-2. Video Input Signal Level : 0.7 Vp-p analog signal(at 75 ohm termination to ground) Polarity : Positive 3-3. Horizontal Synchronization Signal Level : TTL High : 2.4V min Low : 0.4V max Polarity : - or + Frequency : 31kHz ~ 60kHz 3-4. Vertical Synchronization Signal Level : TTL High : 2.4V min Low : 0.4V max Polarity : - or + Frequency : 56Hz ~ 75Hz
--1--
Control Description
Front View
LED Indicator
Soft Power Switch
Support Modes
NO 1 2 3 4 5 6 7 8 Resolution 720 x 400 640 x 480 640 x 480 800 x 600 800 x 600 1024 x 768 1024 x 768 1024 x 768 H Frequency (kHz) 31.5 31.5 37.9 37.9 46.9 48.4 56.5 60.0 V Frequency (Hz) 70.0 59.9 72.8 60.3 75.0 60.0 70.1 75.0 H Polarity 0 0 0 1 1 0 0 1 V Polarity 1 0 0 1 1 0 0 1 V Polarity 28.322 25.175 31.500 40.000 49.500 65.000 75.000 78.750
Refresh rate
70.087 59.940 72.809 60.317 75.000 60.004 70.069 75.029
--2--
L50A(L50C) Technical Service Manual
Video Input Signal
Recommended signal are shown below ·Video Signal Video level : 0 to 700mV Polarity : positive Video Input : RGB separated Analog level Sync input : H-Sync(TTL level) V-Sync (TTL level) ·Waveform Video input(R.G.B)
255 254 253 252 251
700mV
· Signal: 256 level gray scale · Linear stepping: (2.73mV ~ 256 Steps)
4 3 2 1 0 0mV
· H-Sync
ACTIVE (T4)
· V-Sync
ACTIVE (T4)
Front Porch (T5)
Period (T1) Back Porch (T3) Sync Width (T2)
Front Porch (T5)
Period (T1) Back Porch (T3) Sync Width (T2)
--3--
Video Input Terminal
A 15 Pin D-sub connector is used as the input signal connector Pin and input signals are shown in the table below.
Pin Description
SIGNAL PIN NO.
SEPARATE SYNC/ DDC 1/2B RED GREEN BLUE GND RETURN RED GROUND GREEN GROUND BLUE GROUND N.C LOGIC GROUND GROUND SDA H-SYNC(TTL) V-SYNC(VCLK) SCL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D-Sub miniature connector
--4--
L50A(L50C) Technical Service Manual
Connecting with External Equipment
Cautions Be sure to turn off the power of your computer before connecting the monitor.
--5--
Theory of Operation
1. AC/DC Adapter
Input voltage : Input current : Inrush current : 90 ~ 264 Vac, 50/60 Hz Max 1A (Vin : 90Vac , 50Hz) 15A peak (At 115Vac Max . Load) 30A peak (At 230Vac Max. Load) DC 12V 2.0A(Max) 40 - 80 KHz 5.0V
2. DC/AC INVERTER
Input voltage : Input current : Frequency(switching) : On/off control voltage :
3. DPMS MODE
Reference to DPMS files
Mode Normal Suspend off Unplugged LED Green Orange Orange Not illuminated LED Indicator 40W 10W 5W 0W
--6--
L50A(L50C) Technical Service Manual
On Screen Controls & LED Indicator
The menu for screen setting adjustment is located in the OSD and can be viewed in one of five languages OSD feature andmain funcrions are as follows:
The OSD adjustments available to you are listed below.
BRIGHTNESS
Adjust the brightness of the screen.
CONTRAST
Adjust the contrast of the screen.
COLOR CONTROL
Color temperature affects the tint of the image. With lower color temperatures the image turns reddish and with higher temperatures bluish. There are three color settings available: Mode 1(a warm white), Mode 2(a cool white) or USER. With the USER setting you can set individual values for red, green and blue.
H/V POSITION H-POSITION
Adjusts the horizontal position of the entire screen image.
V-POSITION
Adjusts the vertical position of the entire screen image.
--7--
CLOCK PHASE PHASE
Adjust the noise of the screen image.
CLOCK
Adjust the horizontal size of the entire screen image.
AUTO ADJUST
You can adjust the shape of screen automatically at the full screen pattern.
MISCELLANEOUS RECALL
Recall the saved color data.
OSD TIMER
You can set the displayed time of OSD Menu window on the screen by using this adjustment.
OSD POSITION
Adjust the OSD menu's horizontal or vertical position on the screen.
LANGUAGE
You can select the language in which adjustment menus are displayed. The following languages are available : English, French, German, Italian, Spanish, Swedish, Finnish, Danish, P
--8--
L50A(L50C) Technical Service Manual
Getting Fine Picture Step 1. At first Display, a full screen, such as, Window's background or "H" character should be achieved by using Editor (ex: Notepad. exe) Step 2. Adjust the screen to the center of the Display(LCD), by using the top and bottom display controls. (i.e.Using V-Position Adjust menu)
Step 3. Adjust the screen to the center of the Display(LCD), by using the right and left display controls. (i.e.Using Clock and H-Position adjust menu)
Step 4. Adjust the Clock-phase until the "H" Character displays clear.
Step 5. Using the Contrast. Brightness, and Color Control menu, set the color to your preference. Step 6. When you finish the adjustment, you can save your settings by pressing on the menu until the OSD screen has disappeared. Factory Setting & EEPROM Initialization Method Factory Setting Method - Connect the signal cable and power cable to the LCD monitor. - Press Power switch with pressed MENU key.(Menu key + Power key). - Then, a User can change the factory setting value in OSD menu. - Save changed value and Turn off the power s/w. - Turn on the power, adjust the screen.
--9--
Specification
SIZE Dot Pitch LCD Module Brightness Response Time Signal Input Connector H-Freq SYNC V-Freq Area Display Resolution Video Bandwidth User Control & OSD Control Power Management Plug & Play EMC Safety & Regulation Safety Ergonomi Operating Temperature Storage Operating Humidity Storage unpacked Weight packed Dimension(WXHXD mm) 4.4Kg 367X353X188.3mm 5 to 90%(Non-condensing) 3.1Kg - 5 to 45 °C 30 to 80%(Non-condensing) Color 56.0Hz ~ 75Hz 304(H)X228(V)mm 16.2M Colors 1024 X 768 @ 75Hz 80MHz Contrast,Brightness,H-V Position, Clock Phase, Color Control, Language, Auto Adjust, Miscellaneous VESA DPMS Standard VESA DDC 1/2B FCC CLASS B , CE , VCCI cULus, CE, TUV-GS, SEMKO TCO 5 to 35 °C 15 pin D-SUB Connector 31.0kHz ~ 60.0kHz 15" Viewable diagonal 0.297mm 180 cd/m2 (MIN), 250 cd/m2 (TYP) 20m- sec (Typ) R.G.B Analog
* Specification is subject to change without notice for performance improvement.
--10--
L50A(L50C) Technical Service Manual
Critical Parts Specification
1. LCD Module HT-15X13(LTM150XH-L01 is a a-si TFT active matrix color liquid crystal comprising amorphous silicon TFT attached to each signal electrode, a driving circuit and a backlight. HT-15X13(LTM150XH-L01 has a built-in backlight display area contains 1024X768 pixels and can display full color (16.2M colors) Display area 304(H)X228(V)mm Drive system a-si TFT Display color 16.2M Colors Number of Pixel 1024X768 Pixel arrangement RGB vertical strip Pixel pitch 0.297(H)X0.297(V)mm Weight 300:1 Viewing angle Horizontal: 80 degree(3' clock, 9' clock)/45(12 ' clock) 80 (6' clock) Vertical: 40 degree(12' clock) ,55 degree(6' clock)/65(3 ' clock, 9 ' clock) Response time 20ms(Typr) Luminance 250cd/m2(Typ) Signal system Digital RGB signals, Sync signals(H, V-Sync), Dot clock(DCLK) , DE(Data Enable) Supply voltage 3.3V Backlight Edge light type: Four colt cathode fluorescent lamps With in- verter Power consumption 1.5W(TYP) without B/L
--11--
2) INTERFACE CONNEXTION 2-1) Electrical Interface CN1 Interface connector : DF14H-20P-1.25H(HIROSE) or equivalent User side connector : DF14-20S-1.25C(HIROSE)or equivalent
Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Symbol VDD1 VDD2 VSS VSS RIN0RIN0+ VSS RIN0RIN0+ VSS RIN2RIN2+ VSS RCLKINRCLKIN+ VSS RIN3RIN3+ VSS NC
Pin No Power Supply : +3.3V Power Supply : +3.3V Ground Ground LVDS Negative data signal (-) LVDS Negative data signal (+) Ground LVDS Negative data signal (-) LVDS Negative data signal (+) Ground LVDS Negative data signal (-) LVDS Negative data signal (+) Ground LVDS Negative data signal (-) LVDS Negative data signal (+) Ground LVDS Negative data signal (-) LVDS Negative data signal (+) Ground Reserved
Remark
Tx pin #48 Tx pin #47
Tx pin #46 Tx pin #45
Tx pin #42 Tx pin #41
Tx pin #40 Tx pin #39
Tx pin #38 Tx pin #37
--12--
L50A(L50C) Technical Service Manual
2-2) LVDS Infcrface LVDS Transmitter : THC63LVDM83A or equivalent. Input signal R0 R1 R2 R3 R4 R5 G0 G1 G2 G3 G4 G5 B0 B1 B2 B3 B4 B5 HSYNC VSYNC DE MCLK Transmitter Pin No Pin No 51 52 54 55 56 3 4 6 7 11 12 14 15 19 20 22 23 24 27 28 30 31 40 39 R6 R7 G6 G7 B6 B7 RSVD 50 2 8 10 16 18 25 38 37 OUT+ OUTIN3IN3+ 17 18 CLKOUTCLKOUT+ CLKINCLKIN+ 14 15 42 41 OUT2OUT2+ IN2IN2+ 11 12 46 45 OUT1+ OUT1+ IN1IN1+ 8 9 48 47 OUT 0OUT + IN0IN0+ 5 6 Interface System (Tx) TFT-LCD (Rx) DF14H-20P-1.25H Pin No Remark
--13--
gmZAN1
.
Features
The gmZAN1 device utilizes Genesisķ patented thirdgeneration Advanced Image Magnification technology as well as a proven integrated ADC/PLL to provide excellent image quality within a cost-effective SVGA / XGA LCD monitor solution. As a pin-compatible replacement for the gmB120, the gmZAN1 incorporates all of the gmB120 features plus many enhanced features; including 10-bit gamma correction, Adaptive Contrast Enhancement (ACE) filtering, and an enhanced OSD.
·
Output Format
· Support for 8 or 6-bit panels (with high quality dithering) · One or two pixel output format
·
Built In High-Speed Clock Generator
· Fully programmable timing parameters · On-chip PLLs generate clocks for the on-chip ADC and pixel clock from a single reference oscillator
Features
· Fully integrated 135MHz 8-bit triple-ADC, PLL, and pre-amplifier · gmZ2 scaling algorithm featuring new Adaptive Contrast Enhancement (ACE) · On-chip programmable OSD engine · Integrated PLLs · 10-bit programmable gamma correction · Host interface with 1 or 4 data bits · Pin-compatible with gmB120
·
Auto-Configuration / Auto-Detection
· Phase and image positioning · Input format detection
·
Operating Modes
· Bypass mode with no filtering · Multiple zoom modes: with filtering with adaptive (ACE) filtering
·
Integrated On-Screen Display
· On-chip character RAM and ROM for better customization · External OSD supported for greater flexibility · Many other font capabilities including: blinking, overlay and transparency
·
Integrated Analog Front End
· · · · Integrated 8-bit triple ADC Up to 135MHz sampling rates No additional components needed All color depths up to 24-bits/pixel are supported
Package
· 160-pin PQFP
·
High-Quality Advanced Scaling
· Fully programmable zoom · Independent horizontal / vertical zoom · Enhanced and adaptive scaling algorithm for optimal image quality · Recovery Mode / Native Mode
Applications
· · Multi-synchronous LCD monitors Other fixed-resolution pixelated display devices
·
Input Format
· Analog RGB up to XGA 85Hz
--14--
L50A(L50C) Technical Service Manual
Pin Out Diagram
Figure 1. gmZAN1 Pin Diagram
OSD_DATA3 OSD_FSW MFB11 MFB10 DVDD DVSS DAC_DGNDA DAC_DVDDA PLL_DVDDA Reserved PLL_DGNDA SUB_DGNDA SUB_SGNDA PLL_SGNDA Reserved PLL_SVDDA DAC_SVDDA DAC_SGNDA SVDD SVSS TCLK XTAL (Reserved) PLL_RVDDA PLL_RGNDA Reserved SUB_RGNDA Reserved VSYNC SYN_VDD HSYNC/CS SYN_VSS Reserved STI_TM1 STI_TM2 SCAN_IN1 Reserved SCAN_IN2 SRVSS2 SCAN_OUT1 SCAN_OUT2
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
OSD_DATA2 OSD_DATA1 OSD_DATA0 OSD_CLK OSD_VREF OSD_HREF CVSS4 MFB0 MFB1 MFB2 MFB3 MFB4 CVDD4 MFB5 MFB6 MFB7 MFB8 HCLK MFB9 IRQ RESETn HDATA HFS N/C ADC_RVDDA RED+ REDADC_RGNDA ADC_GVDDA GREEN+ GREENADC_GGNDA ADC_BVDDA BLUE+ BLUEADC_BGNDA ADC_VDDA Reserved ADC_GNDA SUB_GNDA
gmZAN1 (160-Pin PQFP)
NOTE: For all power pads:
C: Core R: Ring S: From pad 125 to 132, S represents Sclk DDS (source clk) D: From pad 133 to 140, D represents Dclk DDS (destination clk)
NOTE: SRVSS1, SRVSS2 are connected to core VSS and SRVDD1 and SRVDD2 are connected to core VDD. NOTE: The following signals have the same function but different nam es in the gmB120 datasheet:
OSD-HREF is here called OSD_HREF OSD-VREF is here called OSD_VREF OSD-CLK is here called OSD_CLK OSD-DATA0 is here called OSD_DATA0 OSD-DATA1 is here called OSD_DATA1 OSD-DATA2 is here called OSD_DATA2 OSD-DATA3 is here called OSD_DATA3 SYVDD is here called SYN_VDD SYVSS is here called SYN_VSS
NOTE: when connected to a pull-down resistor, the MFB5 strapping option (sampled at reset) enables the use of an external crystal. MFB5 has an internal pull-up resistor, so an external oscillator is the default. NOTE: MFB6 is a strapping option to select a host data bus width of four when connected to a pull-down (sampled at reset). Since MFB6 has an internal pull-up resistor, a 1-wire host bus width is the default.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
ADC_GND1 ADC_VDD1 ADC_GND2 ADC_VDD2 PPWR PBIAS PHS PVS CVSS3 PD0 PD1 PD2 PD3 PD4 PD5 RVDD3 PD6 PD7 PD8 RVSS4 Reserved Reserved CVDD2 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 RVSS3 PD17 PD18 PD19 PCLKB PCLKA PDISPE PD20 CVSS2
CVSS1 Reserved PSCAN Reserved Reserved PD47 PD46 RVSS1 PD45 PD44 SRVDD1 RVDD1 PD43 PD42 PD41 PD40 PD39 SRVSS1 PD38 PD37 SRVDD2 PD36 PD35 PD34 PD33 PD32 PD31 PD30 PD29 RVSS2 PD28 PD27 RVDD2 PD26 PD25 PD24 PD23 PD22 PD21 CVDD1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
--15--
FEATURES MTV312M64
· · · · · · · · · · · · · · ·
8051 core, 12MHz operating frequency with double CPU clock option 0.35uM process; 5V/3.3V power supply and I/O; 3.3V core operating 1024-byte RAM; 64K-byte program Flash-ROM support In System Programming (ISP) Maximum 14 channels of PWM DAC Maximum 31 I/O pins SYNC processor for composite separation/insertion, H/V polarity/frequency check and polarity adjustment Built-in low power reset circuit Built-in self-test pattern generator with four free-running timings Compliant with VESA DDC1/2B/2Bi/2B+ standard Dual slave IIC addresses; H/W auto transfer DDC1/DDC2x data Single master IIC interface for internal device communication Maximum 4-channel 6-bit ADC Watchdog timer with programmable interval Flash-ROM program code protection selection 40-pin DIP, 42-pin SDIP or 44-pin PLCC package
GENERAL DESCRIPTIONS
The MTV312M micro-controller is an 8051 CPU core embedded device especially tailored for CRT/LCD Monitor applications. It includes an 8051 CPU core, 1024-byte SRAM, 14 built-in PWM DACs, VESA DDC interface, 4-channel A/D converter, and a 64K-byte internal program Flash-ROM.
BLOCK DIAGRAM
P1.0-7 P3.0-2 P3.4-5 P0.0-7 P2.0-3 RD WR ALE INT1 P0.0-7 P2.0-3 RD WR ALE INT1
XFR
AUXRAM& DDCRAM
8051 CORE
RST X1 X2
AD0-3
ADC
H/VSYNC CONTROL
HSYNC VSYNC HBLANK VBLANK ISCL ISDA HSCL HSDA
PWM DAC
P6.0-7 P5.0-6 P4.0-2
AUX I/O
DA0-13
DDC& IIC INTERFACE
--16--
L50A(L50C) Technical Service Manual
PIN CONNECTION
DA2/P5.2 DA1/P5.1 DA0/P5.0 VDD3 VDD VSS X2 X1 ISDA/P3.4/T0 ISCL/P3.5/T1 STOUT/P4.2 P6.2/AD2/HLFHI P1.0 P1.1 P3.2/INT0 P1.2 P1.3 P1.4 P1.5 P1.6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
MTV312M 40 Pin PDIP
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VSYNC HSYNC DA3/P5.3 DA4/P5.4 DA5/P5.5 DA8/HLFHO DA9/HALFV HBLANK/P4.1 VBLANK/P4.0 DA7/HCLAMP DA6/P5.6 RST P6.6/DA12 P6.5/DA11 P6.4/DA10 HSCL/P3.0/Rxd HSDA/P3.1/Txd P6.0/AD0 P6.1/AD1 P1.7
DA2/P5.2 DA1/P5.1 DA0/P5.0 VDD3 NC NC RST VDD VSS X2 X1 ISDA/P3.4/T0 ISCL/P3.5/T1 STOUT/P4.2 P6.2/AD2/HLFHI P1.0 P1.1 P3.2/INT0 P1.2 P1.3 P1.4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
MTV312M 42 Pin SDIP
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
VSYNC HSYNC DA3/P5.3 DA4/P5.4 DA5/P5.5 DA8/HLFHO DA9/HALFV HBLANK/P4.1 VBLANK/P4.0 DA7/HCLAMP DA6/P5.6 P6.6/DA12 P6.5/DA11 P6.4/DA10 HSCL/P3.0/Rxd HSDA/P3.1/Txd P6.0/AD0 P6.1/AD1 P1.7 P1.6 P1.5
DA0/P5.0 VDD3 NC NC RST VDD P6.3/AD3 VSS X2 X1 ISDA/P3.4/T0 ISCL/P3.5/T1 STOUT/P4.2 P6.2/AD2/HLFHI P1.0 7 8 9 10 11 12 13 14 15 16 17
MTV312M 44 Pin PLCC
DA2/P5.2 DA1/P5.1
DA5/P5.5 DA4/P5.4 DA3/P5.3 HSYNC VSYNC 39 38 37 36 35 34 33 32 31 30 29 DA8/HLFHO DA9/HALFV HBLANK/P4.1 VBLANK/P4.0 DA7/HCLAMP DA6/P5.6 P6.7/DA13 P6.6/DA12 P6.5/DA11 P6.4/DA10 HSCL/P3.0/Rxd HSDA/P3.1/Txd P6.0/AD0 P6.1/AD1 P1.7 P1.6
40 41 42 43 44 1 2 3 4 5 6 28 27 26 25 24 23 22 21 20 19 18 P1.5 P1.4 P1.3 P1.2 P3.2/INT0 P1.1
--17--
PIN CONFIGURATION
A ģCMOS output pinī means it can sink and drive at least 4mA current. It is not recommended to use such pin as input function. A ģopen drain pinī means it can sink at least 4mA current but only drive 10~20uA to VDD. It can be used as input or output function and needs an external pull up resistor. A ģ8051 standard pinī is a pseudo open drain pin. It can sink at least 4mA current when output is at low level, and drives at least 4mA current for 160nS when output transits from low to high, then keeps driving at 100uA to maintain the pin at high level. It can be used as input or output function. It needs an external pull up resistor when driving heavy load device.
4mA
10uA
120uA
2 OSC period delay 4mA Output Data Input Data
8051 St andard Pin
Pin
4mA No Current
Output Data 4mA
Pin Input Data 4mA Output Data Pin
CMOS Output Pin
Open Drain Pin
POWER CONFIGURATION
The MTV312M can work on 5V or 3.3V power supply system. In 5V power system, the VDD pin is connected to 5V power and the VDD3 needs an external capacitor, all output pins can swing from 0~5V, input pins can accept 0~5V input range. And ADC conversion range is 5V. However, X1 and X2 pins must be kept below 3.3V. In 3.3V power system, the VDD and VDD3 are connected to 3.3V power, all output pins swing from 0~3.3V, HSYNC, VSYNC and open drain pin can accept 0~5V input range, other pins must be kept below 3.3V. And the ADC conversion range is 3.3V.
5V VDD VDD3 10u 3.3V VDD VDD3
MTV312M in 5V System
MTV312M in 3.3V System
--18--
L50A(L50C) Technical Service Manual
CS5828
GENERAL DESCRIPTION The CS5828 receives four sets of 7-bit data in CMOS logic level and converts them into four lowvoltage differential signaling (LVDS) serial channels. The 7-bit input data is referenced to the CKIN signal. The RF pin selects either rising or falling edge trigger of CKIN. Parallel to serial conversion is performed by a 7X internal generated clock reference using onchip PLL using CKIN. A copy of CKIN but phaselocked to the output serial streams, CLKOUT, is also converted to the fifth LVDS channel. The CS5828 offers a reliable communication media using LVDS signaling and provides low EMI dealing with wide, high-speed TTL interfaces. This is especially attractive for interfaces between GUI controller and display systems such as LCD panels for SVGA/XGA/SXGA applications. BLOCK DIAGRAM
D0,D1,D2,D3, D4,D6,D7
DIN
FEATURES
· · · · · · · · · · ·
Four 7-bit serial and one clock LVDS channels. Compatible with ANSI TIA/EIA-644 LVDS standard. Wide CKIN ranges from 31MHz to 85MHz. Fully integrated on-chip PLL that provides 7X CKIN serial shift clock. Pin selectable for rising or falling edge trigger. Support power-down mode. 5V/3.3V tolerant data input. Single 3.3V supply operation. CMOS low power consumption. Functional compatible with DS90C385. Available in 56-pin TSSOP package.
SHIFT/LOAD_N CLK
PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER EN
Y0P Y0N
D8,D9,D12,D13, D14,D15,D18
DIN
SHIFT/LOAD_N CLK
PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER
Y1P EN Y1N
D19,D20,D21,D22, D24,D25,D26
DIN
PARALLEL-IN SERIAL-OUT EN
Y2P Y2N
SHIFT/LOAD_N 7-Bit SHIFT REGISTER CLK
D27,D5,D10,D11, D16,D17,D23
DIN
SHIFT/LOAD_N CLK
PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER
Y3P EN Y3N
RF CKIN
7xCLK PHASE LOCK LOOP SHIFT/LOAD_N R/F CLK
CKOP EN CKON
SHTDN
CONTROL LOGIC
CS5828
--19--
PIN CONNECTION DIAGRAM
VDD D5 D6 D7 VSS D8 D9 D10 VDD D11 D12 D13 VSS D14 D15 D16 RF D17 D18 D19 VSS D20 D21 D22 D23 VDD D24 D25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
D4 D3 D2 VSS D1 D0 D27 LVDS_VSS Y0M Y0P Y1M Y1P LVDS_VDD LVDS_VSS Y2M Y2P CKOM CKOP Y3M Y3P LVDS_VSS PLL_VSS PLL_VDD PLL_VSS SHTDN CKIN D26 VSS
CS5828
Figure-1 56-pin TSSOP
--20--
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5
5
L50C(S527B/L550B/L1510B) Schematic
4
4
CONTENTS SCHEMATIC 1. Contents, Revision History 2. gmZAN1/2 3. MCU(MTV312M) 4. LVDS & Power 5. BLOCK DIAGRAM 3 4 5 SHEET 1 2
REVISION HISTORY Date
01.09.04 01.09.20 01.10.10 01.10.23 01.11.29
Author
G.H.NAM W.S.IM W.S.IM E.J.NAM E.J.NAM
Ver A B C D E
Comments Initial release ver A L50C VP L50C VP-A
3
3
L50C VP-B S527 NOISE SOLUTION
2
2
1
1
Title Size B Date:
A B C D
Document Number NONE
1. Contents
Thursday, November 29, 2001 Sheet
E
Rev E 1 of 5
5
4
3
2
1
+3.3V DVDDA C201 22uF/16V C203 0.1uF C204 0.1uF +3.3V
3.3 DIGITAL SUPPLY DECOUPLING
C210 SVDDA C206
D
C211 0.1uF
C213 0.1uF
C214 0.1uF
C216 0.1uF
C218 0.1uF
C221 0.1uF
22uF/16V
C207 0.1uF
C208 0.1uF GND ZAN1_3.3V/ ZAN2_2.5V RVDDA
D
22uF/16V +5V C223 22uF/16V
KDS226 SOT23
KDS226 SOT23
KDS226 SOT23
C224 0.1uF C202 VDDA 0.1uF C229 0.1uF GND ZAN1_3.3V/ ZAN2_2.5V C205 0.1uF C200 22uF/16V
D205
D206
D207
3.3 DIGITAL SUPPLY DECOUPLING
C225
C226 0.1uF
C227 0.1uF
C228 0.1uF
ANALOG SUPPLY DECOUPLING
22uF/16V
VGA INPUT CONNECTOR
CN200 11 VGA_SDA VGA_HSYNC VGA_VSYNC VGA_SCL 12 13 14 15 DB15HD 1 6 2 7 3 8 4 9 5 10
GND GND
GND C212 C215 0.1uF C217 0.1uF C219 0.1uF C220 0.1uF C222 0.1uF C209 22uF/16V
RED GREEN BLUE
R200 R201 R202
100 100 100
C230 C231 C232
0.01uF 0.01uF
0.1uF
GND 0.01uF 143 137 136 129 128 125 139 96 92 88 84 79 77 11 21 58 12 33 40 60 65 RVDD1 RVDD2 RVDD2A RVDD2B RVDD3 U200 R204 75 R205 75 R206 75 R207 R208 100 100 C234 C235 0.01uF 0.01uF RED+ GREEN+ BLUE+ REDGREENBLUE95 91 87 94 90 86 2 4 14 1 U203A 14 U203B 4 74LCX14 SO14 0 152 156 14 6 74LCX14 SO14 7 7 9 U203D 8 74LCX14 SO14 X200 C241 C242 R220 GND 0 20MHz R218 0 5pF 5pF 153 154 155 157 159 160 3 115 116 117 118 119 120 121 122 98 103 99 100 101 113 112 111 110 109 107 106 105 104 102 124 123 150 148 141 142 7 83 97 130 135 145 RESERVED N/C RESERVED RESERVED RESERVED RESERVED RESERVED HSYNC/CS VSYNC TCLK XTAL/RESERVED STI_TM1 STI_TM2 SCAN_IN1 SCAN_IN2 SCAN_OUT1 SCAN_OUT2 PSCAN OSD_HREF OSD_VREF OSD_CLK OSD_DATA0 OSD_DATA1 OSD_DATA2 OSD_DATA3 OSD_FSW HFS HCLK HDATA RESETn IRQ MFB0 MFB1 MFB2 MFB3 MFB4 MFB5 MFB6 MFB7 MFB8 MFB9 MFB10 MFB11 RED+ GREEN+ BLUE+ REDGREENBLUERESERVED RESERVED 108 149 CVDD4 SYN_VDD
ADC_RVDDA ADC_GVDDA ADC_BVDDA ADC_VDDA
PLL_RVDDA DAC_SVDDA PLL_SVDDA PLL_DVDDA DAC_DVDDA
ADC_VDD1 ADC_VDD2
R203
100
C233
0.01uF
SRVDD1 SRVDD2 CVDD2
DVDD SVDD
C
PD[0..5] PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 PD32 PD33 PD34 PD35 PD36 PD37 PD38 PD39 PD40 PD41 PD42 PD43 PD44 PD45 PD46 PD47 PCLKA PCLKB PDISPE PVS PHS PPWR PBIAS 71 70 69 68 67 66 64 63 62 57 56 55 54 53 52 51 50 48 47 46 42 39 38 37 36 35 34 32 31 29 28 27 26 25 24 23 22 20 19 17 16 15 14 13 10 9 7 6 44 45 43 73 74 76 75 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17
PD[0..5]
SHEET 4
C
GND VGA_CON SHEET 3 GND +5V D208 6.2V GND R209 22
PD[6..11]
PD[6..11]
SHEET 4
PD[12..17]
PD[12..17]
SHEET 4
U203A NC
2 74LCX14 SO14 7 R219 3
C243 NC
REV. E
GND R210 22 14 5 U203C
D203 6.2V SOT23
D202 6.2V SOT23 GND
C240 47pF
REV. E
B
R211 NC
R211 0
Default R218
+5V GND D204 R212 47K R214 R215 100 100 VGA_SCL VGA_SDA D200 6.2V SOT23 D201 GND 6.2V SOT23 SHEET 3 SHEET 3 SHEET 3 HDATAF1 HDATAF2 HDATAF3 MFB7 MFB8 MFB9 R213 U202 47K 8 7 6 5 VCC NC VCLK NC SCL NC SDA GND 1 2 3 4 0.1uF RLS4148 C239 SHEET 3 SHEET 3 SHEET 3 SHEET 3 SHEET 3 SHEET 3 SHEET 3 SHEET 3 SHEET 3 HFS HCLK HDATAF0 ZAN_RST /IRQ MENU SELECT KEY_DOWN KEY_UP HFS HCLK HDATA0 RESETn IRQ MFB0 MFB1 MFB2 MFB3
PD36 PD37 PD38 PD39 PD40 PD41
PD36 PD37 PD38 PD39 PD40 PD41
SHEET 4 SHEET 4 SHEET 4 SHEET 4 SHEET 4 SHEET 4
B
PCLKA PDISPE PVS PHS
PCLKA PDISPE PVS PHS
SHEET 4 SHEET 4 SHEET 4 SHEET 4
24LC21 8P SOIC
ADC_RGNDA ADC_GGNDA ADC_BGNDA
DAC_DGNDA PLL_DGNDA PLL_SGNDA DAC_SGNDA PLL_RGNDA
127 131 134 138 144
93 89 85
10K
A
10K
gmZAN1/gmZAN2
82 81 80 78
R217
R216
1 5 8 18 30 41 49 59 61 72 114 126 140 147 151 158
CVSS1 CVSS1A RVSS1 SRVSS1 RVSS2 CVSS2 RVSS3 CVSS2A RVSS4 CVSS3 CVSS4 DVSS SVSS CVSS5 SYN_VSS SRVSS2
GND
133 SUB_SGNDA 132 SUB_DGNDA 146 SUB_RGNDA
ADC_GNDA SUB_GNDA ADC_GND1 ADC_GND2
A
GND
GND GND GND GND GND
NOTE:
ANALOG AND DIGITAL GROUNDS MUST BE INTERCONNECTED AT A SINGLE POINT
Title Size C Date:
5 4 3 2
2. gmZAN2
Document Number NONE Thursday, November 29, 2001
1
Rev E Sheet 2 of 5
5
4
3
2
1
+5V
D D
R315 10K GND CN301 8 7 6 5 4 3 2 1 HEADER 8 10uF/16V GND GND +5V 44 43 42 41 +5V
C
C313 0.1UF
R321 R322 R312 R313 R323 R324
10K 10K 330 330 10K 10K
R319 R314
470 470
LED_ORANGE_EN LED_GRN_EN KEY_UP KEY_DOWN SELECT KEY_UP KEY_DOWN SELECT MENU SHEET 2 SHEET 2 SHEET 2 SHEET 2
C305
C314 0.1uF GND
C315 0.1uF
C316 0.1uF
C317 0.1uF
C318 0.1uF
C319 0.1uF
40
6
5
4
3
2
1
U303
VSYNC
DA0/P5.0
DA1/P5.1
DA2/P5.2
HSYNC
VDD3
DA3/P5.3
DA4/P5.4
DA5/P5.5
NC
NC
+5V
C
D301 RLS4148
C304 10uF/16V 7 8 9 10 11 RST VDD P6.3/AD3 VSS X2 X1 ISDA/P3.4/T0 ISCL/P3.5/T1 STOUT/P4.2 P6.2/AD2/HLFHI P1.0 P3.2/INTO
DA8/HALFH DA9/HALFV HBLANK/P4.1
39 38 37 36
R309 R308 R310 R334
4.7K +12V 4.7K 4.7K CN302 10K 1 2 3 4 5 6 HEADER 6 C309 1uF/50V
X300 +5V 12MHz R300 U301 1 2 3 4 A0 A1 A2 VSS VCC WP SCL SDA 8 7 6 5 10K R301 10K GND C308 18pF C307 18pF
12 13 14 15 16 17
MTV312M 44Pin PLCC
VBLANK/P4.0 DA7/HCLAMP DA6/P5.6 P6.7/DA13 P6.6/DA12 P6.5/DA11 P6.4/DA10 P3.0/Rxd P6.1/AD1 P6.0/AD0 P3.1/Txd
35 34 R307 33 32 31 30 29 GND GND PWM_BRIGHT 1K
INVERTER CONNECTOR
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
SHEET 4
PANEL_POWER +5V MTV312M R302 R303 R304 R306 R305 10K 10K 10K 10K 10K
P1.7
24LC08SOIC
VGA_CON MUTE
SHEET 2
18
19
20
21
22
23
24
25
26
27
GND
B
28
B
+5V HDATAF0 HDATAF1 HDATAF2 HDATAF3 HDATAF[0..3] SHEET 2
C300 10uF/16V
C301 0.1uF
C302 0.1uF
C303 0.1uF
C306 0.1uF
HCLK GND HFS ZAN_RST /IRQ LVDS_EN
SHEET 2 SHEET 2 SHEET 2 SHEET 2 SHEET 4 +5V +12V
CN303 1 2 3 4 5
HEADER 7 GND
A
Only L1510B
A
Title Size C Date:
5 4 3 2
3. MCU(MTV312M)
Document Number NONE Thursday, November 29, 2001
1
Rev E Sheet 3 of 5
5
4
3
2
1
1pxl/clk
SHEET 2 SHEET 2
D
PD36 PD37 PD[0..5] PD[0..5]
SHEET 2
PD36 PD37 PD0 PD1 PD2 PD3 PD4 PD5 LVDS_3.3V
D
RED
SHEET 2 SHEET 2 SHEET 2 PD38 PD39 PD[6..11] PD[6..11]
U403 PD38 PD39 PD6 PD7 PD8 PD9 PD10 PD11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VCC TD1 TA5 TA6 GND TB0 TB1 TD2 VCC1 TD3 TB2 TB3 GND1 TB4 TB5 TD4 R/F TD5 TB6 TC0 GND2 TC1 TC2 TC3 TD6 VCC2 TC4 TC5 TA4 TA3 TA2 GND3 TA1 TA0 TD0 LVDSGND TATA+ TBTB+ LVDSVCC LVDSGND1 TCTC+ TCLKTCLK+ TDTD+ LVDSGND2 PLLGND PLLVCC PLLGND1 /PDWN CLKIN TC6 GND4 CS5824 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 C401 0.1uF C402 0.1uF C400 0.1uF C404 0.1uF C403 0.1uF
GREEN
SHEET 2 SHEET 2 SHEET 2 PD40 PD41 PD[12..17] PD[12..17]
RX0RX0+ RX1RX1+ RX2RX2+ RXCLKRXCLK+ RX3RX3+ SPLL-VCC SPLL-GND SLVDSPDN STTL-GND
RX0RX0+ RX1RX1+ RX2RX2+ RXCLKRXCLK+ RX3RX3+
GND
PD40 PD41 PD12 PD13 PD14 PD15 PD16 PD17 SO-TD6
BLUE
C
LVDS_EN
SHEET 3
C
SLVDSR/F SHEET 2 SHEET 2 SHEET 2 SHEET 2 PHS PVS PDISPE PCLKA PHS PVS PDISPE PCLKA R402 33 R403 33 R404 33 R405 33 R400 1K R401 1K C419 33pF C420 33pF
PANEL_3.3V
C421 33pF
C422 33pF
SHEET 2
PANEL_POWER
R406
4.7K
U404 1 2 3 4 GND C423 100uF/16V CN400 POWER +5V 1 12V C410 3 GND
B
S S S G
D D D D
8 7 6 5
C426 100uF/16V GND
C424 0.1uF GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 GND CN401 VDD VDD GND GND RX0RX0+ GND RX1RX1+ GND RX2RX2+ GND RXCLKRXCLK+ GND RX3RX3+ GND NC DF-14A-20P-1.25H
C425 0.1uF
SI4435 SO8
U401 ZAN1 RC1117_3.3 / ZAN2 RC1117_2.5 3 C409 0.1uF SOT223 VIN VOUT GND 1 2 C412 0.1uF
ZAN1_3.3V / ZAN2_2.5V GND
RX0RX0+ RX1RX1+ RX2RX2+ RXCLKRXCLK+ RX3RX3+
RX0RX0+ RX1RX1+ RX2RX2+ RXCLKRXCLK+ RX3RX3+
2 4
5V
C411 22uF/16V
22uF/16V GND 5 5V 6 12V GND GND
B
GND
GND
GND
U400 RC1117.3.3 GND 3 +12V C405 22uF/16V C406 0.1uF SOT223 VIN VOUT GND 1 2 C408 0.1uF
+3.3V
C407 22uF/16V
GND
GND
GND
GND
GND
LVDS_3.3V U402 RC1117.3.3 3 C413
A
PANEL_3.3V
VIN
VOUT GND
2 C416 0.1uF C414
A
C415 0.1uF SOT223
22uF/16V
1
22uF/16V
GND
GND
GND
GND
GND Title Size C Date:
4. LVDS & POWER Document Number
NONE Thursday, November 29, 2001
1
Rev E 4 of 5
Sheet
5
4
3
2
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