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INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:
· The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC · The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

HEF4505B LSI 64-bit, 1-bit per word random access read/write memory
Product specification File under Integrated Circuits, IC04 January 1995

Philips Semiconductors

Product specification

64-bit, 1-bit per word random access read/write memory
DESCRIPTION The HEF4505B is a 64-bit, 1-bit per word, fully decoded and completely static, random access memory. The memory is strobed for reading or writing only when the strobe input (ST), chip enable inputs (CE1 and CE2) are HIGH simultaneously. The output data is available at the data output (DOUT) only when the memory is strobed, the read/write input (R/W) is HIGH and after the read access time has passed. Note that the three-state output is initially disabled and always goes to the LOW state before data is valid. The output is disabled in the high-impedance OFF-state, when the memory is not strobed or R/W is LOW. R/W may remain HIGH during a read cycle or LOW during a write cycle. The output data has the same polarity as the input data. HEF4505BP(N): HEF4505BD(F):

HEF4505B LSI

Fig.1 Pinning diagram.

14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73)

( ): Package Designator North America PINNING A0 to A5 CE1, CE2 R/W ST DIN DOUT FUNCTION TABLE ST, CE1, CE2 R/W L H L H Note 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) Z = high-impedance OFF-state L L H H Z Z Z equal to memory data DOUT MODE disabled write disabled read address inputs chip enable inputs read/write input strobe input data input data output Note 1. Minimum standby voltage for data retention is 3 V. FAMILY DATA, IDD LIMITS category LSI See Family Specifications SUPPLY VOLTAGE RATING -0,5 to +15 OPERATING 4,5 to 15 V

January 1995

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64-bit, 1-bit per word random access read/write memory HEF4505B LSI

Philips Semiconductors

Product specification

64-bit, 1-bit per word random access read/write memory
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns VDD V Minimum strobe pulse width; LOW 5 10 15 5 Read cycle time 10 15 5 Write cycle time 10 15 5 Read access time 10 15 5 Address recovery time 10 15 5 Read recovery time 10 15 5 Write recovery time 3-state propagation delays 5 Output disable times Set-up times An ST 10 15 5 10 15 5 R/W ST 10 15 5 DIN ST 10 15 5 R/W ST 10 15 tsuW tsuD tsuR tsuA tPHZ, tPLZ -20 -10 -5 -30 -15 -5 160 75 45 240 100 75 105 60 55 -40 -20 -10 -60 -30 -10 80 35 20 120 50 35 210 125 115 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 15 tWR tRR tAR 80 40 25 180 120 90 75 45 40 tACC tWC tRC tSTL SYMBOL MIN. TYP. MAX. 75 45 30 35 22 15 350 250 210 220 125 75 330 135 100 40 20 10 90 60 45 35 25 20 700 500 420 440 250 150 660 270 200 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

HEF4505B LSI

TYPICAL EXTRAPOLATION FORMULA

303 ns + (0,55 ns/pF) CL 124 ns + (0,23 ns/pF) CL 92 ns + (0,16 ns/pF) CL

January 1995

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Philips Semiconductors

Product specification

64-bit, 1-bit per word random access read/write memory
VDD V Hold time DIN ST 5 10 15 tholdD SYMBOL MIN. TYP. MAX. -20 5 10 -40 -10 0 ns ns ns

HEF4505B LSI
TYPICAL EXTRAPOLATION FORMULA

(1) Output in high impedance OFF-state. (2) tSTHmin = tRCmax - tSTLmin.

Fig.3 Read cycle timing diagram.

January 1995

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Philips Semiconductors

Product specification

64-bit, 1-bit per word random access read/write memory

HEF4505B LSI

(1) tSTHmin = tWCmax - tSTLmin.

Fig.4 Write cycle timing diagram.

January 1995

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Philips Semiconductors

Product specification

64-bit, 1-bit per word random access read/write memory
APPLICATION INFORMATION

HEF4505B LSI

Fig.5 256-word by n-bit static read/write memory using HEF4505B ICs.

January 1995

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Philips Semiconductors

Product specification

64-bit, 1-bit per word random access read/write memory
Figure 5 shows a 256-word by n-bit static RAM system. The outputs of the four HEF4505B circuits are tied together to form 256 words by 1-bit. Additional bits are attained by paralleling the inputs in groups of four. Memories of larger words can be attained by decoding the most significant bits of the address and AND-ing them with the strobe input. Fan-in and fan-out of the memory are limited only by speed requirements. The extremely low input and output leakage currents keep the output voltage levels from changing significantly as more outputs are tied together. With the output levels independent of fan-out, most of the power supply range is available as logic swing, regardless of the number of units wired together. As a result, high noise immunity is maintained under all conditions.

HEF4505B LSI
The memory system shown in Fig.5 can be interfaced directly with other ICs of the LOCMOS HE family. No external components are required. Non-volatile information storage is allowed due to very low power dissipation when the memory is powered by a small standby battery. Figure 6 shows an optional standby power supply circuit for making a LOCMOS memory `non-volatile'. When the usual power fails, a battery is used to sustain operation or maintain stored information. While normal power supply voltage is present, the battery is trickle-charged through a resistor (R) which sets the charging rate. In Fig.6 the sustaining voltage is VB, and + V is the ordinary voltage from a power supply. VDD is connected to the power supply pin of the memory. Low-leakage diodes are recommended to conserve battery power.

Fig.6 Standby battery circuit.

January 1995

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