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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA
MC14506UB Dual 2-Wide, 2-Input Expandable AND-OR-INVERT Gate
The MC14506UB is an expandable AND­OR­INVERT gate with inhibit and 3­state output. The expand option allows cascading with any other gate, which may be carried as far as desired as long as the propagation delay added with each gate is considered. For example, the second AOI gate in this device may be used to expand the first gate, giving an expanded 4­wide, 2­input AOI gate. This device is useful in data control and digital multiplexing applications. · · · · · 3­State Output Separate Inhibit Line Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low­Power TTL Loads or One Low­Power Schottky TTL Load Over the Rated Temperature Range
L SUFFIX CERAMIC CASE 620

P SUFFIX PLASTIC CASE 648

D SUFFIX SOIC CASE 751B

ORDERING INFORMATION
MC14XXXUBCP MC14XXXUBCL MC14XXXUBD Plastic Ceramic SOIC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Parameter DC Supply Voltage Value Unit V V mA mW ­ 0.5 to + 18.0 Vin, Vout Iin, Iout PD Tstg TL Input or Output Voltage (DC or Transient) Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature Lead Temperature (8­Second Soldering) ­ 0.5 to VDD + 0.5 ± 10 500 ­ 65 to + 150 260

TA = ­ 55° to 125°C for all packages.

_C _C

* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: ­ 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: ­ 12 mW/_C From 100_C To 125_C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

v

v

TRUTH TABLE
A B C D E Inhibit Disable 0 0 0 0 0 X X X 1 X 0 0 0 0 0 0 0 0 0 1 Z 1 1 1 1 1 0 0 0 0 High Impedance 0 0 0 X 0 X X 0 0 1 X X 0 0 X 0 X X 1 X 0 X 0 X 0 X 1 X 1 1 1 1 1 X X 0

LOGIC DIAGRAM
AA BA CA DA EA 1 2 3 4 5

15 ZA

INH 6 DIS 14 EB 13 DB 12 CB 11 BB 10 AB 9 3­STATE OUTPUT DISABLE

VDD = PIN 16 VSS = PIN 8

X 1 X X

X X X X X X X X X X X = Don't Care

7 ZB

Z = (AB + CD + E + I)

REV 3 1/94

©MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995

MC14506UB 1

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 ­ 3.0 ­ 0.64 ­ 1.6 ­ 4.2 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- ± 0.1 -- 1.0 2.0 4.0 ­ 2.4 ­ 0.51 ­ 1.3 ­ 3.4 0.51 1.3 3.4 -- -- -- -- -- ­ 4.2 ­ 0.88 ­ 2.25 ­ 8.8 0.88 2.25 8.8 ± 0.00001 5.0 0.002 0.004 0.006 -- -- -- -- -- -- -- ± 0.1 7.5 1.0 2.0 4.0 ­ 1.7 ­ 0.36 ­ 0.9 ­ 2.4 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- ± 1.0 -- 30 60 120 mAdc 4.0 8.0 12.5 -- -- -- 4.0 8.0 12.5 2.75 5.50 8.25 -- -- -- 4.0 8.0 12.5 -- -- -- mAdc Min -- -- -- ­ 55_C 25_C 125_C Max Min -- -- -- Typ # 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.0 2.0 2.5 0.05 0.05 0.05 -- -- -- 1.0 2.0 2.5 0.05 0.05 0.05 -- -- -- 1.0 2.0 2.5 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Three­State Leakage Current VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Cin IDD µAdc pF µAdc IT IT = (0.6 µA/kHz) f + IDD IT = (1.1 µA/kHz) f + IDD IT = (1.7 µA/kHz) f + IDD µAdc ITL 15 -- ± 0.1 -- ± 0.0001 ± 0.1 -- ± 3.0 µAdc #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL ­ 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD ­ VSS) in volts, f in kHz is input frequency, and k = 0.002.

PIN ASSIGNMENT
AA BA CA DA EA INH ZB VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD ZA DISABLE EB DB CB BB AB

MC14506UB 2

MOTOROLA CMOS LOGIC DATA

Vout , OUTPUT VOLTAGE (Vdc)

Vout , OUTPUT VOLTAGE (Vdc)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Data Propagation Delay Time tPLH = (1.7 ns/pF) CL + 210 ns tPLH = (0.66 ns/pF) CL + 77 ns tPLH = (0.5 ns/pF) CL + 50 ns tPHL = (1.7 ns/pF) CL + 185 ns tPHL = (0.66 ns/pF) CL + 62 ns tPHL = (0.5 ns/pF) CL + 40 ns Expand Propagation Delay Time tPLH = (1.7 ns/pF) CL + 95 ns tPLH = (0.66 ns/pF) CL + 42 ns tPLH = (0.5 ns/pF) CL + 25 ns tPHL = (1.7 ns/pF) CL + 115 ns tPHL = (0.66 ns/pF) CL + 47 ns tPHL = (0.5 ns/pF) CL + 30 ns Inhibit Propagation Delay Time tPLH = (1.7 ns/pF) CL + 135 ns tPLH = (0.66 ns/pF) CL + 67 ns tPLH = (0.5 ns/pF) CL + 40 ns tPHL = (1.7 ns/pF) CL + 145 ns tPHL = (0.66 ns/pF) CL + 62 ns tPHL = (0.5 ns/pF) CL + 35 ns 3­State Propagation Delay Time "1" to High Impedance Symbol VDD 5.0 10 15 5.0 10 15 tPHL 5.0 10 15 5.0 10 15 tPHL 5.0 10 15 5.0 10 15 tPHL 5.0 10 15 5.0 10 15 tPLZ 5.0 10 15 5.0 10 15 5.0 10 15 Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ # 100 50 40 295 110 75 270 95 65 180 75 50 200 80 55 220 100 65 230 95 60 60 45 35 90 55 40 110 50 40 170 70 50 Max 200 100 80 580 225 180 480 175 140 430 160 125 330 110 90 500 225 160 400 175 150 150 110 90 225 140 100 300 125 100 425 175 125 ns ns ns ns Unit ns tTLH, tTHL tPLH ns tPLH ns tPLH ns tPHZ ns "0" to High Impedance High Impedance to "1" tPZH ns High Impedance to "0" tPZL ns * The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" Is not to be used for design purposes but is intended as an indication of the IC's potential performance. 16 14 12 10 8.0 6.0 a 4.0 b 2.0 0 0 2.0 4.0 6.0 8.0 10 Vin, INPUT VOLTAGE (Vdc) c a b c 5.0 Vdc a b c 10 Vdc UNUSED INPUTS CONNECTED TO VSS a b c TA = + 125°C TA = + 25°C TA = ­ 55°C 12 14 16 VDD = 15 Vdc 16 14 12 10 8.0 6.0 10 Vdc a b c 5.0 Vdc 4.0 a b c 2.0 0 0 2.0 4.0 6.0 8.0 10 12 14 16 Vin, INPUT VOLTAGE (Vdc) A AND B CONNECTED TO Vin ENABLE INPUT CONNECTED TO VDD. OTHER INPUTS CONNECTED TO VSS. VDD = 15 Vdc a a TA = + 125°C b TA = + 25°C c TA = ­ 55°C b c

(a) Expand Inputs Figure 1. Typical Voltage Transfer Characteristics MOTOROLA CMOS LOGIC DATA

(b) Data Inputs

MC14506UB 3

VDD 16 INH AA BA CA DA EA AB BB CB DB EB DIS 8 ZA VOH INH AA BA CA DA EA AB BB CB DB EB DIS 8

VDD 16 ZA VOL

IOH

IOL

EXTERNAL POWER SUPPLY

EXTERNAL POWER SUPPLY

ZB VSS

ZB VSS

Figure 2. Typical Output Source Characteristics Test Circuit

Figure 3. Typical Output Sink Characteristics Test Circuit

VDD VDD 16 INH AA BA CA DA EA AB BB CB DB EB DIS 8 ZA ITL PULSE GENERATOR 50% DUTY CYCLE B A VDD INH AA BA CA DA EA AB BB CB DB EB DIS 8 500 µF

0.01 µF CERAMIC 16 ZA

ZB VSS CL IDD CL

ZB VSS

Figure 4. 3­State Leakage Current Test Circuit

Figure 5. Typical Power Dissipation Test Circuit

MC14506UB 4

MOTOROLA CMOS LOGIC DATA

VDD 16 INH AA BA CA DA EA AB BB CB DB EB DIS 8 ZA 20 ns 90% 50% 10% tPHL 90% 50% 10% 20 ns VDD VSS tPLH VOH VOL tTLH

PULSE GENERATOR

INPUT

OUTPUT ZB VSS CL CL

tTHL

Figure 6. Switching Time Test Circuit and Waveforms (Data Inputs)

VDD 16 INH AA BA CA DA EA AB BB CB DB EB DIS 8 ZA

Vout

VDD

20 ns CL 1k S2 A B tPLZ 10% OUTPUT ZB VSS tPHZ 90% DISABLE INPUT 90% 50% 10%

20 ns

B A

S1

tPZL 90%

PULSE GENERATOR

tPZH 10%

VOH 2.5 V @ VDD = 5 V, 10 V AND 15 V 2 V @ VDD = 5 V 6 V @ VDD = 10 V 10 V @ VDD = 15 V VOL

* To test other side of circuit connect to this output and change switch (S1) to other expand input (E).

SWITCH POSITIONS
TEST tPLZ tPHZ tPZL tPZH S1 A B A B S2 A B A B

Figure 7. Switching Time Test Circuit and Waveforms (For 3­State Output)

MOTOROLA CMOS LOGIC DATA

MC14506UB 5

OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 620­10 ISSUE V
­A­
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 ­­­ 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ­­­ 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01

­B­
1 8

C

L

­T­
SEATING PLANE

N E F D G
16 PL

K M J
16 PL

0.25 (0.010)
M

M

T B

S

0.25 (0.010)

T A

S

P SUFFIX PLASTIC DIP PACKAGE CASE 648­08 ISSUE R
­A­
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01

B
1 8

F S

C

L

­T­ H G D
16 PL

SEATING PLANE

K

J T A
M

M

0.25 (0.010)

M

MC14506UB 6

MOTOROLA CMOS LOGIC DATA

OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B­05 ISSUE J
­A­
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019

16

9

­B­
1 8

P

8 PL

0.25 (0.010)

M

B

S

G F

K C ­T­
SEATING PLANE

R

X 45 _

M D
16 PL M

J

0.25 (0.010)

T B

S

A

S

DIM A B C D F G J K M P R

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MOTOROLA CMOS LOGIC DATA

*MC14506UB/D*

MC14506UB MC14506UB/D 7