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8 6 2 REVISIONS
ECN NO. ---REV DESCRIPTION DATE APPROVED

7 APPROVALS

5

4

3

1

NOTE: "NI" OR "( )" USED WITH COMPONENTS INDICATES "NOT INSTALLED". A PRODUCTION RELEASE

TABLE OF CONTENTS
36 37 38 39 40 41 43 44 45 46 47 48 49 50 51 52 53 54 55 56 SCSI CTLR DECOUPLING & LED CKT SCSI ON-BOARD AUTO-TERMINATION INTERNAL LVD/SE SCSI CONNECTOR VOLTAGE REGULATORS VDDQ REGULATOR 2.5V DECOUPLING 2.5V REGULATOR 1.8V REGULATOR DECOUPLING PRIMARY VRM SECONDARY VRM REV SHEET VOLTAGE ATTRIBUTES MISC NET_CROSS_REF_PAGE(S) COMP_CROSS_REF_PAGE(S) 57 58 59 60 61 62 63 64 65-66 67-68 69 70 71 72-75 76-80 Embedded SCSI Controller USBPORT 2&3 USB PORTS 1-2 KB/MS/FLOPPY CONN. SERIAL PORTS PARALLEL PORT TERM. SUPER I/O SIO2 POWER CKT FAN CONTROL BATTERY & RTC OSC. PS_ON & RESET CKT IDE TERMINATIONS IDE CONNECTORS P/S CONNECTOR I2C SELECT CONTROL FWH AUDIO REGULATOR /MIC HEADPHONE AMP INTERNAL SPKR & JACK

D

PAGE

2-

BLOCK DIAGRAM

D

3-

RESET BLOCK DIAGRAM

4-

SYSTEM CLOCK

5-

DUAL DRCG

6-

ITP

7-

FOSTERA-1

8-

FOSTERA-2

9-

FOSTERB-1

10 -

FOSTERB-2

11 -

VRM decoupling

12 -

Comparator

13 -

GTL REFERENCE

14 -

CPU PLL VOLTAGE

C

15 -

COLUSA-1

C

16 -

COLUSA-2

17 -

CHA RIMM 1

18 -

CHA RIMM 2

19 -

SLP_S3

20 -

CHA RSL TERMINATION

21 -

CHB RIMM1

22 -

CHB RIMM2

23 -

CHB TERMINATION

24 -

UNIV AGP PRO

25 -

AGP TERMINATIONS

26 -

PCI TERMINATIONS

27 -

PCI CONNECTOR SLOT 1

28 -

PCI CONNECTOR SLOT 2

B

29 -

PCI CONNECTOR SLOT 3

B

30 -

LAN PHY

31 -

MAGNETICS/RJ45 CONNECTOR

32-33 -

ICH2

34 -

sound blaster

35 -

AC97 CODEC

Machine ID = xxxxh
APPROVALS 010912-101 ASSEMBLY
DRAWN

DATE

010913-000 SCHEMATIC FAB DT SPARES MT SPARES 010914-001 xxxxxx-xxx xxxxxx-xxx

COMPAQ CONFIDENTIAL
CHECKED DSGN ENGR ENGR TOOLING
HARINI MALIK 03/09/01

A

A Betty: 2P Foster-Colusa

PROPRIETARY NOTE

PROD ENGR QA NEXT ASSY
SUPPLEMENTS:EF,EF-EPS,EF-TIF?

SIZE
PROJECT NO. LEGAL AGENCY

DRAWING NO.

REV

THIS DOCUMENT CONTAINS INFORMATION CONFIDENTIAL AND PROPRIETARY TO COMPAQ COMPUTER CORPORATION AND SHALL NOT BE REPRODUCED OR TRANSFERRED TO OTHER DOCUMENTS OR DISCLOSED TO OTHERS OR USED FOR ANY PURPOSES OTHER THAN THAT FOR WHICH IT WAS OBTAINED WITHOUT THE EXPRESSED WRITTEN CONSENT OF COMPAQ COMPUTER CORPORATION.

B
SCALE:NTS

010913-000
DO NOT SCALE DRAWING

REV A
SHEET 1 OF

80

8 6

7

5

4

3

2

1

8 6 5 4 3 2 1

7

Audio Ports
D

D

PCI SLOT 3 PCI SLOT 2 PCI SLOT 1
C

SCALABLE BUS

Hub Link

C

AGP BUS AC97 Link PCI BUS

RAMBUS LPC I/F BUS

CMOS BUS

B

B

RSL BUS
USB Ports

ATA-100 IDE CD-ROM DVD

-----------------------------

SIZE

DRAWING NO.

REV

B
COMPAQ CONFIDENTIAL FILE: 5 4 6 3

010913-000
betty.2
2 SCALE: NONE SHEET 1

REV A
2
OF

80

8

7

-------------------------

A

A

8 6 5 4 3 2 1

7

D

D

C

C

B

B

A

A

SIZE

DRAWING NO.

REV

B
COMPAQ CONFIDENTIAL FILE: 5 4 6 3

010913-000
betty.3
2 SCALE: NONE SHEET 1

REV A
3
OF

80

8

7

8 6 3_3V_SYS_CLK 1K 1K R946
* *

7

5

4

3

2

1

4

+3.3V 1%
* * * *
C99 COG 10PF

CLK_CPU_SEC
4,8 4,8 4,10

4,10

CLK_CPU_SEC_

CLK_CPU_PRI 1% CLK_CPU_PRI_

1 49.9 49.9 49.9
C38

14.318MHZ
49.9 NI
C39 COG 10PF COG 10PF C100

114410-002 10PF R257 R255
*

D 1K
*

R256

NI
COG 10PF

Y3
NI

R254

SXTL4DT R1006 1% 1%

NI U32 R1005
*

C287

10PF

NI 33 33
*

XTALIN XTALIN XTALOUT R1004
*

XTALOUT 23 52 SEL133 SPREAD_ R952 R953 R950 R951
* * * *

5 6 REFCLK0_MULTISEL0 REFCLK1_MULTISEL1 CPUCLK0 CPUCLK0_ 33 33 33 33 CLK_CPU_SEC CLK_CPU_SEC_ CLK_MCH CLK_MCH_ DRCG_CLKIN 33 33 33 CLK_CPU_PRI CLK_CPU_PRI_ CPUCLK1 CPUCLK1_ 48 47 51 50
*

175244-001 SSO56WAT 2 3
32 49

R259

*

C288

NI

ICH_CLK14 SIO_CLK14M R954 R955 CLK_ITP CLK_ITP_ 33 33
4,6 4,6 4,10 4,10

R1008

NC_133_100_ 42 41 45 44 28 PWR_DWN_ IREF VDDREF VSSREF R948 R949 R945
* * *

*

300 39 4 1 56 53 VDDMEM VSSMEM MEMREF MEMREF_ R1007
*

I

R947 CPUCLK2 CPUCLK2_ CPUCLK3 CPUCLK3_ 55 54 33 33 CPUDIV2 NC_MEMREF_

NI

*

33

SPREAD_

R_SPREAD_

4,8 4,8 4,16 4,16
5

R252

*

R261

0

I

*

475

+3.3V 27 24 VDDUSB VSSUSB AVDD AVSS 33 38 37
8 7 6 5 1 2 3 4

300

C

60

R253

4
NI NI

1K
NI

D

R262

8.2K

L32

C ICH_PCICLK
32

1 SB_PCICLK SCSI_PCICLK SIO_PCICLK FWH_PCICLK

2

RN15

34
55 49 39

C275 15PF NI
27 28 29

C1028

4.7UF C250

0.1UF

R958
*

*

3V66_0 3V66_1 3V66_2 3V66_3 AGPCLK R956 33
*

B 1 2
4

+3.3V 3_3V_SYS_CLK

L33
*

*

8,10

C282

4.7UF

4.7UF

0.1UF C286

0.1UF C285

0.1UF C284

0.1UF C283

0.1UF C249

0.1UF C253

49.9

49.9

49.9

C164 COG 10PF

COG 10PF

COG 10PF

COG 10PF

R260

R258

R251

NI

1%

1% A

A

SIZE

DRAWING NO.

R250

NI

NI

NI

49.9

SYSTEM CLOCK
COMPAQ CONFIDENTIAL 6 5 4

R302

C1030

C281 10UF

*

Q808
S603AT Clock Power - Use Islands Place 4.7 uF caps close to L

1/16W

1

2.2K

0.01UF

2

C

C1029

C1051

0.1UF C248

0.1UF C252

0.1UF C251

0.1UF

C247
VDDCPU1 VDDCPU2 VSSCPU1 VSSCPU2

S603AT

43 49 40 46

RN16

+3.3V

0.01UF
29 36 32 33 VDD3V66_1 VDD3V66_2 VSS3V66_1 VSS3V66_2 R957 33 30 31 34 35 33 25 26 NC_PCICLK9 10 16 22 7 13 19 VDDPCI1 VDDPCI2 VDDPCI3 VSSPCI1 VSSPCI2 VSSPCI3 USBCLK0_SELA USBCLK1_SELB R1009 48MHZ R1010 1K
*

PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 PCICLK7 PCICLK8 PCICLK9
8 7 6 5 1 2 3 4

8 9 11 12 14 15 17 18 20 21 PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4

119917-115
12

GCLKIN AGP_CLK ICH_GCLKIN
24 32

16

C206 15PF NI 119917-115 33 ICH_CLK48
32

P_THERMTRIP_

R285 1K

B

3

E

60

DTC123TKA

B

8.2K
THERMTRIP_
49

CLK_MCH 1%
*
C165

4,16

CLK_MCH_
*

4,16

1%
*
C809 C810

CLK_ITP CLK_ITP_
*

4,6 4,6

used for level translation

REV

B
FILE: 3

010913-000
betty.4
2 SCALE: NONE SHEET 1

REV A
4
OF

80

8

7

8 6 5 4 3 2 1

7

Some 64 mbit tech rimms had a bug

that saw some commands in broadcast

DRCG RATIO(MULT2=0) MODE MODE STATE Normal 1 0 X Clk Off Powerdown 0 1 1 PWRDNB STOPB PAclk PLLclk Refclk RefclkB Hi-Z Hi-Z PLLclkB PAclkB MODE Normal Bypass 1 1 0 1 x 1 0 Test Disable 0 0 0 0 0 S0 S1 S2

mode. this caused a current spike

MULT 0:1

RATIO

FSB/RDRM

on the rambus channel. putting

0:

0

4:

1

100/200

the DRCG in test mode during

D

init, cut this current spike down.

0:

1

6:

1

100/300

C

2

1:

0

8:

3

100/133

D

1: Use Normal and Test Modes

1

8:

1

100/400

5,33

MULT0

1

Q4

B

2N2222A

106127-002

E

3

NI
+3.3V +1.8V

SOT23FT

+3.3V

C

2

+3.3V

+3.3V

+3.3V

5,49
* *

DRCG_S0_S1 R233 8.2K

1 8.2K NI

Q5

B

2N2222A

R237

R929

R928

8.2K

8.2K

106127-002

*

*

8.2K

*

NI R236

I

I

NI
176902-001
R235 8.2K SSO28AT
*
*

E Place these resistors less than 1 inch from DRCG

3

U31
Intel recommends

SOT23FT

C R266 2 REFCLK 39.2 1% 20 19 CTMA_CLK_R CTMNA_CLK_R 1 12 CLK1 CLK1_ VDDIR VDDIPD CLK0 CLK0_ 23 24 CTMB_CLK_R CTMNB_CLK_R

W234

51ohm and 39ohm.

C B_RM2_LCTM
Intel recommends If C815 and C796 are changed to 0.1 uF, jitter will decrease, but latency coming out of stop clock will increase *

22

4

DRCG_CLKIN 17 16 15 M0 M1 M2 SYNCLK0 PCLK0 4 5 9 10 SYNCLK1 PCLK1 R265

R268

I

5,33 33

MULT0 MULT1

*

0

R267 51 1% C256 4PF NI CTMB_DIFF R264
*

16 16

RCLKOUT_B HCLKOUT_B

16 16

RCLKOUT_A HCLKOUT_A

C257 51 1% 0.1UF

*

5,49

DRCG_S0_S1 28 27 26 S0 S1 S2 STOP_ PWRDN_

B_RM2_LCTMN
*

R286 I

0

22

MULTO&MULT1
*

300 R888

to ICH2 GPIO

*

I 1K 3_3V_DRCG;3,7,11,21,22 GND;6,8,18,25 +1.8V

13 14 DRCG_PWRDN_P_U

39.2 1% R270
*

*

R887

R263

A_RM2_LCTM 39.2 1%
*

1K

18

B C263 4PF NI

R269 51 1% CTMA_DIFF

B

C978
C980 0.1UF
X7R

10UF

+3.3V

C226
*

R272 51 1% R271

C260 0.1UF

L31 3_3V_DRCG C228 C262 C259 C230 .01UF
S603AT 100PF C227 100PF

A_RM2_LCTMN
*

1

2

18

60

C231 .1UF
S603AT S603AT S603AT

C979 .1UF .1UF

39.2 1%

S603AT

TANTB

A

100PF C258

100PF C229

0.01UF

C261

*

10UF

A

SIZE

DRAWING NO.

REV

DUAL DRCG
COMPAQ CONFIDENTIAL 6 5 4

B
FILE: 3

010913-000
betty.5
2 SCALE: NONE SHEET 1

REV A
5
OF

80

8

7

8 6 VDD3_AUX;14 VDD3_AUX 2 SW1 3 74LCX125 5 4 3 2 1

7

U26

R853
*

1.5K

Make sure GTL_RESET_ is from Colusa- XU2-XU1-ITP
*

PB_SWITCH 1 P1 P2 2 219333-001

R175 1 300 D

D

make sure BPMx lines are from Xu1-xu2-ITP
3 P3 114477-007 SSW4AT INCLUDE=NI P4 4

*

*

R801 1.5K NI NI 121546-019
*

P100
+3.3V VDD3_AUX

R812

40.2

1%

*

40.2

R806

R810
ITP 150
* *

R811

R809

40.2

*

I NI 1% R807 1%
8,10,12,15 GTL_RESET_

4 4

CLK_ITP CLK_ITP_ 21 19 R808 BCLK0 BCLK1 DBA_ DBR_ 4 6 DBRESET_ TCK FBI FBO 18 17 ITP_PWR

1%

40.2

C

40.2

1% 15 22 23 RESET_ PWR BPM5DR_

*

150

R804
39.2

*

1%

33,49 8,10

C

139708-216

8,10 8,10

BPM0_ BPM1_ 3 5 7 9 11 13 1% 27.4 5% BPM0_ BPM1_ BPM2_ BPM3_ BPM4_ BPM5_
*

1%

220

PKG_TYPE=C26HD2H
*

*

R803 GND;1,2,8,20,25 NI R802 150 1%
*

R159

R62

ITP
10

XU1 CPU_PRI_TDI

XU2

150

8,10 8,10

BPM4_ BPM5_

TCK TDI TDO TMS TRST_

16 10 24 12 14

TMS TRST_

8,10 8,10

2 -3 : P1 only 1 - 2 : P1 and P2

CPU_PRI_TDI C808 0.01UF
S603AT S603AT S603AT

CPU_SEC_TDI C845 0.01UF 0.01UF C826

TDI

TDI

TDI B

B

CPU_PRI_TDO

75 1%

*

R800
*

150

R815

TDO

TDO

TDO
8 10 8

P400 CPU_SEC_TDI CPU_PRI_TDO 1 2 3 C3HA1A CHECK NAMING CONVENTION 100186-012

NI

CPU_SEC_TDO

CPU_SEC_TDO

A

A

SIZE

DRAWING NO.

REV

ITP
COMPAQ CONFIDENTIAL 6 5 4

B
FILE: 3

010913-000
betty.6
2 SCALE: NONE SHEET 1

REV A
6
OF

80

8

7

8 6 GTL_D[31:16]_
9,15

7

5

4

3

2

1

9,15

GTL_D[63:48]_
9,15

GTL_D[47:32]_ GTL_D[15:0]_
9,15

SECONDARY PROCESSOR
D

D

GTL_D63_ GTL_D62_ GTL_D61_ GTL_D60_ GTL_D59_ GTL_D58_ GTL_D57_ GTL_D56_ GTL_D55_ GTL_D54_ GTL_D53_ GTL_D52_ GTL_D51_ GTL_D50_ GTL_D49_ GTL_D48_ GTL_D47_ GTL_D46_ GTL_D45_ GTL_D44_ GTL_D43_ GTL_D42_ GTL_D41_ GTL_D40_ GTL_D39_ GTL_D38_ GTL_D37_ GTL_D36_ GTL_D35_ GTL_D34_ GTL_D33_ GTL_D32_ GTL_D31_ GTL_D30_ GTL_D29_ GTL_D28_ GTL_D27_ GTL_D26_ GTL_D25_ GTL_D24_ GTL_D23_ GTL_D22_ GTL_D21_ GTL_D20_ GTL_D19_ GTL_D18_ GTL_D17_ GTL_D16_ GTL_D15_ GTL_D14_ GTL_D13_ GTL_D12_ GTL_D11_ GTL_D10_ GTL_D9_ GTL_D8_ GTL_D7_ GTL_D6_ GTL_D5_ GTL_D4_ GTL_D3_ GTL_D2_ GTL_D1_ GTL_D0_

(MIDDLE AGENT)
XU2

D63_ D62_ D61_ D60_ D59_ D58_ D57_ D56_ D55_ D54_ D53_ D52_ D51_ D50_ D49_ D48_ D47_ D46_ D45_ D44_ D43_ D42_ D41_ D40_ D39_ D38_ D37_ D36_ D35_ D34_ D33_ D32_ D31_ D30_ D29_ D28_ D27_ D26_ D25_ D24_ D23_ D22_ D21_ D20_ D19_ D18_ D17_ D16_ D15_ D14_ D13_ D12_ D11_ D10_ D9_ D8_ D7_ D6_ D5_ D4_ D3_ D2_ D1_ D0_

AB6 Y9 AA8 AC5 AC6 AE7 AD7 AC8 AB10 AA10 AA11 AB13 AB12 AC14 AA14 AA13 AC9 AD8 AD10 AE9 AC11 AE10 AC12 AD11 AD14 AD13 AB15 AD18 AE13 AC17 AA16 AB16 AB17 AD19 AD21 AE20 AE22 AC21 AC20 AA18 AC23 AE23 AD24 AC24 AE25 AD25 AC26 AE26 AA19 AB19 AB22 AB20 AA21 AA22 AB23 AB25 AB26 AA24 Y23 AD27 AA25 Y24 AA27 Y26

GTL_A[35:17]_

A4 VCF_PLL1 A15 VCF_PLL2 AE4 VCF_PLL3

FOSTER Symbol 1 of 2

9,12,15

GTL_ADSTB[1:0]_

9,15

GTL_ADSTB1_ GTL_ADSTB0_

F14 F17

ADSTB1_ ADSTB0_

9,15

C

9,15

GTL_AP1_ GTL_AP0_

D9 E10

AP1_ AP0_

C

GTL_DBI[3:0]_

GTL_DBI3_ GTL_DBI2_ GTL_DBI1_ GTL_DBI0_

AB9 AE12 AD22 AC27

9,15

DBI3_ DBI2_ DBI1_ DBI0_

VCCP;A14,A18,A2,A24,A28,A8,AA12,AA20,AA26,AA4,AA6,AB14,AB18 VCCP;AB24,AB8,AC10,AC16,AC22,AC4,AD12,AD20,AD26,AD6,AE14 VCCP;AE18,AE24,AE8,B12,B20,B26,B29,B6,C10,C16,C2,C22,C28,C4 VCCP;D14,D18,D24,D29,D8,E12,E2,E20,E26,E28,E6,F10,F16,F22 VCCP;F29,F4,G2,G24,G26,G28,G4,G6,G8,H23,H25,H27,H29,H3,H5 VCCP;H7,H9,J2,J24,J26,J28,J4,J6,J8,K23,K25,K27,K29,K3,K5,K7 VCCP;K9,L2,L24,L26,L28,L4,L6,L8,M23,M25,M27,M29,M3,M5,M7,M9 VCCP;N23,N25,N27,N29,N3,N5,N7,N9,P2,P24,P26,P28,P4,P6,P8 VCCP;R23,R25,R27,R29,R3,R5,R7,R9,T2,T24,T26,T28,T4,T6,T8 VCCP;U23,U25,U27,U29,U3,U5,U7,U9,V2,V24,V26,V28,V4,V6,V8 VCCP;W25,W27,W29,Y10,Y16,Y22,AB2,AC3,AD2,AE3,Y2

GTL_DP[3:0]_

9,15

GTL_DP3_ GTL_DP2_ GTL_DP1_ GTL_DP0_

AE17 AC15 AE19 AC18

DP3_ DP2_ DP1_ DP0_

GTL_DSTBN[3:0]_

GTL_DSTBN3_ GTL_DSTBN2_ GTL_DSTBN1_ GTL_DSTBN0_

Y12 Y15 Y18 Y21

9,15

DSTBN3_ DSTBN2_ DSTBN1_ DSTBN0_

GTL_DSTBP[3:0]_

9,15

GTL_DSTBP3_ GTL_DSTBP2_ GTL_DSTBP1_ GTL_DSTBP0_ VCCP;A30,B4,B31,C30,D1,D31,E30,F1,F31,G30,H1,H31,J30,K1,K31,L30,M1,M31 VCCP;N1,N31,P30,R1,R31,T30,U1,U31,V30,W1,W31,Y30,AA1,AA31,AB30,AC31,AD30 GND;A31,B30,C1,C31,D30,E1,E31,F30,G1,G31,H30,J1,J31,K30,L1,L31,M30 GND;N30,P1,P31,R30,T1,T31,U30,V1,V31,W30,Y1,Y31,AA30,AB1,AB31,AC30,AD31

Y11 Y14 Y17 Y20

DSTBP3_ DSTBP2_ DSTBP1_ DSTBP0_

GND;A11,A21,A27,A29,A5,AA15,AA17,AA23,AA9,AB11,AB21,AB27,AB5 GND;AC13,AC19,AC25,AC7,AD15,AD17,AD23,AD9,AE11,AE21,AE27,B15 GND;B17,B2,B23,B28,B9,C13,C19,C25,C29,C7,D11,D2,D21,D27,D28 GND;D5,E15,E17,E23,E29,E9,F13,F19,F2,F25,F28,F7,G25,G27,G29 GND;G3,G5,G7,G9,H2,H24,H26,H28,H4,H6,H8,J23,J25,J27,J29,J3,J5 GND;J7,J9,K2,K24,K26,K28,K4,K6,K8,L23,L25,L27,L29,L3,L5,L7,L9 GND;M2,M24,M26,M28,M4,M6,M8,N2,N24,N26,N28,N4,N6,N8,P23,P25 GND;P27,P29,P3,P5,P7,P9,R2,R24,R26,R28,R4,R6,R8,T23,T25,T27 GND;T29,T3,T5,T7,T9,U2,U24,U26,U28,U4,U6,U8,V23,V25,V27,V29 GND;V3,V5,V7,V9,W2,W24,W26,W28,W4,Y13,Y19,Y25,Y5,Y7,AA2,AC2,AD3 NC=AA3,AB3,AE15,AE16,Y27,Y28,Y3,A1,A16,A26,AC1,AD1,B1,C5,D25,W3

A35_ A34_ A33_ A32_ A31_ A30_ A29_ A28_ A27_ A26_ A25_ A24_ A23_ A22_ A21_ A20_ A19_ A18_ A17_ A16_ A15_ A14_ A13_ A12_ A11_ A10_ A9_ A8_ A7_ A6_ A5_ A4_ A3_

C8 C9 A7 A6 B7 C11 D12 E13 B8 A9 D13 E14 C12 B11 B10 A10 F15 D15 D16 C14 C15 A12 B13 B14 B16 A13 D17 C17 A19 C18 B18 A20 A22

GTL_A35_ GTL_A34_ GTL_A33_ GTL_A32_ GTL_A31_ GTL_A30_ GTL_A29_ GTL_A28_ GTL_A27_ GTL_A26_ GTL_A25_ GTL_A24_ GTL_A23_ GTL_A22_ GTL_A21_ GTL_A20_ GTL_A19_ GTL_A18_ GTL_A17_ GTL_A16_ GTL_A15_ GTL_A14_ GTL_A13_ GTL_A12_ GTL_A11_ GTL_A10_ GTL_A9_ GTL_A8_ GTL_A7_ GTL_A6_ GTL_A5_ GTL_A4_ GTL_A3_

GTL_A[16:3]_
9,15

B

178342-001

B

SKTBGA603F

Place <0.5" around processor #1 socket

for VCCP decoupling

CLOSE TO CPU1 PACKAGE ON BOTTOM SIDE CLOSE TO CPU1 PACKAGE ON BOTTOM SIDE
DECOUPLING FOR GTL ADDR/CTRL SIGNALS

DECOUPLING FOR GTL DATA SIGNALS

UNDER CPU1 CAVITY C72 C66 C69 0.01UF 0.01UF
S603AT S603AT

C872 C36 C63 0.01UF 0.01UF
S603AT S603AT S603AT S603AT

C871 0.01UF

NI 0.01UF

+

+

C37

C8

C27 0.01UF

C48

C73 0.01UF
S603AT S603AT

C33 0.01UF
S603AT

C28 0.01UF
S603AT
121808-349

C57 0.01UF
S603AT

C68 0.01UF
S603AT

820UF

820UF

NI

0.01UF

0.01UF
S603AT

S603AT

4V

4V

121520-012 A

A

SIZE

DRAWING NO.

REV

FOSTERA-1
COMPAQ CONFIDENTIAL

B
FILE: 5 4 6 3

010913-000
betty.7
2 SCALE: NONE SHEET 1

REV A
7
OF

80

8

7

8 6 5 4 3 2 1

7

for signal integrity 56

+3.3V

40.2

*

*

SECONDARY PROCESSOR
* *

40.2

40.2

R1161

R1160

D C1266 47PF
10,15 10,32 10,32 10,32
S603T

47PF
10,32

R139

1UF FERR_ IERR_ MCERR_ SMI_ INIT_ STPCLK_ C27 D6 D4 H_SMI_ H_INIT_ H_STPCLK_ E27 E5 D7 H_FERR_ H_IERR0_ GTL_MCERR_

1UF

1UF

1UF

1UF

1UF

1UF

1UF

R15

C14
139708-216

C17

C83

R1159

C10

C50

C35

C56

C80

FOSTER
10,15 10,15 10,15 10,15

XU2
NI

56 I

*

s805t

s805t

s805t

s805t

s805t

s805t

s805t

s805t

D

C1267

47PF E22 A23 C23 HIT_ HITM_ DEFER_ F21 D22 E21 C6 RS2_ RS1_ RS0_ RSP_

C1265

GTL_ADS_ GTL_DRDY_ GTL_DBSY_ GTL_TRDY_ D19 E18 F18 E19 ADS_ DRDY_ DBSY_ TRDY_

10,15 10,15 10,15

GTL_HIT_ GTL_HITM_ GTL_DEFER_ GTL_RS[2:0]_

S603T

S603T

+3.3V

10,15

40.2

R78

*

10,15

GTL_RS2_ GTL_RS1_ GTL_RS0_ GTL_RSP_

*

R19

300

41.2

8.2K
10,49

SM_ALERT SM_EP_A2 SM_EP_A1 SM_EP_A0 SM_TS_A1 SM_TS_A0 SM_CLK SM_DAT SM_WP AE28 AE29

AD28 AB28 AB29 AA29 Y29 AA28 AC28 AC29 AD29
10,26,32 8 8 8 8 8 10,40,47 10,40,47

ICH_SMBALERT_ SM_A2_CPUMID SM_A1_CPUMID SM_A0_CPUMID SM_TSA1_CPUMID SM_TSA0_CPUMID SMBCLK SMBDAT WP_CPU_EEPROM

GTL_REQ[4:0]_
10,15 10,15 10

GTL_REQ4_ GTL_REQ3_ GTL_REQ2_ GTL_REQ1_ GTL_REQ0_ B22 C20 C21 B21 B19 REQ4_ REQ3_ REQ2_ REQ1_ REQ0_ SM_VCC1 SM_VCC2 W5 Y4
4 4

*

ICH_PROCHOT_ GTL_LOCK_ GTL_BINIT_ BCLK1 BCLK0 CLK_CPU_SEC_ CLK_CPU_SEC GTL_BNR_ 10,15 GTL_BPRI_ 10,15
6,10,12,15

33

*

56

C GTL_RESET_ P0_GTL_BR_2_3
10,15 10 10,32 10,32 10,32 10,32

2

*

41.2

*

A17 F11 F20 D23 Y8 LOCK_ BINIT_ BNR_ BPRI_ RESET_ CPUMID_VCCA CPUM_VCCIOPLL CPUMID_VSSA
14 14 14

C GTL_BR0_ GTL_BR1_ H_IGNNE_ H_NMI H_INTR H_A20M_ C26 G23 B24 F27 IGNNE_ LINT1_ LINT0_ A20M_ BPM5_ BPM4_
6,10 6,10

1

1/16W

Q3
BR3_ BR2_ BR1_ BR0_ TCK TDI TDO TMS TRST_ E24 C24 E25 A25 F24 TCK CPU_SEC_TDI CPU_SEC_TDO TMS TRST_
6,10 6 6 6,10 6,10

R35

R144

2.2K

C

B

DTC123TKA

R874

D10 E11 F12 D20

E

3 PROCHOT_

8,10

R65

VCCA VCCIOPLL VSSA VCCSENSE VSSSENSE

AB4 AD4 AA5 B27 D26

10,32 12,16 10,32 4,10

4.7K

8,10

PWRGD_ICH_CPU SKT_OCC_SEC_ H_SLP_ P_THERMTRIP_ PROCHOT_ AB7 A3 AE6 F26 B25 PWRGOOD SKTOCC_ SLP_ THERMTRIP_ PROCHOT_ BPM5_ BPM4_ BPM3_ BPM2_ BPM1_ BPM0_ BPM1_ BPM0_
6,10 6,10

CPUMID_VCCSEN CPUMID_VSSSEN
100186-014

RN801

E4 E8 F5 E7 F8 F6

HDR1X2

1 2 E405 VIDB4 VIDB3 VIDB2 VIDB1 VIDB0
11,12 11,12 11,12 11,12 11,12

empty

RN800

4.7K

8 7 6 5 1 2 3 4

8 7 6 5

1 2 3 4

AE5 AD5 AA7 Y6 W8 W7 W6 TESTHI6 TESTHI5 TESTHI4 TESTHI3 TESTHI2 TESTHI1 TESTHI0 VID4 VID3 VID2 VID1 VID0 B3 C3 D3 E3 F3 B5 E16 AD16 ODTEN COMP1 COMP0 MP_DP_ AE2 XU2_MP_DP_

C2HA1A +3.3V B R1154

B

R67

1K

R63

*

CPUMID_GTLREF3 CPUMID_GTLREF2 CPUMID_GTLREF1 CPUMID_GTLREF0 GTLREF3 GTLREF2 GTLREF1 GTLREF0
13

F9 F23 W9 W23

43.2

43.2

*

*

R34

R96

*

0 119919-001
8 8 8 8 8

R98
1K NI
*

1K
*

R104

R102

R100

100

100

Symbol 2 of 2
178342-001
SKTBGA603F VCCP decoupling

139708-279

SM_TSA1_CPUMID SM_TSA0_CPUMID SM_A2_CPUMID SM_A1_CPUMID SM_A0_CPUMID

I

NI

NI

I

VCCP decoupling

R99

R103

R101

R105

R97

C47 C67 22UF
s1210t s1210t s1210t s1210t s1210t s1210t

C84 C81 22UF 22UF 22UF 22UF 22UF C18 C29

C7 C70

C71

C24

C13

C55

C46 C34

C54 C51 22UF
s1210t

C16 C9 22UF
s1210t

C11 22UF
s1210t

C82

1K
*

1K
*

1K
*

1K
*

1K
*

22UF

22UF

22UF

22UF

22UF

22UF

22UF

22UF

22UF
s1210t

22UF
s1210t

22UF
s1210t
129621-026

NI NI

s1210t

s1210t

s1210t

s1210t

s1210t

s1210t

s1210t

s1210t

A

100

1%

1% CPUMID_GTLREF[3:0]

*

*

*

A

SIZE

DRAWING NO.

REV

FOSTERA-2
COMPAQ CONFIDENTIAL

B
FILE: 5 4 6 3

010913-000
betty.8
2 SCALE: NONE SHEET 1

REV A
8
OF

80

8

7

8 6 5 4 3 2 1

7

7,15

GTL_D[63:48]_
7,15 7,15

GTL_D[31:16]_ GTL_D[15:0]_
7,15

GTL_D[47:32]_

PRIMARY PROCESSOR (END AGENT)
XU1
D

D63_ D62_ D61_ D60_ D59_ D58_ D57_ D56_ D55_ D54_ D53_ D52_ D51_ D50_ D49_ D48_ D47_ D46_ D45_ D44_ D43_ D42_ D41_ D40_ D39_ D38_ D37_ D36_ D35_ D34_ D33_ D32_ D31_ D30_ D29_ D28_ D27_ D26_ D25_ D24_ D23_ D22_ D21_ D20_ D19_ D18_ D17_ D16_ D15_ D14_ D13_ D12_ D11_ D10_ D9_ D8_ D7_ D6_ D5_ D4_ D3_ D2_ D1_ D0_

AB6 Y9 AA8 AC5 AC6 AE7 AD7 AC8 AB10 AA10 AA11 AB13 AB12 AC14 AA14 AA13 AC9 AD8 AD10 AE9 AC11 AE10 AC12 AD11 AD14 AD13 AB15 AD18 AE13 AC17 AA16 AB16 AB17 AD19 AD21 AE20 AE22 AC21 AC20 AA18 AC23 AE23 AD24 AC24 AE25 AD25 AC26 AE26 AA19 AB19 AB22 AB20 AA21 AA22 AB23 AB25 AB26 AA24 Y23 AD27 AA25 Y24 AA27 Y26

GTL_D63_ GTL_D62_ GTL_D61_ GTL_D60_ GTL_D59_ GTL_D58_ GTL_D57_ GTL_D56_ GTL_D55_ GTL_D54_ GTL_D53_ GTL_D52_ GTL_D51_ GTL_D50_ GTL_D49_ GTL_D48_ GTL_D47_ GTL_D46_ GTL_D45_ GTL_D44_ GTL_D43_ GTL_D42_ GTL_D41_ GTL_D40_ GTL_D39_ GTL_D38_ GTL_D37_ GTL_D36_ GTL_D35_ GTL_D34_ GTL_D33_ GTL_D32_ GTL_D31_ GTL_D30_ GTL_D29_ GTL_D28_ GTL_D27_ GTL_D26_ GTL_D25_ GTL_D24_ GTL_D23_ GTL_D22_ GTL_D21_ GTL_D20_ GTL_D19_ GTL_D18_ GTL_D17_ GTL_D16_ GTL_D15_ GTL_D14_ GTL_D13_ GTL_D12_ GTL_D11_ GTL_D10_ GTL_D9_ GTL_D8_ GTL_D7_ GTL_D6_ GTL_D5_ GTL_D4_ GTL_D3_ GTL_D2_ GTL_D1_ GTL_D0_

D

A4 VCF_PLL1 A15 VCF_PLL2 AE4 VCF_PLL3

GTL_A[35:17]_

7,12,15

FOSTER Symbol 1 of 2

GTL_ADSTB[1:0]_

7,15

GTL_ADSTB1_ GTL_ADSTB0_

F14 F17

ADSTB1_ ADSTB0_

7,15 7,15

GTL_AP1_ GTL_AP0_

D9 E10

AP1_ AP0_

C

C

GTL_DBI[3:0]_

7,15

GTL_DBI3_ GTL_DBI2_ GTL_DBI1_ GTL_DBI0_

AB9 AE12 AD22 AC27

DBI3_ DBI2_ DBI1_ DBI0_

VCCP;A14,A18,A2,A24,A28,A8,AA12,AA20,AA26,AA4,AA6,AB14,AB18 VCCP;AB24,AB8,AC10,AC16,AC22,AC4,AD12,AD20,AD26,AD6,AE14 VCCP;AE18,AE24,AE8,B12,B20,B26,B29,B6,C10,C16,C2,C22,C28,C4 VCCP;D14,D18,D24,D29,D8,E12,E2,E20,E26,E28,E6,F10,F16,F22 VCCP;F29,F4,G2,G24,G26,G28,G4,G6,G8,H23,H25,H27,H29,H3,H5 VCCP;H7,H9,J2,J24,J26,J28,J4,J6,J8,K23,K25,K27,K29,K3,K5,K7 VCCP;K9,L2,L24,L26,L28,L4,L6,L8,M23,M25,M27,M29,M3,M5,M7,M9 VCCP;N23,N25,N27,N29,N3,N5,N7,N9,P2,P24,P26,P28,P4,P6,P8 VCCP;R23,R25,R27,R29,R3,R5,R7,R9,T2,T24,T26,T28,T4,T6,T8 VCCP;U23,U25,U27,U29,U3,U5,U7,U9,V2,V24,V26,V28,V4,V6,V8 VCCP;W25,W27,W29,Y10,Y16,Y22,AB2,AC3,AD2,AE3,Y2

GTL_DP[3:0]_

7,15

GTL_DP3_ GTL_DP2_ GTL_DP1_ GTL_DP0_

AE17 AC15 AE19 AC18

DP3_ DP2_ DP1_ DP0_

GTL_DSTBN[3:0]_

7,15

GTL_DSTBN3_ GTL_DSTBN2_ GTL_DSTBN1_ GTL_DSTBN0_

Y12 Y15 Y18 Y21

DSTBN3_ DSTBN2_ DSTBN1_ DSTBN0_

GND;A11,A21,A27,A29,A5,AA15,AA17,AA23,AA9,AB11,AB21,AB27,AB5 GND;AC13,AC19,AC25,AC7,AD15,AD17,AD23,AD9,AE11,AE21,AE27,B15 GND;B17,B2,B23,B28,B9,C13,C19,C25,C29,C7,D11,D2,D21,D27,D28 GND;D5,E15,E17,E23,E29,E9,F13,F19,F2,F25,F28,F7,G25,G27,G29 GND;G3,G5,G7,G9,H2,H24,H26,H28,H4,H6,H8,J23,J25,J27,J29,J3,J5 GND;J7,J9,K2,K24,K26,K28,K4,K6,K8,L23,L25,L27,L29,L3,L5,L7,L9 GND;M2,M24,M26,M28,M4,M6,M8,N2,N24,N26,N28,N4,N6,N8,P23,P25 GND;P27,P29,P3,P5,P7,P9,R2,R24,R26,R28,R4,R6,R8,T23,T25,T27 GND;T29,T3,T5,T7,T9,U2,U24,U26,U28,U4,U6,U8,V23,V25,V27,V29 GND;V3,V5,V7,V9,W2,W24,W26,W28,W4,Y13,Y19,Y25,Y5,Y7,AA2,AC2,AD3 NC=AA3,AB3,AE15,AE16,Y27,Y28,Y3,A1,A16,A26,AC1,AD1,B1,C5,D25,W3 VCCP;A30,B4,B31,C30,D1,D31,E30,F1,F31,G30,H1,H31,J30,K1,K31,L30,M1,M31 VCCP;N1,N31,P30,R1,R31,T30,U1,U31,V30,W1,W31,Y30,AA1,AA31,AB30,AC31,AD30 GND;A31,B30,C1,C31,D30,E1,E31,F30,G1,G31,H30,J1,J31,K30,L1,L31,M30 GND;N30,P1,P31,R30,T1,T31,U30,V1,V31,W30,Y1,Y31,AA30,AB1,AB31,AC30,AD31

GTL_DSTBP[3:0]_

7,15

GTL_DSTBP3_ GTL_DSTBP2_ GTL_DSTBP1_ GTL_DSTBP0_

Y11 Y14 Y17 Y20

DSTBP3_ DSTBP2_ DSTBP1_ DSTBP0_

A35_ A34_ A33_ A32_ A31_ A30_ A29_ A28_ A27_ A26_ A25_ A24_ A23_ A22_ A21_ A20_ A19_ A18_ A17_ A16_ A15_ A14_ A13_ A12_ A11_ A10_ A9_ A8_ A7_ A6_ A5_ A4_ A3_

C8 C9 A7 A6 B7 C11 D12 E13 B8 A9 D13 E14 C12 B11 B10 A10 F15 D15 D16 C14 C15 A12 B13 B14 B16 A13 D17 C17 A19 C18 B18 A20 A22

GTL_A35_ GTL_A34_ GTL_A33_ GTL_A32_ GTL_A31_ GTL_A30_ GTL_A29_ GTL_A28_ GTL_A27_ GTL_A26_ GTL_A25_ GTL_A24_ GTL_A23_ GTL_A22_ GTL_A21_ GTL_A20_ GTL_A19_ GTL_A18_ GTL_A17_ GTL_A16_ GTL_A15_ GTL_A14_ GTL_A13_ GTL_A12_ GTL_A11_ GTL_A10_ GTL_A9_ GTL_A8_ GTL_A7_ GTL_A6_ GTL_A5_ GTL_A4_ GTL_A3_ GTL_A[16:3]_
7,15

178342-001

B

SKTBGA603F

B

Place <0.5" around processor #1 socket

for VCCP decoupling

CLOSE TO CPU1 PACKAGE ON BOTTOM SIDE CLOSE TO CPU1 PACKAGE ON BOTTOM SIDE
DECOUPLING FOR GTL ADDR/CTRL SIGNALS

DECOUPLING FOR GTL DATA SIGNALS

UNDER CPU1 CAVITY

C946 C91 0.01UF
S603AT S603AT

C119 0.01UF
S603AT S603AT S603AT

C118 C110 0.01UF
S603AT

C120 0.01UF 0.01UF

C177

C134 0.01UF
S603AT

C142 0.01UF
S603AT

C143 0.01UF
S603AT

C184 0.01UF
S603AT

C949 820UF + 0.01UF

+ 820UF

C111 0.01UF
S603AT

C115 0.01UF
S603AT

C182 0.01UF
S603AT

C179 0.01UF
S603AT

NI 4V

4V NI

A

A

SIZE

DRAWING NO.

REV

FOSTERB-1
COMPAQ CONFIDENTIAL

B
FILE: 5 4 6 3

010913-000
betty.9
2 SCALE: NONE SHEET 1

REV A
9
OF

80

8

7

8 6 5 4 3 2 1

7

56

56

56

56
*

PRIMARY PROCESSOR FOSTER
8,32
* * * * *

(TERMINATING P)
139708-216

XU1

R158

R94

R124

R12

8,15 8,15 8,15 8,15

GTL_ADS_ GTL_DRDY_ GTL_DBSY_ GTL_TRDY_ ADS_ DRDY_ DBSY_ TRDY_ R13 FERR_ IERR_ MCERR_ R16
8,15
*

D19 E18 F18 E19 E27 E5 D7 40.2 R17 C27 D6 D4 NI
8,32 8,32 8,32

*

40.2

41.2

8,15 8,15 8,15

GTL_HIT_ GTL_HITM_ GTL_DEFER_ E22 A23 C23 HIT_ HITM_ DEFER_ TO ICH2 GPIO

56

41.2

*

1%

1K

56

56

56

56

56

*

*

*

*

8,15

10K

*

*

*

*

*

*

GTL_RS[2:0]_ GTL_RSP_

NI

GTL_RS2_ GTL_RS1_ GTL_RS0_ F21 D22 E21 C6 RS2_ RS1_ RS0_ RSP_
6,8,10 6,8,10 6,8,10 6,8,10

8,15

R160

R163

R140

8,26,32 10 10 10 10 10 8,40,47 8,40,47

BPM0_ BPM1_ BPM4_ BPM5_

R36

R143

R194

R93

SM_ALERT SM_EP_A2 SM_EP_A1 SM_EP_A0 SM_TS_A1 SM_TS_A0 SM_CLK SM_DAT SM_WP
8,49

AD28 AB28 AB29 AA29 Y29 AA28 AC28 AC29 AD29 +3.3V AE28 AE29 W5 Y4
4 4

ICH_SMBALERT_ SM_A2_CPUEND SM_A1_CPUEND SM_A0_CPUEND SM_TSA1_CPUEND SM_TSA0_CPUEND SMBCLK SMBDAT WP_CPU_EEPROM

R138

R81

R80

R66

GTL_REQ[4:0]_ SM_VCC1 SM_VCC2 BCLK1 BCLK0 AB4 AD4 AA5 B27 D26
14 14 14

NI GTL_LOCK_ GTL_BINIT_ GTL_BNR_ GTL_BPRI_ GTL_RESET_ A17 F11 F20 D23 Y8 LOCK_ BINIT_ BNR_ BPRI_ RESET_ CLK_CPU_PRI_ CLK_CPU_PRI CPUEND_VCCA CPUE_VCCIOPLL CPUEND_VSSA P1_GTL_BR_2_3 GTL_BR1_ GTL_BR0_ H_IGNNE_ H_NMI H_INTR H_A20M_ C26 G23 B24 F27 IGNNE_ LINT1_ LINT0_ A20M_ BPM5_ BPM4_
6,8,10 6,8,10

NI

NI

8,15

GTL_REQ4_ GTL_REQ3_ GTL_REQ2_ GTL_REQ1_ GTL_REQ0_ B22 C20 C21 B21 B19 REQ4_ REQ3_ REQ2_ REQ1_ REQ0_

NI

NI

8,15 8 8,15 8,15

6,8,12,15

C TCK TDI TDO TMS TRST_ CPUEND_VCCSEN CPUEND_VSSSEN E24 C24 E25 A25 F24
6,8 6 6 6,8 6,8

8 8,15

D10 E11 F12 D20 BR3_ BR2_ BR1_ BR0_ TCK CPU_PRI_TDI CPU_PRI_TDO TMS TRST_

40.2 1% 1% C

SMI_ INIT_ STPCLK_

VCCA VCCIOPLL VSSA VCCSENSE VSSSENSE

8,32 8,32 8,32 8,32

100186-014

1 2

E406 C2HA1A

8,32 12,49 8,32 4,8 8

PWRGD_ICH_CPU SKT_OCC_PRI_ H_SLP_ P_THERMTRIP_ PROCHOT_ 4.7K PWRGOOD SKTOCC_ SLP_ THERMTRIP_ PROCHOT_ BPM5_ BPM4_ BPM3_ BPM2_ BPM1_ BPM0_ BPM1_ BPM0_
6,8,10 6,8,10

AB7 A3 AE6 F26 B25

RN802
AE5 AD5 AA7 Y6 W8 W7 W6 TESTHI6 TESTHI5 TESTHI4 TESTHI3 TESTHI2 TESTHI1 TESTHI0 VID4 VID3 VID2 VID1 VID0 B3 C3 D3 E3 F3 CPUEND_VIDA4 CPUEND_VIDA3 CPUEND_VIDA2 CPUEND_VIDA1 CPUEND_VIDA0

E4 E8 F5 E7 F8 F6

4.7K
1 2 3 4

8 7 6 5

RN803

8 7 6 5 1 2 3 4

11,12 11,12 11,12 11,12 11,12

+3.3V

B5 E16 AD16 ODTEN COMP1 COMP0 MP_DP_ AE2 XU1_MP_DP_

1K
*

1K

100

100

*

*

43.2

R161

R164

10

NI R1155
*

NI
10

43.2

B

CPUEND_GTLREF3 CPUEND_GTLREF2 CPUEND_GTLREF1 CPUEND_GTLREF0 F9 F23 W9 W23 GTLREF3 GTLREF2 GTLREF1 GTLREF0

SM_TSA1_CPUEND SM_TSA0_CPUEND 0
10 10 10

NI SM_A2_CPUEND SM_A1_CPUEND SM_A0_CPUEND S603AT 119919-001 1K
*

NI

NI B

1%

1%

13

139708-279

CPUEND_GTLREF[3:0]

Symbol 2 of 2
178342-001
SKTBGA603F

1K
*

1K
*

1K
*

1K
*

for signal integrity C183 C93 C180 C178 22UF
s1210t s1210t s1210t s1210t

VCCP decoupling

VCCP decoupling SIGNAL=VCCP;N1,N31,P30,R1,R31,T30,U1,U31,V30,W1,W31,Y30,AA1,AA31,AB30,AC31,AD30 C200 C116 C112 22UF 22UF 22UF
s1210t

I

I

C938 22UF
s1210t s1210t s1210t s1210t

C98 22UF 22UF 22UF 22UF

C141

C135

C96

C101

C140 C136 22UF
s1210t

C92 C921 22UF
s1210t

C936 C175 22UF
s1210t

C103 C121 22UF
s1210t

C145 C185 22UF
s1210t

C174

C94

C117

C139

C95

1UF

1UF

1UF

1UF

1UF

1UF

1UF

1UF

22UF

22UF

22UF
s1210t

22UF
s1210t

22UF
s1210t

22UF
s1210t

s805t

s805t

s805t

s805t

s805t

s805t

s805t

s805t

s1210t

s1210t

A .

100

R196

R199

R198

R200

R197

*

*

*

*

R14

H_SMI_ H_INIT_ H_STPCLK_ 1%

40.2

R18

NI NI NI

40.2

D

56

H_FERR_ H_IERR1_ GTL_MCERR_

D
*

HDR1X2

R214

R217

R218

R215

R216

A

SIZE

DRAWING NO.

REV

FOSTERB-2
COMPAQ CONFIDENTIAL 6 5 4

B
FILE: 3

010913-000
betty.10
2 SCALE: NONE SHEET 1

REV A
10
OF

80

8

7

8 6 5 4 3 2 1

7

12_PROC 12_PROC

117467-755

VCCP decoupling near VRM plane D C88 C87 22UF
s1210t X7R X7R X7R X7R X7R s1210t s1210t s1210t s1210t s1210t s1210t s1210t s1210t s1210t

D C132 C4 C131 22UF 22UF 22UF 22UF 22UF C90 22UF 22UF 22UF 22UF C107 C173 C5 C89 C902 C925 C844 C839 C867 0.1UF

1

+

16V

16V

C860

16V

C854

470UF

0.1UF

0.1UF

0.1UF

0.1UF

+5V C130 C106 22UF
s1210t s1210t s1210t s1210t s1210t s1210t s1210t

CAP200U

2

CAP200U

2

470UF

2

470UF

Y5V 1UF

C857

C840

1

+

1

+

C843

Y5V 1UF

CAP200U

20%

20%

20%

VCCP decoupling near VRM plane

C60 C78 C23 22UF 22UF C79 22UF 22UF 22UF

C62

C6 C22 22UF
s1210t

C21 22UF
s1210t

*

*

These parts go near the VRM section

22UF

22UF
s1210t

R860 100K

*

*

R856

R855 100K

*

R870

100K

R858 100K

100K

I

I

I

C

I

I

119919-138 C

VIDB0 VIDB1 VIDB2 VIDB3 VIDB4

8,12 8,12 8,12 8,12 8,12

Processor PAL

For VRM Heat sink guiding

E4

E9

I

I

C1HA1B

C1HA1B

+5V

DUMMYNET1

DUMMYNET2

1

1

100186-002

100186-002 B

OFF

OFF

B

*

*

*

*

*

8.2K

VIDA0 65-68 VIDA1 65-68 VIDA2 65-68 VIDA3 65-68 65-68 VIDA4
10,12 10,12 10,12 10,12 10,12

*

*

*

*

0

R126 0

R121 0

R120

0

R119 0

*

*

*

R125

NI

NI

NI

*

NI

NI

*

A

*

R854
6 5 4

R857 8.2K

8.2K

R859

R871 8.2K

R869 8.2K

NI

NI

NI

NI

NI

R127 R122 R128 R123 R129

CPUEND_VIDA0 0 0 CPUEND_VIDA1 CPUEND_VIDA2 0 CPUEND_VIDA3 0 0 CPUEND_VIDA4

A

SIZE

DRAWING NO.

REV

VRM decoupling & pullups
COMPAQ CONFIDENTIAL

B
FILE: 3

010913-000
betty.11
2 SCALE: NONE SHEET 1

REV A
11
OF

80

8

7

8 6 +5V In a 1P config, both VRMs get enabled but if the VRM is plugged, into the wrong slot, the VIDS are high and hence VCCP will be disabled.
*

7

5

4

3

2

1

COST OF LOGIC GATE SOLUTION: 70c as COMPARED TP 96c FOR PAL

8.2K

R137

D U28 7SZ32 U14 1 4 VRM_OUTEN
12,65-68

need new part shape NI

D

74LS688A 2 VRM_OUTEN 7SZ04 U7 Y_
(P=Q)

10,11 10,11 10,11 10,11 10,11

CPUEND_VIDA0 CPUEND_VIDA1 CPUEND_VIDA2 CPUEND_VIDA3 CPUEND_VIDA4 347910-004 4 COMP_OUTEN +5V

2 4 6 8 11 13 15 17 19 2

P0 P1 P2 P3 P4 P5 P6 P7

12,65-68

8,11 8,11 8,11 8,11 8,11

VIDB0 VIDB1 VIDB2 VIDB3 VIDB4 347910-003 C1269
* *

R136

G_

3 5 7 9 12 14 16 18 NI 8.2K

R26 8.2K

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 0.1UF

1
NI

192537-001 C VRM_OUTEN
12,65-68

C

7SZ32

2P_PRESENT_

10,49

SKT_OCC_PRI_

1

U29

SLOT2_OCC_ 2

4

P/D_NUM=347910-004

+5V

+5V NI

Place this jumper very close to gtl_a31 testpoint

U55
347910-010 7SZ125 JT_DIS_ E3 2 4 1

R1163
+3.3V

*

HDR1X2

*

R1181
*

150 106146-070

U6
74174 NI

1 VDD3_AUX;5

10K 119919-114

2 C2HA1A

NI

8.2K

R816

C

B

Q844

2

100186-014

B

B 1

3

SOT23FT

R1182
SKT_OCC_SEC_
8,16

106127-002 CLK

*

E

CLR_

3.6K 119919-103 C1270 I 47PF 119917-121
100186-014

3 4 6 11 13 14 D1 D2 D3 D4 D5 D6

Q1 Q2 Q3 Q4 Q5 Q6

2 5 7 10 12 15

GTL_A31_

7,9,15

VDD3_AUX

P/D_NUM=121708-001 9 1

VDD3_AUX

*

R1183
C2HA1A 2 GTL_RESET_ 1
4

*

R1184

2.2K 119919-098
NI HDR1X2

1K 119919-090

SIO_SLOT2_OCC_

PCI_CLK4 GTL_RESETB_
6,8,10,15

For proto purposes only

49

C

Q845
E40

2

B 1

A

3

SOT23FT

place the header after gtl_reset to ITP A

106127-002

*

R1185

E

1K 119919-090 SIZE DRAWING NO. REV

Comparator & JT disable
COMPAQ CONFIDENTIAL 6 5 4 U28 (the comparator) gets enabled only when there are 2Proc.

B
FILE: 3

010913-000
betty.12
2 SCALE: NONE SHEET 1

REV A
12
OF

80

8

7

8 6 5 4 3 2 1

7

C52 C147 0.01UF
S603AT S603AT S603AT S603AT

C30 0.01UF
S603AT

C32 0.01UF D

C114 0.01UF

C896 0.01UF

D

0.01UF

S603AT

1% 1% 49.9 49.9 49.9 49.9
* * * *

49.9

*

1% 1%

1%

1%

49.9

*

R172

R837

R201

R130

R162

R141

MAX trace length = 1.5" MCH_HAVREF
16 16

MIN_LINE_WIDTH=50

MAX trace length = 1.5"

MIN_LINE_WIDTH=50 MCH_HDVREF

1UF

1UF

CPUEND_GTLREF0 CPUEND_GTLREF1 CPUEND_GTLREF2 CPUEND_GTLREF3

10 10 10 10

1% C109 1UF 1UF 1UF 1UF
* * * *

1% C176 C104 1% 100 100 100 100 R142 C144 C102 C133 C108 1% 1% 1%

100

100

C159

Y5V

R171

R836

Y5V

C895

R202

NI
Y5V Y5V Y5V Y5V

NI

220PF

place near MCH

Place 220pF caps at processor pins

220PF

220PF

220PF

C

R131

R195

S603AT

S603AT

S603AT

C146
S603AT

*

*

C160

S603AT

C894

S603AT

220PF

220PF
16

C

16

HXRCOMP Place 1uF and 0.01uF caps at volltage divider 1%
*

HYRCOMP

1% 1% 20
* * * *

139708-140

49.9

*

1% 1% 49.9 49.9 49.9 49.9 R170

1%

1%

R209

*

R204

R82

100

C195

C196

*

R21

R79

1%

R33

16

20

MCH_CCVREF

MAX trace length = 1.5"

R210

Y5V

1UF

NI

CPUMID_GTLREF0 CPUMID_GTLREF1 CPUMID_GTLREF2 CPUMID_GTLREF3

8 8 8 8

220PF

C26

1% 100 100 100 100 1UF 1UF
* * * *

1% C75 C15

1UF

C65

C25

1UF

C49

1%

R32

R83

220PF

220PF

220PF

220PF

0.01UF

2

X7R

0.01UF

C168

105077-149 HYSWING
16

2

Y5V

C897

139708-025

Y5V

HXSWING

Place 1uF and 0.01uF caps at voltage divider Place 220pF caps at processor pins

16

2

2

Y5V

Y5V

139708-009

C53 0.01UF
S603AT

C148 0.01UF
S603AT

C150 0.01UF
S603AT

139708-009

A

Y5V

139708-025

105077-149

R20

R64

S603AT

S603AT

S603AT

C74

1%

C12

B

139708-001

B

S603AT

A

SIZE

DRAWING NO.

REV

GTL REFERENCE
COMPAQ CONFIDENTIAL 6 5 4

B
FILE: 3

010913-000
betty.13
2 SCALE: NONE SHEET 1

REV A
13
OF

80

8

7

8 6 5 4 3 2 1

7

MCH DECOUPLING
+1.8V

D

Verify Rail Voltage

COLUSA MCH DECOUPLING

D

R22
8

L800
C205 C188 C187
Y5V Y5V Y5V Y5V Y5V Y5V

1

L_VCCA C947 .01UF I I .01UF

1

4.7UH A C189

B

2

CPUMID_VCCA

C191

*

1/16W

5%

119919-018

142866-002

S1206T .01UF I I .01UF .01UF .01UF I I

*

C803

*

33UF

C802
8

33UF

CPUMID_VSSA C1070 C204
Y5V Y5V Y5V Y5V Y5V Y5V Y5V Y5V Y5V

C192 C213 C201
Y5V Y5V

C202 .01UF I I I I I I I I .01UF .01UF .01UF .01UF .01UF .01UF .01UF

C193 C898

C964 C152

C221

C190
Y5V

+
.01UF I I .01UF I 109764-087 .01UF

1 2

C940 150UF C TANTD

.01UF I

C
8

R23

L801

1

L_VCIOPLL

1

4.7UH A

B

2

CPUM_VCCIOPLL

*

1/16W

5%

119919-018

142866-002

S1206T

Place C close to VCCA, VSSA

C138 0.01UF
S603AT S603AT S603AT

C113 0.01UF 0.01UF

C137

Verify Rail Voltage

R826
10

L8

1

L_VCCA1

1

4.7UH A

B

2

CPUEND_VCCA

*

1/16W

5%

119919-018

142866-002

S1206T B

B

*

33UF

C873

*

R825
10

L7

1

33UF

C874
10

CPUEND_VSSA

L_VCIOPLL1

1

4.7UH A

B

2

CPUE_VCCIOPLL

*

1/16W

5%

119919-018

142866-002

S1206T A

A

Single circuit for 2 CPUs?

SIZE

DRAWING NO.

REV

CPU PLL VOLTAGE
COMPAQ CONFIDENTIAL 6 5 4

B
FILE: 3

010913-000
betty.14
2 SCALE: NONE SHEET 1

REV A
14
OF

80

8

7

8 6 GTL_A[35:17]_ A_DQA[8:0]
17

7

5

4

3

2

1

7,9,12

7,9 17 21 21

GTL_A[16:3]_ A_DQB[8:0] B_DQA[8:0] B_DQB[8:0]

41.2

GTL_A3_ GTL_A4_ GTL_A5_ GTL_A6_ GTL_A7_ GTL_A8_ GTL_A9_ GTL_A10_ GTL_A11_ GTL_A12_ GTL_A13_ GTL_A14_ GTL_A15_ GTL_A16_ GTL_A17_ GTL_A18_ GTL_A19_ GTL_A20_ GTL_A21_ GTL_A22_ GTL_A23_ GTL_A24_ GTL_A25_ GTL_A26_ GTL_A27_ GTL_A28_ GTL_A29_ GTL_A30_ GTL_A31_ GTL_A32_ GTL_A33_ GTL_A34_ GTL_A35_

A_DQA0 A_DQA1 A_DQA2 A_DQA3 A_DQA4 A_DQA5 A_DQA6 A_DQA7 A_DQA8

NI

B_DQB0 B_DQB1 B_DQB2 B_DQB3 B_DQB4 B_DQB5 B_DQB6 B_DQB7 B_DQB8

*

A_DQB0 A_DQB1 A_DQB2 A_DQB3 A_DQB4 A_DQB5 A_DQB6 A_DQB7 A_DQB8

B_DQA0 B_DQA1 B_DQA2 B_DQA3 B_DQA4 B_DQA5 B_DQA6 B_DQA7 B_DQA8

D

D

AE6 AF4 AH1 AH3 AG2 AH4 AJ1 AL3 AJ4 AK3 AM4 AL4 AK2 AL2 AF7 AG9 AH9 AM5 AJ10 AK6 AJ8 AH7 AJ5 AM7 AM8 AH6 AH10 AK5 AK9 AL9 AK8 AL6 AL7

AC29 AC27 AC31 AB28 AD30 AD28 AE31 AE27 AE29

T27 P31 P29 M29 P27 M31 N30 M27 N28

D23 F23 B23 E22 A24 E24 C24 D25 B25

R203

F16 B14 D14 D12 F14 B12 C13 F12 E13

U22

Check if these need to be removed from the colusa symbol

HA3_ HA4_ HA5_ HA6_ HA7_ HA8_ HA9_ HA10_ HA11_ HA12_ HA13_ HA14_ HA15_ HA16_ HA17_ HA18_ HA19_ HA20_ HA21_ HA22_ HA23_ HA24_ HA25_ HA26_ HA27_ HA28_ HA29_ HA30_ HA31_ HA32_ HA33_ HA34_ HA35_

CHA_DQA0 CHA_DQA1 CHA_DQA2 CHA_DQA3 CHA_DQA4 CHA_DQA5 CHA_DQA6 CHA_DQA7 CHA_DQA8

CHA_DQB0 CHA_DQB1 CHA_DQB2 CHA_DQB3 CHA_DQB4 CHA_DQB5 CHA_DQB6 CHA_DQB7 CHA_DQB8

CHB_DQA0 CHB_DQA1 CHB_DQA2 CHB_DQA3 CHB_DQA4 CHB_DQA5 CHB_DQA6 CHB_DQA7 CHB_DQA8

CHB_DQB0 CHB_DQB1 CHB_DQB2 CHB_DQB3 CHB_DQB4 CHB_DQB5 CHB_DQB6 CHB_DQB7 CHB_DQB8

CHA_CFM CHA_CFM_ CHA_CTM CHA_CTM_ CHA_CMD U30 V29 K32 L30 A_MCH_EXCC A_MCH_EXRC L32 A_MCH_LCMD R889 R890 AA32 AA31 A_MCH_LCTM A_MCH_LCTMN

Y31 Y32

A_MCH_LCFM A_MCH_LCFMN

17 17 17 17 17,19
1%
* *

+1.8V

8,10 8,10 8,10 8,10 8,10 6,8,10,12 8,10 8,10 8,10 8,10 8,10 8,10 8,10

GTL_ADS_ GTL_MCERR_ GTL_BNR_ GTL_BPRI_ GTL_BR0_ GTL_RESET_ GTL_DBSY_ GTL_DEFER_ GTL_DRDY_ GTL_HIT_ GTL_HITM_ GTL_LOCK_ GTL_TRDY_

AG11 AJ14 AM12 AK12 AM15 AL11 AJ12 AH12 AM13 AL13 AK13 AH13 AM14

ADS_ BERR_ BNR_ BPRI_ BREQ0_ CPURST_ DBSY_ DEFER_ DRDY_ HIT_ HITM_ HLOCK_ HTRDY_

COLUSA_MCH
Symbol 1 of 2 CHA_SCK CHA_SIO

CHA_EXCC CHA_EXRC

28 28
1%

A_MCH_LSCLK A_MCH_SIO

A_MCH_COL[4:0]

17,19 17

7,9 7,9

GTL_AP0_ GTL_AP1_

AK11 AH11

17

AP0_ AP1_

C

GTL_DP[3:0]_

GTL_DP0_ GTL_DP1_ GTL_DP2_ GTL_DP3_

P1 P4 P5 R2

7,9

DEP0_ DEP1_ DEP2_ DEP3_

CHA_RQ0 CHA_RQ1 CHA_RQ2 CHA_RQ3 CHA_RQ4 CHA_RQ5 CHA_RQ6 CHA_RQ7 CHB_CFM CHB_CFM_ CHB_CTM CHB_CTM_ CHB_CMD B20 A20 A21 B21 A11

R32 T29 T31 U28 U32 V27 V31 W28

A_MCH_COL0 A_MCH_COL1 A_MCH_COL2 A_MCH_COL3 A_MCH_COL4 A_MCH_ROW0 A_MCH_ROW1 A_MCH_ROW2 B_MCH_LCFM B_MCH_LCFMN B_MCH_LCTM B_MCH_LCTMN B_MCH_LCMD C17 B_MCH_EXCC D18 B_MCH_EXRC R167 R166
21 21 21 21

A_MCH_ROW[2:0]

C
17

GTL_DBI[3:0]_

GTL_DBI0_ GTL_DBI1_ GTL_DBI2_ GTL_DBI3_

A3 K1 V2 AC1

7,9

DINV0_ DINV1_ DINV2_ DINV3_

GTL_ADSTB[1:0]_

7,9

GTL_ADSTB0_ GTL_ADSTB1_

AJ2 AJ7

HASTBN0_ HASTBN1_

+1.8V
19,21
1%
*

28 CHB_EXCC CHB_EXRC CHB_SCK CHB_SIO
*

GTL_DSTBN[3:0]_

GTL_DSTBN0_ GTL_DSTBN1_ GTL_DSTBN2_ GTL_DSTBN3_

G3 N4 T3 AA3

28
1%

7,9

HDSTBN0_ HDSTBN1_ HDSTBN2_ HDSTBN3_

A10 C11

B_MCH_LSCLK B_MCH_SIO

B_MCH_COL[4:0]
21

19,21 21

GTL_DSTBP[3:0]_

GTL_DSTBP0_ GTL_DSTBP1_ GTL_DSTBP2_ GTL_DSTBP3_

H1 N3 T1 AA2

7,9

HDSTBP0_ HDSTBP1_ HDSTBP2_ HDSTBP3_

B_MCH_ROW[2:0]
21

GTL_REQ[4:0]_ P/D_NUM=175170-001

GTL_REQ0_ GTL_REQ1_ GTL_REQ2_ GTL_REQ3_ GTL_REQ4_

AG3 AF2 AF1 AF5 AE4

8,10

HREQ0_ HREQ1_ HREQ2_ HREQ3_ HREQ4_

GND;A12,A13,A14,A16,A18,A19,A22,A23,A25,AA1,AA10,AA11 GND;AA16,AA17,AA22,AA23,AA24,AA25,AA26,AA28,AA30,AA4 GND;AA7,AA8,AA9,AB12,AB13,AB14,AB15,AB18,AB19,AB20,AB21 GND;AB26,AB27,AB29,AB31,AB32,AC12,AC13,AC14,AC15,AC18 GND;AC19,AC20,AC21,AC26,AC28,AC3,AC30,AC32,AC6,AC7,AD12 GND;AD13,AD14,AD15,AD18,AD19,AD20,AD21,AD26,AD27,AD29 GND;AD31,AD32,AE12,AE13,AE14,AE15,AE18,AE19,AE2,AE20,AE21 GND;AE26,AE28,AE30,AE32,AE5,AE7,AF10,AF14,AF15,AF16,AF23 GND;AF29,AF31,AG1,AG15,AG16,AG24,AG4,AG8,AH14,AH22,AH28 GND;AH31,AH8,AJ13,AJ20,AJ26,AJ3,AJ6,AK10,AK18,AK24,AK30 GND;AL12,AL22,AL28,AL5,AL8,AM20,AM26,B11,B13,B15,B17,B19 GND;B22,B24,B26,B4,B7,C1,C12,C14,C16,C18,C20,C21,C23,C25 GND;C28,C3,C30,D13,D15,D17,D19,D22,D24,D32,D6,D9,E11,E12 GND;E14,E15,E16,E18,E20,E21,E23,E25,E28,E3,F11,F13,F17 GND;F19,F22,F24,F30,G10,G12,G13,G14,G15,G16,G17,G18,G19 GND;G2,G20,G21,G22,G23,G24,G25,G26,G5,H12,H13,H14,H15 GND;H18,H19,H20,H21,H28,H31,H7,J1,J12,J13,J14,J15,J18 GND;J19,J20,J21,J26,J4,J7,K12,K13,K14,K15,K18,K19,K20 GND;K21,K29,L12,L13,L14,L15,L18,L19,L20,L21,L26,L28,L3 GND;L31,L6,L7,M10,M11,M16,M17,M22,M23,M24,M25,M26,M28 GND;M30,M32,M8,M9,N10,N11,N16,N17,N2,N22,N23,N24,N25,N26 GND;N27,N29,N31,N32,N5,N8,N9,P10,P11,P16,P17,P22,P23,P24 GND;P25,P26,P28,P30,P32,P8,P9,R1,R10,R11,R16,R17,R22,R23 GND;R24,R25,R26,R28,R29,R31,R4,R7,R8,R9,T12,T13,T14,T15 GND;T18,T19,T20,T21,T26,T28,T30,T32,U12,U13,U14,U15,U18 GND;U19,U20,U21,U26,U27,U29,U3,U31,U6,U7,V10,V11,V16,V17 GND;V22,V23,V24,V25,V26,V28,V30,V32,V8,V9,W10,W11,W16 GND;W17,W2,W22,W23,W24,W25,W26,W27,W29,W31,W32,W5,W7,W8 GND;W9,Y10,Y11,Y16,Y17,Y22,Y23,Y24,Y25,Y26,Y28,Y30,Y8,Y9 CHB_RQ0 CHB_RQ1 CHB_RQ2 CHB_RQ3 CHB_RQ4 CHB_RQ5 CHB_RQ6 CHB_RQ7 A15 D16 B16 E17 A17 F18 B18 E19

B_MCH_COL0 B_MCH_COL1 B_MCH_COL2 B_MCH_COL3 B_MCH_COL4 B_MCH_ROW0 B_MCH_ROW1 B_MCH_ROW2

B

8,10

GTL_RSP_

D3 B2 E1 E4 C2 F2 E2 D4 D1 F3 G4 G1 H2 G6 H4 H5 K6 J5 K4 J3 K3 J2 L4 L5 N1 M3 L2 M5 M2 L1 N6 P2 T4 R3 R5 U2 R6 U5 U1 U4 V5 V3 W1 V6 W4 W3 Y5 Y4 Y2 AA6 AA5 AB6 Y1 AB3 AB1 AB4 AC5 AD2 AD3 AE3 AD5 AC4 AC2 AE1

HD0_ HD1_ HD2_ HD3_ HD4_ HD5_ HD6_ HD7_ HD8_ HD9_ HD10_ HD11_ HD12_ HD13_ HD14_ HD15_ HD16_ HD17_ HD18_ HD19_ HD20_ HD21_ HD22_ HD23_ HD24_ HD25_ HD26_ HD27_ HD28_ HD29_ HD30_ HD31_ HD32_ HD33_ HD34_ HD35_ HD36_ HD37_ HD38_ HD39_ HD40_ HD41_ HD42_ HD43_ HD44_ HD45_ HD46_ HD47_ HD48_ HD49_ HD50_ HD51_ HD52_ HD53_ HD54_ HD55_ HD56_ HD57_ HD58_ HD59_ HD60_ HD61_ HD62_ HD63_

8,10

GTL_RS[2:0]_

GTL_RS0_ GTL_RS1_ GTL_RS2_

AM11 AL10 AM10 AK14

RS0_ RS1_ RS2_ RSP_

B HS_RET1 HS_RET2 HS_RET3 HS_RET4 1013 1014 1015 1016

CLOSE TO MCH PACKAGE
DECOUPLING FOR GTL DATA SIGNALS

CLOSE TO MCH PACKAGE
7,9

7,9

C155 0.01UF
S603AT

C154 0.01UF
S603AT

C153 0.01UF
S603AT

C31 0.01UF
S603AT

C64 0.01UF
S603AT

C166 0.01UF
S603AT

C181 0.01UF
S603AT

C194 0.01UF
S603AT

C97 0.01UF
S603AT

GTL_D0_ GTL_D1_ GTL_D2_ GTL_D3_ GTL_D4_ GTL_D5_ GTL_D6_ GTL_D7_ GTL_D8_ GTL_D9_ GTL_D10_ GTL_D11_ GTL_D12_ GTL_D13_ GTL_D14_ GTL_D15_ GTL_D16_ GTL_D17_ GTL_D18_ GTL_D19_ GTL_D20_ GTL_D21_ GTL_D22_ GTL_D23_ GTL_D24_ GTL_D25_ GTL_D26_ GTL_D27_ GTL_D28_ GTL_D29_ GTL_D30_ GTL_D31_ GTL_D32_ GTL_D33_ GTL_D34_ GTL_D35_ GTL_D36_ GTL_D37_ GTL_D38_ GTL_D39_ GTL_D40_ GTL_D41_ GTL_D42_ GTL_D43_ GTL_D44_ GTL_D45_ GTL_D46_ GTL_D47_ GTL_D48_ GTL_D49_ GTL_D50_ GTL_D51_ GTL_D52_ GTL_D53_ GTL_D54_ GTL_D55_ GTL_D56_ GTL_D57_ GTL_D58_ GTL_D59_ GTL_D60_ GTL_D61_ GTL_D62_ GTL_D63_ GTL_D[47:32]_ GTL_D[63:48]_
7,9

DECOUPLING FOR GTL ADDR&CONTROL SIGNALS

GTL_D[15:0]_

A GTL_D[31:16]_

C163
7,9

C161

C162

C158

C157

C156

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

0.01UF

A

S603AT

S603AT

S603AT

S603AT

S603AT

S603AT

SIZE

DRAWING NO.

REV

COLUSA-1
COMPAQ CONFIDENTIAL 6 5 4

B
FILE: 3

010913-000
betty.15
2 SCALE: NONE SHEET 1

REV A
15
OF

80

8

7

8 6 AGP_AD[31:00]
24 24 33 33

7

5

4

3

2

1

AGP MCH Decoupling AGP_CBE[3:0]_

VDDQ

16,24,25,60

272777-002

C151 C219
0.01UF 0.01UF U22 0.01UF

*

*

*

HL_STB HL_STB_

NC_HLBSTB1 NC_HLBSTB1_

NC_HLBSTB0 NC_HLBSTB0_

AG32 AH32 AK32 AF32 AJ31 AK31 AL31 AF30 AM30 AH29 AG29 AL29 AF28 AG28 AJ28 AM28 AG25 AJ25 AM25 AH24 AJ24 AK23 AM24 AG22 AM22 AF21 AH21 AJ21 AM21 AG20 AH20 AK20

AL30 AM27 AL26 AL23

D28 C27

E32 D31

H32 G31

C6 D5

NC_HLCSTB0 NC_HLCSTB0_

C9 D8

NC_HLCSTB1 NC_HLCSTB1_

AH30 NC_HLDSTB0 AG31 NC_HLDSTB0_

AL27 NC_HLDSTB1 AK28 NC_HLDSTB1_

AL24 NC_HLESTB0 AK25 NC_HLESTB0_

AJ22 NC_HLESTB1 AH23NC_HLESTB1_

D

C217

D

R228 2
MIN_LINE_WIDTH=25

HLASTB HLASTB_

HLDSTB1 HLDSTB1_

HLESTB0 HLESTB0_

HLBSTB0 HLBSTB0_

HLBSTB1 HLBSTB1_

HLCSTB0 HLCSTB0_

HLCSTB1 HLCSTB1_

HLDSTB0 HLDSTB0_

HLESTB1 HLESTB1_

CHA_VREF0 CHA_VREF1 100 R165 2 100
1%

Y29 AA29
MIN_LINE_WIDTH=25

A_RIMM_VREF

17,18

GAD0_PDD5 GAD1_PDD7 GAD2_PDD3 GAD3_PDD1 GAD4_PDD9 GAD5_PDD6 GAD6_PDD12 GAD7 GAD8_PDD13 GAD9_PDD4 GAD10_PDD2 GAD11_PDD15 GAD12_PDD14 GAD13_PDD10 GAD14_PDD0 GAD15 GAD16_PDE2 GAD17_PDE1 GAD18_PDE0 GAD19_PDE5 GAD20_PDE4 GAD21_PDE7 GAD22_PDE3 GAD23_PDE6 GAD24_PDE8 GAD25_PDE13 GAD26_PDE12 GAD27_PDE10 GAD28_PDE9 GAD29_PDE15 GAD30_PDE14 GAD31_PDE11

GCBE0_PDD11 GCBE1_PDD8 GCBE2 GCBE3

CHB_VREF0 CHB_VREF1
MIN_LINE_WIDTH=25

D20 D21 AF8 AD6

B_RIMM_VREF
MIN_LINE_WIDTH=25

21,22

24,25 24,25 24,25 24,25 24,25 24,25 24,25 24,25 24,25

AGP_DEVSEL_ AGP_FRAME_ AGP_GNT_ AGP_IRDY_ AGP_PAR AGP_REQ_ AGP_SERR_ AGP_STOP_ AGP_TRDY_ HAREF0 HAREF1 HOST_REF_V J6 M6 T6 W6

AH26 AG26 AM17 AK26 AF27 AL16 AG27 AJ27 AH27

GDEVSEL_ GFRAME_RQMD GGNT_RQME GIRDY_ GPAR_PSTOPD GREQ_RQIE GSERR_ GSTOP_RQID GTRDY_PARD

MCH_HAVREF

13

24,25

AGP_PIPE_

AG17

PIPE_

COLUSA_MCH
175170-001 Symbol 2 of 2 HUB_COMP_v HLRCOMPA HLRCOMPB HLRCOMPC HLRCOMPD E29 K27 F7 AF24

HDVREF0 HDVREF1 HDVREF2 HDVREF3 NC_HLRCOMPB NC_HLRCOMPC NC_HLRCOMPD

MCH_HDVREF HLRCOMPA +1.8V

13

C HUB_REF HLREFA HLREFB HLREFC F27 K28 F6

AGP_SBA[7:0]

24

AL18 AJ18 AH18 AG18 AJ19 AG19 AF19 AL20

C HLREFA_MCH HLREF_NC C1268 0.01UF
16 16

SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7

24,25 24,25

AGP_RBF_ AGP_WBF_ HUB_COMP_REF_V HOST_COMP_V HOST_COMP_REFV HLSWNGB HLSWNGC HLSWNGD HRCOMP0 HRCOMP1 HSWNG0 HSWNG1

AH17 AM18

RFB_ WBF_

24,25 24,25 24,25

AGP_ST0 AGP_ST1 AGP_ST2

AL17 AK17 AJ17

ST0_HLE18 ST1_HLE19 ST2

K26 G8 AF25 AF13 P7 AF12 N7

NI

0.1UF C215 HXRCOMP HYRCOMP HXSWING HYSWING MCH_CCVREF R221 I
*

24,25 24,25

AGP_ADSTB0 AGP_ADSTB0_

AK29 AJ30

AD_STB0 AD_STB0_

13 13 13 13 13

24,25 24,25

AGP_ADSTB1 AGP_ADSTB1_

AL21 AK22

AD_STB1 AD_STB1_

24,25 24,25

AGP_SBSTB AGP_SBSTB_

AM19 AK19

SB_STB SB_STB_

4 4

CLK_MCH CLK_MCH_

AG6 AG7

BCLK0 BCLK1

CCVREF PRCOMPE_AGP PREFD_AGPREF0 PREFE_AGPREF1 PSWNGE_AGP BUSPARK HLAENH_

AG13 AF17 AF26 AF18 AF20 AH16 AH15 HLAENH_

5 5

HCLKOUT_A RCLKOUT_A

K31 K30

CHA_HCLKOUT CHA_RCLKOUT

VDD1_8;A6,A9,AA12,AA13,AA14,AA15,AA18,AA19,AA20,AA21 VDD1_8;AB10,AB11,AB16,AB17,AB22,AB23,AB24,AB25,AB8 VDD1_8;AB9,AC10,AC11,AC16,AC17,AC22,AC23,AC24,AC25,AC8 VDD1_8;AC9,AD10,AD11,AD16,AD17,AD22,AD23,AD24,AD25,AD8 VDD1_8;AD9,AE10,AE11,AE16,AE17,AE22,AE23,AE24,AE25,AE8,AG5 VDD1_8;AE9,AF22,B29,B31,C5,C8,D11,D26,D27,E10 VDD1_8;E31,E7,G11,G29,G32,G7,G9,H10,H11 VDD1_8;H16,H17,H22,H23,H24,H25,H26,H8,H9,J10,J11,J16 VDD1_8;J17,J22,J23,J24,J25,J27,J30,J8,J9,K10,K11,K16,K17 VDD1_8;K22,K23,K24,K25,K8,K9,L10,L11,L16,L17,L22 VDD1_8;L23,L24,L25,L27,L29,L8,L9,M12,M13,M14,M15,M18,M19 VDD1_8;M20,M21,N12,N13,N14,N15,N18,N19,N20,N21,P12,P13 VDD1_8;P14,P15,P18,P19,P20,P21,R12,R13,R14,R15,R18,R19 VDD1_8;R20,R21,T10,T11,T16,T17,T22,T23,T24,T25 VDD1_8;T8,T9,U10,U11,U16,U17,U22,U23,U24,U25,U8,U9,V12 VDD1_8;V13,V14,V15,V18,V19,V20,V21,W12,W13,W14,W15,W18 VDD1_8;W19,W20,W21,Y12,Y13,Y14,Y15,Y18,Y19,Y20,Y21 VCCP;AB2,AB5,AB7,AD1,AD4,AD7,AF11,AF3,AF6,AF9,AG10,AG12 VCCP;AG14,AH2,AH5,AJ11,AJ9,AK1,AK4,AK7,AL14,AM3,AM6 VCCP;AM9,B3,D2,F1,F4,H3,K2,M1,M4,M7,P3,P6,T2,T5,T7,V1,V4 VCCP;V7,Y3,Y6,Y7,K5,K7,H6 VDDQ;AG21,AG30,AH19,AH25,AJ23,AJ29,AJ32,AK21,AK27,AL19 VDDQ;AL25,AM23,AM29 NC;AL15,AJ15,AK15

300

AGP_VREF_CG

24

P403 R830 NI 1K R225 1%
* *

5 5

HCLKOUT_B RCLKOUT_B

B10 C10

CHB_HCLKOUT CHB_RCLKOUT

B

NI

4

B 1 2 3

HDR1X3

32,39,45,49

HLA0 HLA1 HLA2 HLA3 HLA4 HLA5 HLA6 HLA7 HLA8 HLA9 HLA10 HLA11 HLB0 HLB1 HLB2 HLB3 HLB4 HLB5 HLB6 HLB7 HLB8 HLB9 HLB10 HLB11 HLB12 HLB13 HLB14 HLB15 HLB16 HLB17 HLB18 HLB19

HLC0 HLC1 HLC2 HLC3 HLC4 HLC5 HLC6 HLC7 HLC8 HLC9 HLC10 HLC11 HLC12 HLC13 HLC14 HLC15 HLC16 HLC17 HLC18 HLC19

GCLKIN OVERT_ ICH_RST_ TESTIN_

AG23 AJ16 AM16 AK16

GCLKIN OVERT_ RSTIN_ TESTIN_

CHB_RAC7 CHB_RAC6 CHB_RAC5 CHB_RAC4 CHB_RAC3 CHB_RAC2 CHB_RAC1 CHA_RAC6 CHA_RAC5 CHA_RAC4 CHA_RAC3 CHA_RAC2 CHA_RAC1

D29 C29 A29 B28 A28 B27 A27 A26 E26 E27 F26 C26

0.01UF

B30 D30 A30 C31 C32 F31 F32 E30 J31 F28 F29 J28 H30 H29 J32 J29 G30 G27 H27 G28

F5 E5 E6 C4 A5 A4 B6 B5 E9 F8 B8 F10 B9 F9 E8 D10 A8 D7 A7 C7

+1.8V

C207

0.1UF

R220

30.1

R205

C214

*

1%

5% I

*

1% 40.2

*

X7R

*

R226

C212

NC_HLC00 NC_HLC01 NC_HLC02 NC_HLC03 NC_HLC04 NC_HLC05 NC_HLC06 NC_HLC07 NC_HLC08 NC_HLC09 NC_HLC10 NC_HLC11 NC_HLC12 NC_HLC13 NC_HLC14 NC_HLC15 NC_HLC16 NC_HLC17 NC_HLC18 NC_HLC19

VDDQ CHB_RAC

*

R227

150

HL[00:11] L805 1
3.3NH

A

1%

HL00 HL01 HL02 HL03 HL04 HL05 HL06 HL07 HL08 HL09 HL10 HL11

1%

HLREFA_MCH

+1.8V

16,24,25,60

NC_HLB00 NC_HLB01 NC_HLB02 NC_HLB03 NC_HLB04 NC_HLB05 NC_HLB06 NC_HLB07 NC_HLB08 NC_HLB09 NC_HLB10 NC_HLB11 NC_HLB12 NC_HLB13 NC_HLB14 NC_HLB15 NC_HLB16 NC_HLB17 NC_HLB18 NC_HLB19

16

100

0.1UF

150

*

*

R829 1K

NI

*

150 2

33

C1254
X7R

C186 1UF .1UF
S603T

C203
8,12

A 0 SKT_OCC_SEC_ 1UF
S603T
204432-004 *

R168

I R831 I SIZE DRAWING NO.
204432-004

139708-009

HLREF_NC

33,63

VDD1_8

16

MIN_LINE_WIDTH=010

1%

REV

*

R169

301 I 1 .1UF

C1260
X7R

I

L806 2

139708-025

B
COMPAQ CONFIDENTIAL
3.3NH

010913-000
FILE:

REV A
betty.16
SCALE: NONE SHEET

COLUSA-2
6

224246-001 I 5

16
4 3 2 1

OF

80

8

7

8 6 5 4 3 2 1

7

Get SIO connection story from RAMBUS. NOTE: 360107-001 is part number of 168 pin RIMM socket.

XMM1
RDRAM_RIMM_168
-001 = .062" PCB -002 = .093" PCB D

Our routing: RAC->SIN SOUT->SIN SOUT->SIN SOUT->TERM. Intel routing: RAC->SOUT SIN->SIN SOUT->SOUT SIN->TERM.

08/21/98: Rambus says our method is correct!

D

18 15 15 15 15 15 15 15 15 15

NC_MTH_RST_ A_DQA8 A_DQA7 A_DQA6 A_DQA5 A_DQA4 A_DQA3 A_DQA2 A_DQA1 A_DQA0 B38 A2 B2 A4 B4 A6 B6 A8 B8 A10 MTH_RST_ LDQA8 LDQA7 LDQA6 LDQA5 LDQA4 LDQA3 LDQA2 LDQA1 LDQA0 (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) B69 A67 B67 A65 B65 A63 B63 A61 A71 A73 B75 B73 B51 A51 RM1_RROW2 RM1_RROW1 RM1_RROW0 RM1_RCOL4 RM1_RCOL3 RM1_RCOL2 RM1_RCOL1 RM1_RCOL0 RM1_RCTM RM1_RCTMN RM1_RCFM RM1_RCFMN RM1_RCMD RM1_RSCLK RIMM_VCMOS (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) RDQB8 RDQB7 RDQB6 RDQB5 RDQB4 RDQB3 RDQB2 RDQB1 RDQB0 B53 A53 B55 A55 B57 A57 B59 A59 B61 RM1_RDQB8 RM1_RDQB7 RM1_RDQB6 RM1_RDQB5 RM1_RDQB4 RM1_RDQB3 RM1_RDQB2 RM1_RDQB1 RM1_RDQB0
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18

BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL

MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018

(RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL)

RDQA8 RDQA7 RDQA6 RDQA5 RDQA4 RDQA3 RDQA2 RDQA1 RDQA0

A83 B83 A81 B81 A79 B79 A77 B77 A75 RM1_RDQA8 RM1_RDQA7 RM1_RDQA6 RM1_RDQA5 RM1_RDQA4 RM1_RDQA3 RM1_RDQA2 RM1_RDQA1 RM1_RDQA0
18 18 18 18 18 18 18 18 18

15 15 15 15 15 15 15 15 15

A_DQB8 A_DQB7 A_DQB6 A_DQB5 A_DQB4 A_DQB3 A_DQB2 A_DQB1 A_DQB0 LDQB8 LDQB7 LDQB6 LDQB5 LDQB4 LDQB3 LDQB2 LDQB1 LDQB0

BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL

MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018

B32 A32 B30 A30 B28 A28 B26 A26 B24

C A20 B20 A22 B22 A24 LCOL4 LCOL3 LCOL2 LCOL1 LCOL0 (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) RCTM RCTMN RCFM RCFMN RCMD RSCLK A35 A37 B35 B37 (RSL) (RSL) (CMOS) (CMOS) (CMOS) (CMOS) (CMOS) (CMOS) VREF1 VREF2 TPOINT=OFF C168HZ4C 360107-001 A43 B43 C998
X7R

15 15 15

A_MCH_ROW2 A_MCH_ROW1 A_MCH_ROW0 (RSL) (RSL) (RSL) RROW2 RROW1 RROW0 RCOL4 RCOL3 RCOL2 RCOL1 RCOL0 (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (CMOS) (CMOS) (RSL) (RSL) (RSL)

BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL

MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018

B16 LROW2 A18 LROW1 B18 LROW0

C

15 15 15 15 15

A_MCH_COL4 A_MCH_COL3 A_MCH_COL2 A_MCH_COL1 A_MCH_COL0 A14 LCTM A12 LCTMN B10 LCFM B12 LCFMN B34 LCMD A34 LSCLK B36 SIN A36 SOUT VCMOS1 VCMOS2 VCMOS3 VCMOS4

BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL

MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018

15 15

A_MCH_LCTM A_MCH_LCTMN

BUS_NAME=RSL BUS_NAME=RSL

MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018

15 15

A_MCH_LCFM A_MCH_LCFMN

BUS_NAME=RSL BUS_NAME=RSL

MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018

15,19 15,19

A_MCH_LCMD A_MCH_LSCLK

BUS_NAME=RSL BUS_NAME=RSL

MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018

15

18

A_MCH_SIO RM1_SIO

18,21,22,40 18,21,22,40

MEM_SMBCLK MEM_SMBDAT (CMOS) (CMOS) (CMOS) (CMOS)

A_RIMM_VREF

16-18

+3.3V

J9_ID=000 (0)

R944

RIMM_SWP

0.01UF C1005
S603AT 20% 50V X7R

*

A45 SCL A47 SDA B49 SA2 B47 SA1 B45 SA0 A49 SWP

B

4.7K

B

20,63

VDD1_8_RSL

R1001

1%

*

RIMM_SWP

VDD2_5;A41,A42,A46,A50,B41,B42,B46,B50 VDD3;A48,B48

0.01UF NOTE: To achieve 28 ohm channel impedance, the RSL trace width must be 22 MILS, S603AT with a 6 MIL ground trace between signal traces. 20% The spacing between traces is 5 MILS. 50V This assumes a 60 ohm board with 6 layer stackup, dielectric thickness of 5 MILS, dielectric material is FR-4, and 5 MIL traces with 5 MIL spacing.

162

18,21,22,33

139708-217

GROUND SPACE

5 MILS 5 MILS RSL TRACE SPACE GROUND SPACE 19 MILS 5 MILS 5 MILS 5 MILS A RSL TRACE . . . . . SIZE DRAWING NO. REV 19 MILS

A_RIMM_VREF

16-18

2.48MA

GND;A1,A11,A13,A15,A17,A19,A21,A23,A25,A27 GND;A29,A3,A31,A33,A39,A5,A44,A52,A54,A56 GND;A58,A60,A7,A62,A64,A66,A68,A70,A72,A74 GND;A76,A78,A80,A9,A82,A84,B1,B11,B13,B15 GND;B17,B19,B21,B23,B25,B27,B29,B3,B31,B33 GND;B39,B5,B44,B52,B54,B56,B58,B60,B7,B62 GND;B64,B66,B68,B70,B72,B74,B76,B78,B80,B9,B82,B84

R1000

1%

*

560

A

139708-061

CHA RIMM 1
COMPAQ CONFIDENTIAL 6 5 4

B
FILE: 3

010913-000
betty.17
2 SCALE: NONE SHEET 1

REV A
17
OF

80

8

7

8 6 5 4 3 2 1

7

RDRAM_RIMM_168

XMM2
D

D B38 A2 B2 A4 B4 A6 B6 A8 B8 A10 MTH_RST_ LDQA8 LDQA7 LDQA6 LDQA5 LDQA4 LDQA3 LDQA2 LDQA1 LDQA0 (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) RROW2 RROW1 RROW0 (RSL) (RSL) (RSL) B69 A67 B67
BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018

17

20 20 20 20 20 20 20 20 20

NC_MTH_RST_ RM2_LDQA8 RM2_LDQA7 RM2_LDQA6 RM2_LDQA5 RM2_LDQA4 RM2_LDQA3 RM2_LDQA2 RM2_LDQA1 RM2_LDQA0 (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) RDQB8 RDQB7 RDQB6 RDQB5 RDQB4 RDQB3 RDQB2 RDQB1 RDQB0 B53 A53 B55 A55 B57 A57 B59 A59 B61
BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018

RDQA8 RDQA7 RDQA6 RDQA5 RDQA4 RDQA3 RDQA2 RDQA1 RDQA0 RM1_RDQB8 RM1_RDQB7 RM1_RDQB6 RM1_RDQB5 RM1_RDQB4 RM1_RDQB3 RM1_RDQB2 RM1_RDQB1 RM1_RDQB0 RM1_RROW2 RM1_RROW1 RM1_RROW0
17 17 17 17 17 17 17 17 17 17 17 17

A83 B83 A81 B81 A79 B79 A77 B77 A75
BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL 17 17 17 17 17 17 17 17 17 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018

RM1_RDQA8 RM1_RDQA7 RM1_RDQA6 RM1_RDQA5 RM1_RDQA4 RM1_RDQA3 RM1_RDQA2 RM1_RDQA1 RM1_RDQA0

20 20 20 20 20 20 20 20 20

RM2_LDQB8 RM2_LDQB7 RM2_LDQB6 RM2_LDQB5 RM2_LDQB4 RM2_LDQB3 RM2_LDQB2 RM2_LDQB1 RM2_LDQB0 LDQB8 LDQB7 LDQB6 LDQB5 LDQB4 LDQB3 LDQB2 LDQB1 LDQB0 B16 LROW2 A18 LROW1 B18 LROW0

B32 A32 B30 A30 B28 A28 B26 A26 B24

20 20 20

RM2_LROW2 RM2_LROW1 RM2_LROW0

C

20 20 20 20 20

RM2_LCOL4 RM2_LCOL3 RM2_LCOL2 RM2_LCOL1 RM2_LCOL0 LCOL4 LCOL3 LCOL2 LCOL1 LCOL0 (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) RCTM RCTMN RCFM RCFMN RCMD RSCLK B51 A51
BUS_NAME=RSL BUS_NAME=RSL

A20 B20 A22 B22 A24 (RSL) (RSL) (RSL) (RSL) (RSL) RCOL4 RCOL3 RCOL2 RCOL1 RCOL0 A71 A73
BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL

A65 B65 A63 B63 A61
BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL

MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018

RM1_RCOL4 RM1_RCOL3 RM1_RCOL2 RM1_RCOL1 RM1_RCOL0 RM1_RCTM RM1_RCTMN RM1_RCFM RM1_RCFMN RM1_RCMD RM1_RSCLK RIMM_VCMOS C1041
X7R

17 17 17 17 17 17 17 17 17 17 17 17,18

C

5 5

A_RM2_LCTM A_RM2_LCTMN (RSL) (RSL) (RSL) (RSL) (CMOS) (CMOS) VCMOS1 VCMOS2 VCMOS3 VCMOS4 A43 B43 C1044
X7R

A14 LCTM A12 LCTMN B10 LCFM B12 LCFMN (RSL) (RSL) (CMOS) (CMOS) (CMOS) (CMOS) (CMOS) (CMOS) VREF1 VREF2 TPOINT=OFF C168HZ4C 360107-001 A35 A37 B35 B37 B75 B73 B34 LCMD A34 LSCLK B36 SIN A36 SOUT

20 20

RM2_LCFM RM2_LCFMN

20 20

RM2_LCMD RM2_LSCLK

17

RM1_SIO RM2_SIO

17,21,22,40 17,21,22,40

MEM_SMBCLK MEM_SMBDAT J10_SA1 (CMOS)

0.01UF
50V 20% S603AT

A_RIMM_VREF

16,17

J10_ID=010 (2)

A45 SCL A47 SDA B49 SA2 B47 SA1 B45 SA0 A49 SWP (CMOS) (CMOS) (CMOS)

R1016

+3.3V

0.01UF
50V 20% S603AT

*

8.2K

R1002

B

*

8.2K

B

139708-218

17,21,22,33

RIMM_SWP

VDD2_5;A41,A42,A46,A50,B41,B42,B46,B50 VDD3;A48,B48

VDD2_5

22,59,61-63

R998

36.5

*

1%

GND;A1,A11,A13,A15,A17,A19,A21,A23,A25,A27 GND;A29,A3,A31,A33,A39,A5,A44,A52,A54,A56 GND;A58,A60,A7,A62,A64,A66,A68,A70,A72,A74 GND;A76,A78,A80,A9,A82,A84,B1,B11,B13,B15 GND;B17,B19,B21,B23,B25,B27,B29,B3,B31,B33 GND;B39,B5,B44,B52,B54,B56,B58,B60,B7,B62 GND;B64,B66,B68,B70,B72,B74,B76,B78,B80,B9,B82,B84

18.3ma

RIMM_VCMOS

17,18

R999

C1042 NOTES: Per Rambus: VDD=2.5v (RIMM power) VCMOS = 2.5v or 1.8v (was VT termination volage) SVDD = 3.3v (vdd of SPD device) VSR = 3.3v (PC100 sdram power) VREF = 1.4v (RSL reference voltage) SIZE DRAWING NO. REV A

1%

*

X7R

1.83v

100

0.01UF

A

139708-001

CHA RIMM 2
COMPAQ CONFIDENTIAL 6 5 4

B
FILE: 3

010913-000
betty.18
2 SCALE: NONE SHEET 1

REV A
18
OF

80

8

7

8 6 5 4 3 2 1

7

B_MCH_LCMD
15,21

D
C

D

Q806
B_MCH_LSCLK
15,21

B 1 3 E

2

MMBT100 106127-003 SOT23FT

7SZ00 1 2 150 347910-001 VDD3_AUX;5 139708-009
E 3
*

U30 R873 4
B 1 2

C

Q807
MMBT100 106127-003 SOT23FT

I A_MCH_LCMD
15,17 C

C

R1158
Q810
A_MCH_LSCLK
15,17 B 1 3 E 2

119919-001 MMBT100 106127-003 SOT23FT

C

*

32,49

SLP_S3_

S3_CONTROL_

0

R1157

*

32

SUS_STAT_

NI

119919-001 7SZ00 1 2
3 E
*

desktop is using SUS_STAT U807 4
B 1 2

0 R234 MMBT100 106127-003 SOT23FT
C

Q811

32,45,49,59

3V_PWRGD 150 347910-001 139708-009 VDD3_AUX;5

B

B

A

A

SIZE

DRAWING NO.

REV

SLP_S3
COMPAQ CONFIDENTIAL 6 5 4

B
FILE: 3

010913-000
betty.19
2 SCALE: NONE SHEET 1

REV A
19
OF

80

8

7

8 6 5 4 3 2 1

7

17,63

VDD1_8_RSL

D

NOTE: These RNETS really need to be 1% tolerance!

D

NOTE: Two decoupling caps. per RNET.
*

*

R996 R995 56
S603AT 5%

Place these CAPS near RNETS at left.

56

S603AT 5%

18

RM2_LSCLK C1067 C1059
X7R

18
*

RM2_LCMD R994 C1078 C1075 .1UF .1UF
X7R

*

R997 56
S603AT 5%

C1066 .1UF .1UF

C1040 C1064
X7R

+
.1UF

1 C1038 2 10UF 129621-019

+

1

C1080

56 .1UF .1UF

S603AT 5%

10UF 2 129621-019

*

18 18 18 18
* * *

RM2_LDQB1 RM2_LDQB2 RM2_LDQB3 RM2_LDQB4
1% 1% 1% 1%

R986 R987 R988 R989 28 28 28 28

C
*

C

*

18 18 18 18
* *

RM2_LDQB5 RM2_LDQB6 RM2_LDQB7 RM2_LDQB8
1% 1% 1% 1%

R990 R991 R992 R993 28 28 28 28 C1074 .1UF C1076 .1UF C1077 .1UF
50V 20%
*

C1072 .1UF
S603AT X7R 296166-004 20%

*

18 18 18 18
* * *

RM2_LCOL2 RM2_LCOL1 RM2_LCOL0 RM2_LDQB0
1% 1% 1% 1% S603AT X7R 296166-004

R982 R983 R984 R985 28 28 28 28

*

18 18 18 18
* *

RM2_LROW1 RM2_LROW0 RM2_LCOL4 RM2_LCOL3
1% 1% 1% 1%

R979 R978 R980 R981 28 28 28 28

C1071 .1UF C1073 .1UF C1068 .1UF C1079 .1UF
S603AT X7R S603AT X7R 296166-004 50V 20%

*

18 18 18 18
* * *

RM2_LDQA8 RM2_LDQA7 RM2_LDQA6 RM2_LDQA5
1% 1% 1% 1%

R968 R966 R969 R967 28 28 28 28

B
* *

B

*

18 18 18 18
*

RM2_LDQA4 RM2_LDQA3 RM2_LDQA2 RM2_LDQA1
1% 1% 1% 1%

R971 R970 R973 R972

28 28 28 28

*

18 S603AT 1%

RM2_LROW2 28

R977

C1069 .1UF
X7R 1% 25V

C1062 .1UF
S603AT X7R 296166-004 50V 20%

C1063 .1UF
S603AT X7R 296166-004 50V 20%

S603AT These are discretes for routing purposes.

*

18

RM2_LDQA0 28

R974

*

18 S603AT 1%

RM2_LCFMN 28 C289 .1UF
S603AT

R976 RCFMC

A R975
*

HRM: Add extra decoupling for 512MB

A

18 S603AT 1%

RM2_LCFM 28

X7R 296166-004 16V 10%

SIZE

DRAWING NO.

REV

CHA RSL TERMINATION
COMPAQ CONFIDENTIAL 6 5 4

B
FILE: 3

010913-000
betty.20
2 SCALE: NONE SHEET 1

REV A
20
OF

80

8

7

8 6 5 4 3 2 1

7

Get SIO connection story from RAMBUS. NOTE: 360107-001 is part number of 168 pin RIMM socket.

XMM3
RDRAM_RIMM_168
-001 = .062" PCB -002 = .093" PCB D

Our routing: RAC->SIN SOUT->SIN SOUT->SIN SOUT->TERM. Intel routing: RAC->SOUT SIN->SIN SOUT->SOUT SIN->TERM.

08/21/98: Rambus says our method is correct!

D

22
MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018

15 15 15 15 15 15 15 15 15

NC_MTH_RSTB_ B_DQA8 B_DQA7 B_DQA6 B_DQA5 B_DQA4 B_DQA3 B_DQA2 B_DQA1 B_DQA0 B38 A2 B2 A4 B4 A6 B6 A8 B8 A10 MTH_RST_ LDQA8 LDQA7 LDQA6 LDQA5 LDQA4 LDQA3 LDQA2 LDQA1 LDQA0 (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) RROW2 RROW1 RROW0 RCOL4 RCOL3 RCOL2 RCOL1 RCOL0 RCTM RCTMN RCFM RCFMN RCMD RSCLK A35 A37 B35 B37 B51 A51 B75 B73 A71 A73 A65 B65 A63 B63 A61 (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (CMOS) (CMOS) (CMOS) (CMOS) (CMOS) (CMOS) VREF1 VREF2 TPOINT=OFF C168HZ4C 360107-001 A43 B43 VCMOS1 VCMOS2 VCMOS3 VCMOS4 C941
X7R

BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL

(RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) RDQB8 RDQB7 RDQB6 RDQB5 RDQB4 RDQB3 RDQB2 RDQB1 RDQB0 B69 A67 B67 B_RM1_RROW2 B_RM1_RROW1 B_RM1_RROW0 B_RM1_RCOL4 B_RM1_RCOL3 B_RM1_RCOL2 B_RM1_RCOL1 B_RM1_RCOL0 B_RM1_RCTM B_RM1_RCTMN B_RM1_RCFM B_RM1_RCFMN B_RM1_RCMD B_RM1_RSCLK B_RIMM_VCMOS (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (CMOS) (CMOS) B53 A53 B55 A55 B57 A57 B59 A59 B61 B_RM1_RDQB8 B_RM1_RDQB7 B_RM1_RDQB6 B_RM1_RDQB5 B_RM1_RDQB4 B_RM1_RDQB3 B_RM1_RDQB2 B_RM1_RDQB1 B_RM1_RDQB0
22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22

RDQA8 RDQA7 RDQA6 RDQA5 RDQA4 RDQA3 RDQA2 RDQA1 RDQA0

A83 B83 A81 B81 A79 B79 A77 B77 A75
22 22 22 22 22 22 22 22 22

B_RM1_RDQA8 B_RM1_RDQA7 B_RM1_RDQA6 B_RM1_RDQA5 B_RM1_RDQA4 B_RM1_RDQA3 B_RM1_RDQA2 B_RM1_RDQA1 B_RM1_RDQA0

15 15 15 15 15 15 15 15 15

B_DQB8 B_DQB7 B_DQB6 B_DQB5 B_DQB4 B_DQB3 B_DQB2 B_DQB1 B_DQB0
MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018

BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL

B32 A32 B30 A30 B28 A28 B26 A26 B24 LDQB8 LDQB7 LDQB6 LDQB5 LDQB4 LDQB3 LDQB2 LDQB1 LDQB0 B16 LROW2 A18 LROW1 B18 LROW0 A20 B20 A22 B22 A24 LCOL4 LCOL3 LCOL2 LCOL1 LCOL0 A14 LCTM A12 LCTMN B10 LCFM B12 LCFMN B34 LCMD A34 LSCLK B36 SIN A36 SOUT

15 15 15 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018

B_MCH_ROW2 B_MCH_ROW1 B_MCH_ROW0
MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018

BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL

C

15 15 15 15 15

B_MCH_COL4 B_MCH_COL3 B_MCH_COL2 B_MCH_COL1 B_MCH_COL0

BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL

C

15 15

B_MCH_LCTM B_MCH_LCTMN

BUS_NAME=RSL BUS_NAME=RSL

15 15

B_MCH_LCFM B_MCH_LCFMN

BUS_NAME=RSL BUS_NAME=RSL

15,19 15,19

B_MCH_LCMD B_MCH_LSCLK

BUS_NAME=RSL BUS_NAME=RSL

15 22

B_MCH_SIO B_RM1_SIO

17,18,22,40 17,18,22,40

MEM_SMBCLK MEM_SMBDAT

B_RIMM_VREF

16,21,22

+3.3V

R880 (CMOS)

(CMOS) (CMOS) (CMOS)

0.01UF C971
S603AT 20% 50V X7R

with a 6 MIL ground trace between signal traces.

*

A45 SCL A47 SDA B49 SA2 B47 SA1 J30_SA0 B45 SA0 A49 SWP

4.7K +3.3V

B

B
S603AT 20%

23

B_VDD1_8_RSL

J30_ID=001 (1)

0.01UF NOTE: To achieve 28 ohm channel impedance, the RSL trace width must be 22 MILS,
50V

RIMM_SWP VDD2_5;A41,A42,A46,A50,B41,B42,B46,B50 VDD3;A48,B48

+
*

1

R923 R865 8.2K I

17,18,22,33

1%

22UF

C1026

*

The spacing between traces is 5 MILS. This assumes a 60 ohm board with 6 layer stackup, dielectric thickness of 5 MILS, dielectric material is FR-4, and 5 MIL traces with 5 MIL spacing.

2

162

139708-217

129621-026

GROUND SPACE

5 MILS 5 MILS RSL TRACE SPACE GROUND SPACE 20 MILS 5 MILS 5 MILS 5 MILS RSL TRACE . . . . . 20 MILS A

B_RIMM_VREF

16,21,22

2.48MA

GND;A1,A11,A13,A15,A17,A19,A21,A23,A25,A27 GND;A29,A3,A31,A33,A39,A5,A44,A52,A54,A56 GND;A58,A60,A7,A62,A64,A66,A68,A70,A72,A74 GND;A76,A78,A80,A9,A82,A84,B1,B11,B13,B15 GND;B17,B19,B21,B23,B25,B27,B29,B3,B31,B33 GND;B39,B5,B44,B52,B54,B56,B58,B60,B7,B62 GND;B64,B66,B68,B70,B72,B74,B76,B78,B80,B9,B82,B84

R875

C149

1%

X7R

*

560

0.01UF

139708-061

S603AT

A

20%

50V

121808-349

SIZE

DRAWING NO.

REV

CHB RIMM1
COMPAQ CONFIDENTIAL 6 5 4

B
FILE: 3

010913-000
betty.21
2 SCALE: NONE SHEET 1

REV A
21
OF

80

8

7

8 6 5 4 3 2 1

7

XMM4
RDRAM_RIMM_168

D MTH_RST_ LDQA8 LDQA7 LDQA6 LDQA5 LDQA4 LDQA3 LDQA2 LDQA1 LDQA0 (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) RROW2 RROW1 RROW0 (RSL) (RSL) (RSL) B69 A67 B67
BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018

21

D (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) RDQB8 RDQB7 RDQB6 RDQB5 RDQB4 RDQB3 RDQB2 RDQB1 RDQB0 B53 A53 B55 A55 B57 A57 B59 A59 B61
BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018

23 23 23 23 23 23 23 23 23

NC_MTH_RSTB_ B_RM2_LDQA8 B_RM2_LDQA7 B_RM2_LDQA6 B_RM2_LDQA5 B_RM2_LDQA4 B_RM2_LDQA3 B_RM2_LDQA2 B_RM2_LDQA1 B_RM2_LDQA0 B38 A2 B2 A4 B4 A6 B6 A8 B8 A10 RDQA8 RDQA7 RDQA6 RDQA5 RDQA4 RDQA3 RDQA2 RDQA1 RDQA0 B_RM1_RDQB8 B_RM1_RDQB7 B_RM1_RDQB6 B_RM1_RDQB5 B_RM1_RDQB4 B_RM1_RDQB3 B_RM1_RDQB2 B_RM1_RDQB1 B_RM1_RDQB0 B_RM1_RROW2 B_RM1_RROW1 B_RM1_RROW0
21 21 21 21 21 21 21 21 21 21 21 21

A83 B83 A81 B81 A79 B79 A77 B77 A75
BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 21 21 21 21 21 21 21 21 21

B_RM1_RDQA8 B_RM1_RDQA7 B_RM1_RDQA6 B_RM1_RDQA5 B_RM1_RDQA4 B_RM1_RDQA3 B_RM1_RDQA2 B_RM1_RDQA1 B_RM1_RDQA0

23 23 23 23 23 23 23 23 23

B_RM2_LDQB8 B_RM2_LDQB7 B_RM2_LDQB6 B_RM2_LDQB5 B_RM2_LDQB4 B_RM2_LDQB3 B_RM2_LDQB2 B_RM2_LDQB1 B_RM2_LDQB0 LDQB8 LDQB7 LDQB6 LDQB5 LDQB4 LDQB3 LDQB2 LDQB1 LDQB0 B16 LROW2 A18 LROW1 B18 LROW0

B32 A32 B30 A30 B28 A28 B26 A26 B24

23 23 23

B_RM2_LROW2 B_RM2_LROW1 B_RM2_LROW0

C

23 23 23 23 23

B_RM2_LCOL4 B_RM2_LCOL3 B_RM2_LCOL2 B_RM2_LCOL1 B_RM2_LCOL0 LCOL4 LCOL3 LCOL2 LCOL1 LCOL0 (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) (RSL) RCTM RCTMN RCFM RCFMN RCMD RSCLK B51 A51
BUS_NAME=RSL BUS_NAME=RSL

A20 B20 A22 B22 A24 (RSL) (RSL) (RSL) (RSL) (RSL) RCOL4 RCOL3 RCOL2 RCOL1 RCOL0 A71 A73
BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL

A65 B65 A63 B63 A61
BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL BUS_NAME=RSL

MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018 MIN_LINE_WIDTH=018

B_RM1_RCOL4 B_RM1_RCOL3 B_RM1_RCOL2 B_RM1_RCOL1 B_RM1_RCOL0 B_RM1_RCTM B_RM1_RCTMN B_RM1_RCFM B_RM1_RCFMN B_RM1_RCMD B_RM1_RSCLK B_RIMM_VCMOS C254
X7R

21 21 21 21 21 21 21 21 21 21 21 21,22

C

5 5

B_RM2_LCTM B_RM2_LCTMN (RSL) (RSL) (RSL) (RSL) (CMOS) (CMOS) B75 B73 B10 LCFM B12 LCFMN (RSL) (RSL) (CMOS) (CMOS) B34 LCMD A34 LSCLK

A14 LCTM A12 LCTMN

23 23

B_RM2_LCFM B_RM2_LCFMN

23 23

B_RM2_LCMD B_RM2_LSCLK

R232 B36 SIN A36 SOUT (CMO