Text preview for : 60139ic.pdf part of JVC GY-DV300 DV CAMCORDER
Back to : JVC GY-DV300 14parts !.pa | Home
4.21 IC BLOCK DIAGRAMS
AD9842AJST-W [ANALOG DEVICES] (CCD Signal Processors)
SDATA SL NC STBY NC SCK
THREE-STATE
AK6480AM-X [ASAHI KASEI] (8192bit EEPROM)
DVDD2 VRB
BA9738KV [ROHM] (6 Channel Switching Regurator Controller)
Pin Description
VRT CML
DVSS
48 47 46 45 44 43 42 41 40 39 38 37
(LSB) D0 1 D1 2 D2 3 D3 D4
4 5
PIN 1 IDENTIFIER
36 35 34 33
AUX1IN AVSS
D5 6 D6 7 D7 8 D8 9 D9 10 D10 11 (MSB) D11 12
AD9842A
TOP VIEW (Not to Scale)
AUX2IN AVDD2 32 BYP4
31 30 29
NC CCDIN
(Top View) Block Diagram
BYP2 28 BYP1 27 AVDD1
26 25
Pin Name CS SK DI DO RESET RDY/BUSY Vcc GND
Description Chip select Serial clock input Serial data input Serial data outout Reset input RDY/BUSY output Power supply Ground
AVSS AVSS
NC = NO CONNECT 13 14 15 16 17 18 19 20 21 22 23 24 DRVDD DRVSS DVSS DATACLK CLPDM VD DVDD1 HD PBLK CLPOB SHP SHD
PBLK
AVDD
AVSS
HD
VD
CLPOB
4dB
6dB
COLOR STEERING 2dB36dB 2:1 MUX
DRVDD CLP DRVSS
CCDIN
CDS
PxGA
10/12 VGA ADC DOUT
CLP 6 CLPDM 10 AUX1IN 2:1 MUX AUX2IN CLP CONTROL REGISTERS DVDD BUF 8 OFFSET DAC BANDGAP REFERENCE VRT VRB
INTERNAL BIAS
CML
AD9841A/AD9842A
SL
DIGITAL INTERFACE
INTERNAL TIMING
DVSS
BA3314F-X [ROHM] (Dual Pre-Amp. for Audio Signal)
SCK
SDATA
SHP
SHD
DATACLK
Pin Number 1, 2 3 12 1 12 13 14 15, 41 16 17 18 19 20 21 22 23 24 25, 26, 35 27 28 29 30 31 32 33 34 36 37 38 39 40 42 43 44 45 46 47 48
Name NC D0 D9 D0 D11 DRVDD DRVSS DVSS DATACLK DVDD1 HD PBLK CLPOB SHP SHD CLPDM VD AVSS AVDD1 BYP1 BYP2 CCDIN NC BYP4 AVDD2 AUX2IN AUX1IN CML VRT VRB DVDD2 THREE-STATE NC STBY NC SL SDATA SCK
Type NC DO DO P P P DI P DI DI DI DI DI DI DI P P AO AO AI NC AO P AI AI AO AO AO P DI NC DI NC DI DI DI
Description Internally Not Connected (AD9841A ONLY) Digital Data Outputs (AD9841A ONLY) Digital Data Outputs (AD9842A ONLY) Digital Output Driver Supply Digital Output Driver Ground Digital Ground Digital Data Output Latch Clock Digital Supply Horizontal Drive. Used with VD for Color Steering Control Preblanking Clock Input Black Level Clamp Clock Input CDS Sampling Clock for CCD's Reference Level CDS Sampling Clock for CCD's Data Level Input Clamp Clock Input Vertical Drive. Used with HD for Color Steering Control Analog Ground Analog Supply Internal Bias Level Decoupling Internal Bias Level Decoupling Analog Input for CCD Signal Internally Not Connected Internal Bias Level Decoupling Analog Supply Analog Input Analog Input Internal Bias Level Decoupling A/D Converter Top Reference Voltage Decoupling A/D Converter Bottom Reference Voltage Decoupling Digital Supply Digital Output Disable. Active High May be tied high or low. Do not leave floating. Standby Mode, Active High. Same as Serial Interface Internally Not Connected. May be Tied High or Low Serial Digital Interface Load Pulse Serial Digital Interface Data Serial Digital Interface Clock
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
4-39
4-39
AK4560AVQ [ASAHI KASEI] (16bit CODEC with ALC and MIC/HP/SPK-Amp)
Pin Description
Block Diagram
BU4094BCFV-X [ROHM] (8-Stage Shift/Store Register)
4-40
4-40
CXA3268AR-B [SONY] (Driver/Timing generator for color LCD)
Block diagram
Input Disposition
Input Disposition
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Pin Name VSS FIL OUT SYNC IN SYNC OUT CSYNC/HD DA OUT REF F ADJ GND1 VD DWN WIDE TST1 SCK SEN SDAT R INJECT VSS VDD VDD CKO CKI VSS RPD XCLR VDO HDO TST2 GND2 SIG.C B DC DET B OUT R DC DET R OUT G DC DET G OUT
I/O -- O I O I O O O -- I O O -- I I I O -- -- -- O I -- O I O O -- -- I O O O O O O
Description Ground terminal for digital 3.0V H FILTER output terminal (For Internal sync separation) Sync separation circuit input terminal (For Internal sync separation) Sync separation circuit output terminal (For Internal sync separation) CSYNC/Horizontal synchronizing signal input terminal DAC output terminal REF voltage output terminal for Level shifter circuit of LCD panel TRAP f0 adjusting resistor connecting terminal Ground terminal for analog 3.0V Vertical synchronizing signal input terminal Upper and lower invert switching signal output terminal 16:9 wide display switching pulse output terminal TEST terminal (OPEN) Serial clock input terminal Serial load input terminal Serial data input terminal Serial block current control resistor connecting terminal Ground terminal for digital 3.0V Power supply for digital 3.0V Power supply for digital 3.0V Oscillating cell output terminal Oscillating cell input terminal Ground terminal for digital 3.0V Phase comparison output terminal Power on reset capacitor connecting terminal (for timing output) VDO pulse output terminal HDO pulse output terminal TEST terminal (Connect to GND) Ground terminal for analog 12V "R,G,B,PSIG output DC voltage adjusting terminal" B signal DC voltage feedback circuit capacitor connecting terminal B signal output terminal R signal DC voltage feedback circuit capacitor connecting terminal R signal output terminal G signal DC voltage feedback circuit capacitor connecting terminal G signal output terminal
No. 37 38 39 40 41 42 43 44 45
Pin Name VCC2 PSIG DC DET PSIG OUT TST3 VCC3 COM GND3 TST4 POF NC TST5 TST6 TST7 TST8 TST9 TST10 VSS VSS VDD TST11 OSD B OSD R OSD G NC HCK1 HCK2 VCC1 HST EN VCK VST RGT FIL IN B / B-Y G /Y R / R-Y
I/O -- O O -- -- O -- -- O -- -- -- -- -- -- -- -- -- -- I I I O O -- O O O O O I I I I
Description Power supply for analog 12V G signal DC voltage feedback circuit capacitor connecting terminal PSIG signal output terminal TEST terminal (OPEN) Power supply for analog 12V COM(CS) Common electrode voltage output terminal (CS) for LCD panel Ground terminal for analog 12V COM(CS) TEST terminal (OPEN) LCD panel power ON/OFF terminal TEST terminal (Connect to GND) TEST terminal (Connect to GND) TEST terminal (OPEN) TEST terminal (OPEN) TEST terminal (OPEN) TEST terminal (OPEN) Ground terminal for digital 3.0V Ground terminal for digital 3.0V Power supply for digital 3.0V TEST terminal (Connect to GND) OSD B input terminal OSD R input terminal OSD G input terminal H clock pulse1 output terminal H clock pulse2 output terminal Power supply for analog 3.0V H start pulse output terminal EN pulse output terminal V clock pulse output terminal V start pulse output terminal Right and left invert switching signal output terminal H FILTER input terminal (For Internal sync separation) B/B-Y signal input terminal G/Y signal input terminal R/R-Y signal input terminal RGT : RIGHT SCAN and LEFT SCAN
L
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
H
* DWN : DOWN SCAN and UP SCAN H : Pull Up L : Pull Down
CD4053BPW-X [RCA] (Triple 2 Channel Analog Multiplexers/Demultiplexers)
4-41
4-41
CXA3503R-B [SONY] (Driver/Timing generator for color LCD)
Block diagram
Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin name VSS FIL OUT SYNC IN SYNC OUT CSYNC/HD DA OUT TST1 F ADJ GND1 VD VST TST2 TST3 SCK SEN SDAT R INJECT VSS VDD VDD CKO CKI VSS RPD XCLR VDO HDO TST4 GND2 SIG.C B DC DET B OUT R DC DET R OUT G DC DET G OUT I/O O I O I O O I O I I I O O I O I O O I O O O O O O Description Ground terminal for digital 3.0V H FILTER output terminal (For Internal sync separation) Sync separation circuit input terminal (For Internal sync separation) Sync separation circuit output terminal (For Internal sync separation) CSYNC/Horizontal synchronizing signal input terminal DAC output terminal TEST terminal (OPEN) TRAP f0 adjusting resistor connecting terminal Ground terminal for analog 3.0V Vertical synchronizing signal input terminal V start pulse output terminal TEST terminal (OPEN) TEST terminal (OPEN) Serial clock input terminal Serial load input terminal Serial data input terminal Serial block current control resistor connecting terminal Ground terminal for digital 3.0V Power supply for digital 3.0V Power supply for digital 3.0V Oscillating cell output terminal Oscillating cell input terminal Ground terminal for digital 3.0V Phase comparison output terminal Power on reset capacitor connecting terminal (for timing output) VDO pulse output terminal HDO pulse output terminal TEST terminal (Connect to GND) Ground terminal for analog 12V "R,G,B output DC voltage adjusting terminal" B signal DC voltage feedback circuit capacitor connecting terminal B signal output terminal R signal DC voltage feedback circuit capacitor connecting terminal R signal output terminal G signal DC voltage feedback circuit capacitor connecting terminal G signal output terminal H L Input disposition
Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin name VCC2 TST5 TST6 TST7 VCC3 COM GND3 TST8 POF DWN TST9 TST10 TST11 TST12 TST13 TST14 VSS VSS VDD TST15 OSD B OSD R OSD G BLK HCK1 HCK2 VCC1 HST RGT EN STB VCK FIL IN B/B-Y G/Y R/R-Y I/O O O O I I I O O O O O O O O I I I I Description Power supply for analog 12V TEST terminal (OPEN) TEST terminal (OPEN) TEST terminal (OPEN) Power supply for analog 12V COM Common electrode voltage output terminal for LCD panel Ground terminal for analog 12V COM TEST terminal (OPEN) LCD panel power ON/OFF terminal Right and left invert switching signal output terminal TEST terminal (Connect to GND) TEST terminal (Connect to GND) TEST terminal (OPEN) TEST terminal (OPEN) TEST terminal (OPEN) TEST terminal (OPEN) Ground terminal for digital 3.0V Ground terminal for digital 3.0V Power supply for digital 3.0V TEST terminal (Connect to GND) OSD B input terminal OSD R input terminal OSD G input terminal BLK pulse output terminal H clock pulse1 output terminal H clock pulse2 output terminal Power supply for analog 3.0V H start pulse output terminal Right and left invert switching signal output terminal EN pulse output terminal STB pulse output terminal V clock pulse output terminal H FILTER input terminal (For Internal sync separation) B/B-Y signal input terminal G/Y signal input terminal R/R-Y signal input terminal RGT : RIGHT SCAN and LEFT SCAN Input disposition
*DWN : DOWN SCAN and UP SCAN H : Pull Up L : Pull Down
EPC2LC20-008 [ALTERA] (Configuration Devices (1,695,680 x 1bit Device with 5.0V or 3.3V Operation))
DATA TDO TMS VCC TCK
Block Diagram
VPP N.C. N.C. N.C. VPPSEL
Oscillator CLK ENA nRESET Address Counter DCLK
DCLK VCCSEL N.C. N.C. OE
4 5 6 7 8
3
2
1
20 19 18 17 16 15
ACEX 1K, APEX 20K, FLEX 10K, & FLEX 6000 Device Configuration Using an EPC2, EPC1, or EPC1441 Device
9
nCS
10 11
GND TDI
14 12 13
nINIT_CONF nCASC
Oscillator Control nCS Error Detection Circuitry
Address
Decode Logic nCASC(1)
(Top View)
OE(2)
EPROM Array DATA T Shift Register DATA T
4-42
4-42
EP1K30FC256-3 [ALTERA] (CMOS SRAM)
Pin Description
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y
PLSC1401-V2/HD64F2238RFA13 [JVC/HITACHI] (16-Bit Single Chip Micro Computer)
Pin Name (1) MSEL0 (2) MSEL1 (2) nSTATUS (2) nCONFIG (2) DCLK (2) CONF_DONE (2) INIT_DONE (3) nCE (2) nCEO (2) nWS (2) nRS (2) nCS (2) CS (2) RDYnBUSY (4) CLKUSR (4) DATA7 (4) DATA6 (4) DATA5 (4) DATA4 (4) DATA3 (4) DATA2 (4) DATA1 (4) DATA0 (2), (5) TDI (2) TDO (2) TCK (2) TMS (2) TRST (2) Dedicated Inputs Dedicated Clock Pins GCLK1 (7) LOCK (8) DEV_CLRn (3) DEV_OE (3) VCCINT (2.5 V) 256-Pin FineLine BGA P1 R1 T16 N4 B2 C15 G16 B1 B16 B14 C14 A16 A15 G14 D15 B5 D4 A4 B4 C3 A2 B3 A1 C2 C16 B15 P15 R16 B9, E8, M9, R8 A9, L8 L8 P12 D8 C9 E11, F5, F7, F9, F12, H6, H7, H10, J7, J10, J11, K9, L5, L7, L12, M11, R2 D12, E6, F8, F10, G6, G8, G11, H11, J6, K6, K8, K11, L10, M6, N12 L9 A3, A14, C7, E5, E12, F6, F11, G7, G9, G10, H8, H9, J8, J9, K5, K7, K10, L1, L6, L11, M5, M12 T8 D1, E3, E16, G3, H1, H16, J1, K3, K14, K16, L2, L4, M14, M16, N15 171
(Bottom view)
Block Diagram
I/O Element (IOE) IOE IOE IOE IOE
Embedded Array Block (EAB) IOE IOE IOE IOE IOE IOE
IOE IOE Column Interconnect
IOE IOE Logic Array EAB Logic Array Block (LAB) IOE IOE Logic Element (LE) EAB Local Interconnect
IOE IOE Row Interconnect
Block diagram
PD7 /D15 PD6 /D14 PD5 /D13 PD4 /D12 PD3 /D11 PD2 /D10 PD1/D9 PD0/D8 PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0
Port E
VCCIO (2.5 or 3.3 V) VCC_CKLK (9) GNDINT
CVCC VCC VSS VSS
Logic Array
GND_CKLK (9) No Connect (N. C.)
PE5/D5 PE6/D6 PE7/D7 PD0/D8 PD1/D9 PD2/D10 PD3/D11 PD4/D12 PD5/D13 PD6/D14 PD7/D15 CVCC PC0/A0 VSS PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8/TIOCA3 PB1/A9/TIOCB3 PB2/A10/TIOCC3 PB3/A11/TIOCD3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Port D
P30/TxD0 P31/RxD0 P32/SCK0/SDA1/IRQ4 P33/TxD1/SCL1 P34/RxD1/SDA0 P35/SCK1/SCL0/IRQ5 P36 P77/TxD3 P76/RxD3 P75/TMO3/SCK3 P74/TMO2/MRES P73/TMO1/CS7 P72/TMO0/CS6 P71/TMRI23/TMCI23/CS5 P70/TMRI01/TMCI01/CS4 PG0/IRQ6 PG1/CS3/IRQ7 PG2/CS2 PG3/CS1 PG4/CS0 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
PF0/BREQ/IRQ2 PF1/BACK/BUZZ PF2/WAIT PF3/LWR/ADTRG/IRQ3 PF4/HWR PF5/RD PF6/AS PF7/ MD2 FWE EXTAL VSS XTAL VCC STBY NMI RES OSC1 OSC2 MD1 MD0 AVCC Vref P40/AN0 P41/AN1
TFP-100B TFP-100G FP-100B (Top View)
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P96/DA0 P97/DA1 AVSS P17/TIOCB2/TCLKD P16/TIOCA2/IRQ1 P15/TIOCB1/TCLKC P14/TIOCA1/IRQ0 P13/TIOCD0/TCLKB/A23 P12/TIOCC0/TCLKA/A22 P11/TIOCB0/A21 P10/TIOCA0/A20 PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4
Internal Data Bus
H8S/2000 CPU
Internal Address Bus
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
Total User I/O Pins (10)
Embedded Array
Bus Controller
DTC
Circumference Address Bus
Interrupt Controller
Circumference Data Bus
MD2 MD1 MD0 EXTAL XTAL OSC1 OSC2 STBY RES NMI FWE
Sub-clock System Clock Generator Generator
PA3 / A19/SCK2 PA2 / A18/RxD2 PA1 / A17/TxD2 PA0 / A16 PB7 / A15/TIOCB5 PB6 / A14/TIOCA5 PB5 / A13/TIOCB4 PB4 / A12/TIOCA4 PB3 / A11/TIOCD3 PB2/ A10/TIOCC3 PB1 / A9/TIOCB3 PB0 / A8/TIOCA3 PC7 / A7 PC6 / A6 PC5 / A5 PC4 / A4 PC3 / A3 PC2 / A2 PC1 / A1 PC0 / A0 P36 P35/SCK1/SCL0/IRQ5 P34/RxD1/SDA0 P33/TxD1/SCL1 P32/SCK0/SDA1/IRQ4 P31/RxD0 P30/TxD0
EPC2LC20-009 [ALTERA] (Refer to EPC2LC20-008.)
PLSC1402-V2/HD64F2238RFA13 [JVC/HITACHI] (Refer to PLSC1401-V2.)
PF7/ PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2 /WAIT PF1 /BACK/BUZZ PF0 /BREQ/IRQ2
WDT0
WDT1
(Sub-clock operation)
ROM
8-bit Timer (4 channel)
Port F
SCI (4 channel) I2C Bus Interface [Option] D/A Converter (2 channel)
RAM
PG4 /CS0 PG3 /CS1 PG2 /CS2 PG1 /CS3/IRQ7 PG0 /IRQ6
Port G
TPU (6 channel)
Port 9
A/D Converter (8 channel)
Port 3
Port C
PC Break Controller (2 channel)
Port B
Port A
P97/ DA1 P96/DA0
Port 1
Port 7
Port 4
Vref AVCC AVSS
P10/TIOCA0/A20 P11/TIOCB0/A21 P12/TIOCC0/TCLKA/A22 P13/TIOCD0/TCLKB/A23 P14/TIOCA1/IRQ0 P15/TIOCB1/TCLKC P16/TIOCA2/IRQ1 P17/TIOCB2/TCLKD
4-43
4-43
P70/TMRI01/TMCI01/CS4 P71/TMRI23/TMCI23/CS5 P72/TMO0/CS6 P73/TMO1/CS7 P74/TMO2/MRES P75/TMO3/SCK3 P76/RxD3 P77/TxD3
P47/AN7 P46/AN6 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0
ICS570B-X [ICS] (Multiplier and Zero Delay Buffer)
JCY0132 [SONY] (REC/PLAY amplifier for digital VCR)
Block diagram
Pin description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 Pin name ATF_GND Description Ground terminal level adjustment of AGC circuit Pin No. 36 37 38 Pin name DUMP VDD HID3 Description HEAD resonance control terminal at playback mode VDD power supply terminal Mode control terminal, channel select of playback amplifier and control of recording current measurement circuit 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 HID2 HID1 PB_H REC_H Vcc5 R_CTL DCS_C3 DCS_C2 DCS_C1 PB_MONI PB_OUT PB_IN AGC_CTL AGC_DET PB_GND PREAGC AGC_IN REG11 AGC_OUT VRB_AGC MAIN_GND ATF_GAIN VCA_OUT ATF_IN VRB_ATF ATF_OUT Mode control terminal, channel select of recording/playback amplifier Mode control terminal, channel select of recording/playback amplifier Mode control terminal, ON/OFF of playback circuit Mode control terminal, ON/OFF of recording circuit Vcc5 power supply terminal Mode control terminal, ON/OFF of recording current output Time constant terminal for DC servo circuit Time constant terminal for DC servo circuit Time constant terminal for DC servo circuit PB amplifier monitor terminal PB amplifier output terminal PB MAIN/ATF input terminal AGC control terminal for MAIN family Time constant terminal for MAIN family Ground terminal AGC+LPF output terminal for MAIN family 10.3dB amplifier input terminalfor MAIN family Regulator 1.1V output terminal Output terminal for MAIN family Bottom reference voltage output terminal for A/D converter of MAIN family Ground terminal VCA control terminal for ATF family VCA+BPF output terminal for ATF family 12dB amplifier input terminal for ATF family Bottom reference voltage output terminal for A/D converter of ATF family Output terminal for ATF family
S1 VDD GND ICLK
1 2
(Top View)
8 7 6 5
CLK/2 CLK S0 FBIN
MUSIN_EVR EVR terminal for non-signal detection PB_GND TC ADREF REF_CLK REC_DATA REC_GND REC_CLK REC_GAIN Vcc3 MONI_CHG Ground terminal Time constant terminal for F0 auto PLL circuit ADREF power supply terminal ADREF Reference clock input terminal for F0 auto PLL REC DATA input terminal Ground terminal REC CLOCK input terminal Adjusting terminal for recoding current Vcc3 power supply terminal Monitor terminal for recording current output level : REC mode, Quick charge pulse input terminal of TC terminal : PB mode
3 4
Pin Descriptions
Number 1 Name S1 Type Description I Select 1 for output clock. Connect to GND, VDD, or float per decoding table above. 2 3 4 5 6 VDD GND ICLK FBIN S0 P P CI CI I Connect to +3.3V. Connect to ground. Reference clock input. Feedback clock input. Select 0 for output clock. Connect to GND, VDD, or float per decoding table above. Clock output per table above. Clock output per table above. Low skew divide by two of pin 7 clock.
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
HEAD_Vcc REC_R HEAD_GND HEAD_GND HEAD_GND DY1 Y1 X1 DX1 HEAD_GND DY2 Y2 X2 DX2 HEAD_GND DY3 Y3 X3 DX3 HEAD_GND HEAD_GND HEAD_GND PBIN_R
Power supply terminal of R/P amplifier section External resistor connecting terminal for recording current output level monitor Ground terminal Ground terminal Ground terminal Damping resistor connecting terminal HEAD terminal HEAD terminal Damping resistor connecting terminal Ground terminal Damping resistor connecting terminal HEAD terminal HEAD terminal Damping resistor connecting terminal Ground terminal Damping resistor connecting terminal HEAD terminal HEAD terminal Damping resistor connecting terminal Ground terminal Ground terminal Ground terminal External resistor connecting terminal for playback reference current
7 8
CLK CLK/2
O O
Key: CI = clock input, I = input, O = output, P = power supply connection
Block Diagram
29 30 31 32 33
ICLK S1, S0 2
FBIN
divide by N
Phase Detector, Charge Pump, and Loop Filter
Voltage Controlled Oscillator ÷2
34
Output Buffer
CLK
35
Output Buffer
CLK/2
JCY0136-X [ROHM] (High frequency operational amplifier for DVC)
8
7
6
5
Block diagram VCC IN+ 1 + IN 2 7 CTLIN1 8 VCC
GND 3
6 CTLIN2
OUT 4
5 DTROUT
1
2
3
4
4-44
4-44
JCY0176 [JVC] (Digital A/V signal processor)
PAD No. 187 194 200 206 211 213 215 223 228 233 239 245 251 258 264 267 273 281 287 293 300 306 312 317 319 321 329 334 339 345 351 357 364 370 373 379 387 393 399 406 412 418 423 2 5 14 19 25 30 36 45 51 56 63 72 78 85 PIN No. 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 I/O VDDI I O VSS O (N.C) I/O VCC I I I VDDE I/O I/O I/O I/O I/O I/O VCC VDDI I/O I/O VSS VSS I I O I I/O I/O I/O I/O I/O I I I VSSA VSSA I/O VSSA VDDA VSS I/O (N.C) (N.C) VSS VDDE I I I I (N.C) I I VSSP O O INV YSO2 OUTH MON19 TBST DCTEST0 TMS MON8 MON7 MON12 MON13 MON18 MON21 Name PAD No. 91 98 104 108 111 120 125 131 136 142 151 157 162 169 178 184 191 197 204 210 214 217 226 231 237 242 248 257 263 268 275 284 290 297 303 310 316 320 323 332 337 343 348 354 363 369 374 381 390 396 403 409 416 422 421 15 20 PIN No. 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 I/O VDDE O I VDDE VSS O O O O I I I/O I/O VSSP I I I O O O I/O I/O I VCC I I/O I/O I/O I/O I/O I/O I/O I/O O VDDE I/O (N.C) I I I I/O I/O VDDE I/O I/O I VSS I O VSSA O I/O VDDI I/O I/O VDDI O Name SERVOFRREF FRRES PAD No. 26 31 38 43 49 59 65 71 76 83 89 96 103 121 126 132 137 144 149 155 165 171 177 182 189 195 202 209 227 232 238 243 250 255 261 271 277 283 288 295 301 308 315 333 338 344 349 356 361 367 377 383 389 394 401 407 414 PIN No. 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 I/O I I I I VSSA O O I I I/O O O O (N.C) O VDDE O I VSS I I I I I I O O VDDE I I I I/O I/O VSS I/O I/O VSS I/O I/O I I/O I/O I/O I I/O I/O I/O I/O VSS I I VSS VDDA VDDA I/O O VSSA Name EXDATAI5 EXDATAI1 ADVRL1 ADVRH1 ADAVS0 DAAOUT1 DAVRO1 VCI4185 HSP OSC4185O SPA TRKREF CLK135O AILRCK AODAT0 DILRCK OSC24I VCXO11I VCIAUD YSI1 BRSI1 BRSI2 YSO0 YSO3 TRST DCTEST1 TCK MON1 MON24 MON9 MON16 MON22 MON25 EXTREQ EXDATA1 EXDATA3 EXDATA7 CPUDSLOGIC AD2 AD5 AD8 AD11 ADRS1 ADRS6 PHYVDA PHYVDR PHYXTPB PHYTPBIAS PHYAVS1
M62366GP-X [MITSUBISHI] (8bit 12channel D/A converter)
VSS(VrefL) 1 A03 2 A04 3 A05 4 A06 5 A07 6 A08 7 A09 8 A010 9 VDD(VrefU) 10 20 GND 19 A02 18 A01 17 DI
15
Pin No.
17 14 16
Symbol DI DO CLK LD A01 A02 A03 A04 A05 A06 A07 A08 A09 A010 A011 A012 VCC GND VDD VSS
Function Serial data input terminal to input 12-bit long serial data Terminal to output MSB data of 12-bit shift register Shift clock input terminal.Input signal at DI pin is input to 12-bit shift register at rise of shift clock pulse When H-level signal is input to this terminal,the value stored in 12-bit shift register is loaded in decoder and D-A converter output register
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AB AA Y W V U T R P N M L K J H G F E D C B A
M62366GP
INDEX
SBE DODAT PWMAUDIO AOBCK DIMCK AIDAT0 OSC11O VCXO12O YSI2 BRSI1 BRSI3 YSO1 BRSO0 BRSO3 MON17 MON3 PBI TDI MON0 MON4 MON6 MON11 MON14 MON20 MON23 MON26 EXTACCESS EXTDATA4 XCPUDSTB0 XCPURW CPUWAITLOGI AD1 AD4 AD10 AD14 ADRS3 ADRS9 PHYFIL PHYAVS2 PHYRO PHYXTPA PWR2 PWR1 PBCLKO
16 CLK 15 LD 14 DO 13 A012 12 A011 11 VCC
18 19 2 3 4 5 6 7 8 9 12 13 11 20 10 1
8-bit D-A converter output terminal
-
+
-
+
-
+
-
+
-
+
-
+
-
+
AD7 AD13 ADRS0 ADRS2
PBCLKI EXDATAI2 ADVIN1 ADVIN0 DAVREF0 DAVREF1 RECCTL RECCLK
Buffer
1 VSS (VrefL)
2 A03
3 A04
4 A05
5 A06
6 A07
7 A08
8 A09
9 A010
ADRS5 ADRS7 ADRS10
M95320-WMN6-X [ST MICROELECTRONICS] (64/32 Kbit Serial SPI Bus EEPROM)
M5218AFP-X [MITSUBISHI] (Dual Op.Amp.)
M95xxx S 1 Q 2 W 3 VSS 4 8 7 6 5 VCC HOLD C D
Logic Diagram
VCC
(Top View)
D C
Signal Names
C D Q S W HOLD VCC VSS
4-45 4-45
S W HOLD
Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Hold Supply Voltage Ground
M95xxx
VSS
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
PAD No. 424 8 12 17 23 29 34 41 48 50 53 54 57 60 67 73 79 87 92 99 102 106 114 118 123 129 135 140 147 154 156 159 160 163 166 173 179 185 193
PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
I/O I/O VDDP (N.C) I VSS I (N.C) VSSA VDDA I O VDDA O VDDA VSS VDDE I O VSS O O VSS O I O VSS O VDDI I I/O VSS VDDE VDDI VDDE VSS VDDP VDDE I I
PAD No. BUSRST 198 205 208 EXDATA16 212 220 EXDATA13 224 229 ADAVS1 235 ADAVD0 241 ADVRH0 246 DAAOUT0 253 DAAVD0 260 DAVRO0 262 DAAVD1 265 266 269 OSC4185I 272 REFCLK 279 285 SERVOTRKREP 291 CLK27O 299 304 PWM27O 311 CLK27SEL 314 DOBCK 318 326 AOLRCK 330 335 DIDAT 341 OSC24O 347 352 359 366 368 371 372 375 CLK27I 378 INH 385 Name
PIN No. 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78
I/O VSS O O O I/O I I VSS O VDDI VCC I/O VCC VDDE VDDI I/O I/O VCC VDDE I/O I/O VSS I/O I/O I I O I/O VSS I/O VDDI I/O I I VDDE VDDI I I I
Name BRSO1 BRSO2 OUTV MON5 TTST VPD TDO
MON10
MON15 MON2
MON27 EXTFRP XETDATA5 XETDATA6 XRESET XCPUCS CPUWAIT AD0
PAD No. 391 397 405 410 417 420 1 3 11 16 21 27 33 39 46 52 55 61 69 75 81 88 94 100 105 107 109 117 122 127 133 139 145 152 158 161 167 175 181
PIN No. 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117
(TOP VIEW)
I/O O VDDA VDDA I/O I I VDDE (N.C) VSSP I (N.C) I I VDDA I (N.C) VSSA VSSA VDDP I/O VDDI O O VSS VDDE I/O I O O O O O I I I I I/O I I
Name PHYRF PHYAVD2 PHYAVD3 PHYTPA MTEST PMODE
Power supply terminal GND terminal D-A converter upper reference voltage input terminal D-A converter lower reference voltage input terminal
EXDATA0 EXDATA2
EXDATAI7 EXDATAI4 EXDATAI0 ADAVD1 ADVRL0 DAAVS0 DAAVS1 HID RECDATA FRREF
CPUALE XCPUDSTB1 XINT CPUBUSTYPE AD3 AD6 AD9 AD12 AD15 ADRS4 BUSCLK ADRS8 PHYVSA PHYVSR PHYTPB PHYAVS3 PHYAVD1 PWR3
Block Diagram
GND 20 A02 19 A01 18 DI 17 CLK 16 LD 15 D0 14 A012 13 A011 12 VCC 11
- +
8 bit D/A CONVERTER Ch2 8 bit Latch (12)
- +
D-A 1 L
12bit shift register
D0 1 2 3 4 5 6 D7 D8 9 10 D11
- +
D-A 12 L
- +
D-A 11 L (12)
(8) (12)
Address Decoder
8 bit Latch Ch3 8 bit D/A CONVERTER 4
L 5
L 6
L 7
L 8
L 9
L 10
L
OSC27O OSC27I DISCRI DOLRCK AIBCK AIMCK AODAT1 DIBCK AIDAT1 OSC11I VCXO12I VCXO11O YSI0 YSI3
D-A
D-A
D-A
D-A
D-A
D-A
D-A
-
+
10 VDD (VrefU)
Q
MB3782PF-X [FUJITSU] (Switching Regulator Controller)
MK3754D-X [ICS] (Low Cost 54MHz 3.3 Volt VCXO)
X1 VDD VIN GND 1 2 3 4
(Top View)
MM1571JN-X [MITSUMI] (1.8V Regulator)
8 7 6 5 X2 GND CLK VDD
5 1 2
4 3
1 2 3 4 5
VIN GND Cont Noise VO
Block Diagram
Pin Number 1 2 3 4 5 6 7 8 Pin Name XI VDD VIN GND VDD CLK GND X2 Pin Type Input Power Input Power Power Output Power Input Pin Description Crystal connection. Connect to the external pullable crystal. Connect to +3.3 V (0.01uf decoupling capacitor recommended). Voltage input to VCXO -- 0 to 3.3 V analog input which controls the oscillation frequency of the VCXO. Connect to ground. Connect to +3.3 V (0.01uf decoupling capacitor recommended). 54 MHz clock output. Connect to ground. Crystal connection. Connect to the external pullable crystal.
SOT-25A (TOP VIEW)
Block Diagram
VIN Cin 1µF VO Co 1µF
Bias
Cont
Reference
Driver
Current limitter
Pin Descriptions
VDD
Thermal shutdown GND Noise Cn 0.1µF
54 MHz
VIN 13.5 MHz Pullable Crystal X1
Voltage Controlled Crystal Oscillator PLL/Clock Synthesis Circuitry
X2
MM1572FN-X [MITSUMI] (Refer to MM1571JN-X.)
GND
MM1572KN-X [MITSUMI] (Refer to MM1571JN-X.) MN13821/F/-X [MATSUSHITA] (Voltage Detector)
MK9173-01CS08-X [ICS] (Video Genlock PLL)
Pin descriptions
VDD
2
1
3
Block diagram
OUT
VSS
Block Diagram
2 Voltage Reference 1 Level Converter VDD
+
Comparator
Output Circuit 1 OUT
+
Voltage Reference 2 Comparator
3 VSS
4-46
4-46
MN102F1617HL-Z0 [MATSUSHITA] (16bit Micro controller)
MN1030F04KYBSC [MATSUSHITA] (32bit Micro computer)
T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
MN7D056B3W [MATSUSHITA] (Lens drive LSI, CMOS Standard Cell)
(Bottom view)
PE7 NMIRQ PE5 AVDD AN2 AN3 AN7 AN15 P12 AN0 AN5 AN9 AN13 P13 P17 CS0 SYSCLK VSS RST PFO VREFH AN1 AN10 AN14 P14 VSS CS1 VDDH FRQS MMOD0 WE1 RE WE0 16 15 14 VSS PE6 AN4 AN6 AVSS VDDH P15 VDD CS3 PE1 PE3 PE4 PE2 PE0 AN11 P10 P11 P16 PJ4 PJ3 PJ2 PJ1 A9 A8 A6 A5 A7 11 A13 A11 A12 VSS A14 A10 10 A16 A23 A15 VDDB A17 9 A18 A19 VSS A22 A20 8 A21 A24 D0 D3 A25 D1 7 P31 P24 D2 D5 VDDH D6 D4 6 PD0 VDD PC6 PD1 PC7 AN8 AN12 PC4 PC2 PC5 PC3 PC0 PB4 PC1 PB7 VSS PB6 PB2 PB1 PB3 PB5 VDDH PA3 PA2 PA0 PB0 PA1 P95 P93 P94 P92 VSS P90 P86 P67 P60 P91 P85 VDD P83 P81 P63 P64 P41 P35 P33 P21 D9 D7 D11 D8 D10 5 P84 P82 P87 P74 P70 P65 P62 VDDH P34 P30 P22 P13 P10 D12 D13 VSS 4 D15 3 2 1 P77 P75 P72 VSS P55 P51 P40 P32 P15 P20 VDDH D14 P73 VDD P66 P61 P52 VPP VDD P23 P14 P11 P76 VSS P71 P64 P53 P50 VSS P25 VSS P12 P00 P80 T R P N M L K J H G F E D C B A
Block diagram
PJ0 CS2
MODE2-0
Mode controller
Port 0
R07-00 D(15:0) AD(15:0)
OSCO OSCI MMOD0 PVDD
/RST
EXMOD1 EXMOD0 PVSS PL3 A0 VDDB 13 A4 A2 A1 A3 12
Oscillator
MNI02H00
Address bus Data bus
OSCI OSCO
ATC
RD7-D0 RTP7-0 PC7-C0 TMnI(A,R) TMnO NMI NBREQ NBRACK PB5-B0 SBI3,2 SBO3,2 SBT3,2 SDA3 SCK3 PA5-A0 SBI1,0 SBO1,0 SBT1,0 SDA3 SCK3 P97-90 TM4ITM2I TM11O,13O,15O TMI9IB TM20IB
Port C
Port D
Port 1
P17-10
NJM12902V-X [JRC] (Single Supply Quad Amplifier)
Port 2
P27-20 A(23:0) /KI7-0
Port B
Serial
MN3112SA-X [MATSUSHITA] (Vertical Driver)
Circumference data bus
Circumference data bus
BUS Controller
Port A
24 bit Timer
Port 3
P37-30
Port 9
8 bit Timer
Port 4
P47-40
A/D Converter
Port 8
AN15-0 VrefH VrefL WDOUT STOP P75-70 TM16IOA TM16IOB TM17IOA TM17IOB TM18IOA TM18IOB TM19IOA TM20IOB
Port 5
P87-80
P57-50 /WEL /WEH /RE ALE BOSC BIBT1 BIBT2 /DUMX /UCAS /LCAS /RAS P67-60 IRQ7-0 TMnI TMnIA TMnIB /EXTDK
Interrupt Controller
Port 7
16 bit Timer
Port 6
4-47
4-47
MT48LC2M32B2-X [MICRON] (64Mb (2Meg x 32) SDRAM)
NJM2538V-X [JRC] (Video Amp.)
(Top View)
NJM12904V-X [JRC] (Single Supply Dual Amplifier)
NJM2068M-D-XE [JRC] (Dual Low-Noise Op.Amp) NJM2870F05-X [JRC] (Regulator) NJM2870F33-X [JRC] (Refer to NJM2870F05-X.)
1 2 3
(Top View)
V IN Cont
5 4
1.CONTROL(Active High) 2.GND 3.NOISE BYPASS 4.VOUT 5.VIN
V OUT
Thermal Protection Noi se By pass
Bandgap Reference
GND
4-48
4-48
NJM3221VE1-W [JRC] (Optical Image stabilizer (OIS) for DVC)
RS5C314-X [RICHO] (CMOS Realtime Clock)
Block diagram
CE SCLK SIO VSS 1 2 3 4 (Top view) 8 7 6 5 VDD OSCIN OSCOUT INTR
SN74AHC1G14K-X [TEXAS INSTRUMENTS] (Single Schmitt-trigger Inverter Gate)
NC A GND
1 2 3
5 4
VCC Y
(TOP VIEW)
NC-No internal connection
logic diagram (positive logic)
NJM3403AV-X [JRC] (Single Supply Quad Amplifier)
1 2 3 4 5
B
+ +
2 A
4
Y
+
A
+
D
14 13 12 11 10 1. A OUTPUT 2. AINPUT 3. A+INPUT 4. V+ 5. B+INPUT 6. BINPUT 7. B OUTPUT 8. C OUTPUT 9. CINPUT 10. C+INPUT 11. V 12. D+INPUT 13. DINPUT 14. D OUTPUT
SN74AHC1G00K-X [TEXAS INSTRUMENTS] (Single 2-Input Positive NAND Gate)
FUNCTION TABLE
SN74AHC1G125K-X [TEXAS INSTRUMENTS] (Single Bus Buffer Gate with 3-State Outputs)
FUNCTION TABLE INPUT A H L OUTPUT Y L H
6 7
C
9 8
A B GND
1 2 3
5 4
VCC Y
FUNCTION TABLE
INPUTS A H L X B H X L
OUTPUT Y L H H
OE A GND
1 2 3
5 4
VCC Y
INPUTS OE L L H A H L X
OUTPUT Y H L Z
(Top view)
(TOP VIEW)
(TOP VIEW)
NJU7222U30-X [JRC] (3-Terminal Positive Voltage Regulator)
Logic diagram (positive logic)
Logic diagram (positive logic)
A
1. GND 2. INPUT 3. OUTPUT 1 2 3
1 2
SN74AHC2G14U-X [TEXAS INSTRUMENTS] (Triple Schmitt-trigger Inverter Gate)
FUNCTION TABLE (each inverter) INPUT A H L OUTPUT Y L H
4
Y
B
OE A
1 2 4
1A 3Y 2A GND
1 2 3 4 8 7 6 5
Y
VCC 1Y 3A 2Y
SN74AHC1G04K-X [TEXAS INSTRUMENTS] (Single Inverter Gate)
(TOP VIEW)
Logic symbol
FUNCTION TABLE
SIP1250LC [NuCORE TECHNOLOGY] (Smart image processor for DVC)
W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 11 13 15 17 19 10 12 14 16 18
NC A GND
1 2 3
5 4
VCC Y
INPUT A H L
OUTPUT Y L H
SN74AHC1G32K-X [TEXAS INSTRUMENTS] (Single 2-Input Positive OR Gate)
FUNCTION TABLE
INPUTS
1A 2A 3A
1 3 6
7 5 2
1Y 2Y 3Y
(TOP VIEW)
NuCORE
TECHNOLOGY
SiP1250LC
Logic diagram (positive logic)
A B GND
1 2 3
5 4
VCC Y
A H X L
B X H L
OUTPUT Y H H L
Block diagram
A Y
A
2
4
(TOP VIEW)
Y
Logic diagram (positive logic)
A B
1 2
4
Y
4-49
4-49
SN74AHC245DGV-X [TEXAS INSTRUMENTS] (Octal Bus Transceivers with 3-State Outputs)
DIR A1 A2 A3 A4 A5 A6 A7 A8 GND
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
SN74AHC2G241U-X [TEXAS INSTRUMENTS] (Dual Buffer/Driver 3-State Outputs)
1OE 1A 2Y GND
1 2 3 4 8 7 6 5
SN74AHC2G66U-X [TEXAS INSTRUMENTS] (Dual Bidirectional Analog Switch)
FUNCTION TABLE
SN74AHCT04DGV-X [TEXAS INSTRUMENTS] (Hex Inverters)
VCC OE B1 B2 B3 B4 B5 B6 B7 B8
FUNCTION TABLE
(each transceiver) INPUTS OE L L H DIR L H X OPERATION B data to A bus A data to B bus Isolation
INPUTS 1OE L L H 1A H L X
VCC 2OE 1Y 2A
1A 1B 2C GND
1 2 3 4
8 7 6 5
VCC 1C 2B 2A
INPUTS CONTROL SWITCH (C) L H OFF ON
(TOP VIEW) FUNCTION TABLES OUTPUT 1Y H L Z INPUTS 2OE H H L 2A H L X OUTPUT 2Y H L Z
(TOP VIEW)
Logic symbol
1C 1A 2C 2A 7 1 3 5 6 2B X1 1 1 2 1B
1A 1Y 2A 2Y 3A 3Y GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 6A 6Y 5A 5Y 4A 4Y
FUNCTION TABLE (each inverter) INPUT A H L OUTPUT Y L H
(TOP VIEW)
(TOP VIEW)
Logic symbol
1A 2A 1 3 5 9 11 13 1 2 4 6 8 10 12 1Y 2Y 3Y 4Y 5Y 6Y
Logic symbol
OE DIR 19 1 G3 3 EN1 [BA] 3 EN2 [AB] 1 2 18 17 16 15 14 13 12 11 B1 B2 B3 B4 B5 B6 B7 B8
Logic symbol
1OE 1 EN
Block diagram
3A 4A 5A 6A
A1 A2 A3 A4 A5 A6 A7 A8
2 3 4 5 6 7 8 9
A
B
1A
2
6
Logic diagram, each inverter (positive logic)
1Y
A
2OE 7 EN
C
Y
2A
5
3
2Y
SN74AHC2G74U-X [TEXAS INSTRUMENTS] (D-Type Flip-Flop with Preset and Clear)
FUNCTION TABLES INPUTS PRE L H L CLR H L L H H H CLK X X X D X X X H L X OUTPUTS Q H L H H L Q0 Q L H H L H Q0
Block diagram
SN74LV126ADGV-X [TEXAS INSTRUMENTS] (Quad 2-Input Bus Buffers)
Logic diagram (positive logic)
1OE
1 2 6
DIR
1
1A 1Y
CLK D Q GND
1 2 3 4
8 7 6 5
VCC PRE CLR Q
19
OE
2OE 2A 7 5 3
(TOP VIEW)
H H H
A1
2
2Y
18
B1
This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level.
Logic symbol
To Seven Other Channels
SN74LV04ADGV-X [TEXAS INSTRUMENTS] (Hex Inverters)
PRE CLK D CLR
7 1 2 6
S C D R
5
Q
3
Q
SN74AHCT1G08K-X [TEXAS INSTRUMENTS] (AND Gate)
(TOP VIEW)
Block diagram
PRE CLK C C TG C C C C Q C
FUNCTION TABLE
INPUTS
A B GND
1 2 3
5 4
VCC Y
A H L X
B H X L
OUTPUT Y H L L
Logic diagram (positive logic)
D
TG
TG
TG
A B
1 2
4
Q
Y
4-50
C CLR
C
C
4-50
SN74LV138ADGV-X [TEXAS INSTRUMENTS] (1 OF 8 Decoders/Demultiplexers)
TB6543FL [TOSHIBA] (Optical Lens Motor driver for Video Camera)
ACMP EZB EZA EAF ZBRS ZBZB+ VB ZARS ZAZA+ ARS FMFM+ IOPEN ICLOSE
Pin description
Pin No.
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 H5H5+ MGND IRMIRM+ VIR IRB H4O H4H4+ H3O H3+ H2O H2H2+ H1O
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 BCMP LCMP LCI MIXO FCA FCB F2C VCC MA MB REFI AIN BIN DGND DI CK 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Pin name LD HG HB PWMB ZAIN ZBIN ZAO ZBO GND REFO ZD ZB ZC ZA H1+ H1H1O H2+ H2H2O H3+ H3O H4+ H4H4O IRB VIR IRM+ IRMMGND H5+ H5-
Description DAC strobe signal input Hall gain adjusting output Hall bias adjusting output PWM bias adjusting output Zoom A-phase FG signal input Zoom B-phase FG signal input Zoom A-phase FG signal output monitor Zoom B-phase FG signal output monitor Ground terminal VREF amplifier output Zoom FG signal adder output D Zoom FG signal adder output B Zoom FG signal adder output C Zoom FG signal adder output A H1 amplifier non-inverting input H1 amplifier inverting input H1 amplifier output H2 amplifier non-inverting input H2 amplifier inverting input H2 amplifier output H3 amplifier non-inverting input H3 amplifier output H4 amplifier non-inverting input H4 amplifier inverting input H4 amplifier output Iris upper side pre-drive Iris, AF power supply terminal Iris output + Iris output Motor ground terminal H5 amplifier non-inverting input H5 amplifier inverting input
Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Pin name
Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
ICLOSE Iris control input (CLOSE) IOPEN FM+ FMARS ZA+ ZAZARS VB ZB+ ZBZBRS EAF EZA EZB ACMP BCMP LCMP LCI MIXO FCA FCB F2C VCC MA MB REFI AIN BIN DGND DI CK Iris control input (OPEN) AF output + AF output AF power supply detecting terminal Zoom output (A+) Zoom output (A-) Zoom A-phase current detecting terminal Battery power supply terminal Zoom output (B+) Zoom output (B-) Zoom B-phase current detecting terminal AF output-amplifier input Zoom A-phase output-amplifier input Zoom B-phase output-amplifier input A comparator output B comparator output L comparator output L comparator input Modulation MIX output Modulation MIX input (0bit:1) Modulation MIX input (1bit:2) Modulation MIX input (2bit:4) Power supply terminal AF FG A-phase signal monitor AF FG B-phase signal monitor VREF amplifier input AF A-phase signal input AF B-phase signal input Digital ground terminal DAC serial data signal input DAC reference clock signal input
Block diagram
LD HG HB PWMB ZAIN ZBIN ZAO ZBO GND REFO ZD ZB ZC ZA H1+ H1-
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SN74LV165ADGV-X [TEXAS INSTRUMENTS] (Parallel-Load 8-bit Shift Registers)
TC7W04FU-X [TOSHIBA] (Triple Inverter Gate)
TC7WH245FU-X [TOSHIBA] (Dual Bus Transceiver)
(Top view)
4-51
4-51
TB6546F [TOSHIBA] (OIS (Optical Image stabilizer) Lens Driver for Video Camera)
TLC2940IPW-X [TEXAS INSTRUMENTS] (75MHz CMOS VCO)
(TOP VIEW) LOGIC VDD VCO OUT fREF INPUT PFD OUT 1 2 3 4 8 7 6 5 VCO VDD RBIAS VCOIN GND
RBIAS
BIAS CONTROL VCO OUTPUT
L COUNTER
VCO OUT
VCOIN
Block diagram
UPD6467GR-519-X [NEC] (ON-SCREEN CHARACTER DISPLAY)
CLK CS DATA
Decoder
BLOCK DIAGRAM
CMDCT 6 DATA 3 CLK 1 Data input shift register 9 TEST 5 VDD
1 2 3 4 5 6
20 Hsync 19 Vsync 18 VB 17 VG
...
Instruction decoder
Control signals
10 GND 4 PCL
CS 2
µP D 6 4 6 7 G R - X X X
PCL VDD CMDCT
15 VBLK (BBLK) 14 VC2 (GBLK) 13 BLK2 (RBLK) 12 VC1 11 BLK1
OSCIN OSCOUT 8 7
Oscillation circuit
Data selector
16 VR
Display control register
Character size register
Horizontal address register
Write address counter
Video RAM
OSCOUT 7 OSCIN TEST GND 8 9 10
Horizontal size counter
Horizontal position counter
Horizontal address counter
Blink Reverse Character Color Output data data data data specification data 1 bit 9 bits 3 bits 1 bit 1 bit x x x x x 336 words 336 words 336 words 336 words 336 words
Background control data register
Vertical address register
Pin description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin name YV(+) YV(-) YH(+) YINV YHO YPOS YIN YO YFI YFO YFI2 YFO2 NDPB NDB NDG REFI VB YCS VM XCS Description Y hall positive bias output Y hall negative bias output Y hall amplifier + input Y hall amplifier - input Y hall amplifier output Monitor terminal for Y position detecting signal Y control amplifier input Y control amplifier phase compensating terminal Y LPF input Y LPF output Y LPF secondary input Y LPF secondary output PWM bias adjusting signal output Hall bias adjusting signal output Hall gain adjusting signal output Reference power supply input terminal Battery power supply (+7.2V) Y output current detecting terminal Motor power supply (+3V) X output current detecting terminal 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 XHO XINV XH(+) XV(-) XV(+) XH(-) XHR VCC GND DI CK LD XER YER YHR YH(-) 30 31 XIN XPOS Pin No. 25 26 27 28 29 Pin name XFO2 XFI2 XFO XFI XO Description X LPF secondary output X LPF secondary input X LPF output X LPF input X control amplifier phase compensating terminal X control amplifier input Monitor terminal for X position detecting signal X hall amplifier output X hall amplifier - input X hall amplifier + input X hall negative bias output X hall positive bias output X hall positive bias reference X hall negative bias reference Power supply (+3V) Ground terminal DAC data signal input DAC clock signal input DAC strobe signal input X control signal output Y control signal output Y hall negative bias reference Y hall positive bias reference
(Top View)
Hsync 20 Synchronization protection circuit Vertical size counter
Vertical position counter Vertical address counter
Character generator ROM 12 x 18 bits x 512 words
Vsync 19
Output controller
16 17 18 15 VR VG VB VBLK (BBLK)
Remark
Signals in ( ) are set by using an initial status setting command (RGB + RGB compatible blanking).
14 13 12 11 VC1 BLK1 VC2 BLK2 (GBLK) (RBLK)
YDR(-) Y motor drive - terminal YDR(+) Y motor drive + terminal XDR(-) X motor drive - terminal XDR(+) X motor drive + terminal
D.GND Digital ground terminal
4-52
4-52