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NTDPJTV05
TECHNICAL TRAINING MANUAL N5SS CHASSIS
PROJECTION TELEVISION
TW40F80
Only the different points from the training manual "N5SS chassis" with its file No. 026-9506 are described on this manual. For other parts common with "N5SS chassis", please refer to the original manual with its file No. 026-9506.
©1997 TOSHIBA AMERICA CONSUMER PRODUCTS, INC. NATIONAL SERVICE DIVISION TRAINING DEPARTMENT 1420-B TOSHIBA DRIVE LEBANON, TENNESSEE 37087 PHONE: (615)449-2360 FAX: (615)444-7520 www.toshiba.com/tacp
Contents Page 1
Contents
SECTION I: OUTLINE ................................................................................................ 6 1. FEATURE.................................................................................................................... 6 2. MERITS OF BUS SYSTEM ...................................................................................... 6 3. SPECIFICATIONS..................................................................................................... 7 4. FRONT VIEW ........................................................................................................... 8 5. REAR VIEW ............................................................................................................... 9 6. REMOTE CONTROL VIEW.................................................................................. 10 7. CHASSIS LAYOUT.................................................................................................. 11 8. CONSTRUCTION OF CHASSIS ........................................................................... 12 SECTION II: TUNER, IF/MTS/S. PRO MODULE ................................................ 13 1. CIRCUIT BLOCK ................................................................................................... 13 2. POP TUNER ............................................................................................................. 17 SECTION III: CHANNEL SELECTION CIRCUIT ............................................... 18 1. OUTLINE OF CHANNEL SELECTION CIRCUIT SYSTEM .......................... 18 2. OPERATION OF CHANNEL SELECTION CIRCUIT ...................................... 18 3. MICROCOMPUTER ............................................................................................... 19 4. MICROCOMPUTER TERMINAL FUNCTION .................................................. 20 5. EEPROM (QA02) ..................................................................................................... 22 6. ON SCREEN FUNCTION ....................................................................................... 22 7. SYSTEM BLOCK DIAGRAM................................................................................ 23 8. LOCAL KEY DETECTION METHOD ................................................................ 24 9. REMOTE CONTROL CODE ASSIGNMENT ..................................................... 25 10. ENTERING TO SERVICE MODE ...................................................................... 28 11. TEST SIGNAL SELECTION ............................................................................... 28 12. SERVICE ADJUSTMENT .................................................................................... 28 13. FAILURE DIAGNOSIS PROCEDURE ............................................................... 29 14. TROUBLESHOOTING CHART .......................................................................... 32 SECTION IV: DVD SWITCH CIRCUIT ................................................................. 35 1. DVD SWITCH BLOCK DIAGRAM ...................................................................... 35 2. OUTLINE .................................................................................................................. 36
Contents Page 2
SECTION V: WAC CIRCUIT .................................................................................... 37 1. OUTLINE .................................................................................................................. 37 2. CIRCUIT OPERATION .......................................................................................... 37 3. BLOCK DIAGRAM ................................................................................................. 42 4. WIDE ASPECT CONVERSION CIRCUIT FAILURE ANALYSIS PROCEDURES ......................................................................................................... 43 SECTION VI: DUAL CIRCUIT ................................................................................ 45 1. OUTLINE .................................................................................................................. 45 2. PRINCIPLES OF OPERATION ............................................................................. 45 3. SYSTEM COMPONENT DIAGRAM OF DUAL UNIT ...................................... 46 4. CIRCUIT OPERATION .......................................................................................... 47 5. TERMINAL FUNCTION, DESCRIPTION AND BLOCK DIAGRAM OF MAIN IC.................................................................................................................... 51 SECTION VII: 3-DIMENSION Y/C SEPARATOR CIRCUIT .............................. 58 1. OUTLINE .................................................................................................................. 58 2. CIRCUIT DESCRIPTION ...................................................................................... 58 SECTION VIII: VERTICAL OUTPUT CIRCUIT.................................................. 60 1. OUTLINE .................................................................................................................. 60 2. V OUTPUT CIRCUIT.............................................................................................. 61 3. PROTECTION CIRCUIT FOR V DEFLECTION STOP ................................... 64 4. RASTER POSITION SWITCHING CIRCUIT .................................................... 66 SECTION IX: HORIZONTAL DEFLECTION CIRCUIT .................................... 67 1. OUTLINE .................................................................................................................. 67 2. HORIZONTAL DRIVE CIRCUIT ......................................................................... 67 3. BASIC OPERATION OF HORIZONTAL DRIVE............................................... 67 4. HORIZONTAL OUTPUT CIRCUIT ..................................................................... 69 5. HIGH VOLTAGE GENERATION CIRCUIT ....................................................... 76 6. HIGH VOLTAGE CIRCUIT ................................................................................... 78 7. X-RAY PROTECTION CIRCUIT .......................................................................... 80 8. OVER CURRENT PROTECTION CIRCUIT ...................................................... 81
Contents Page 3
SECTION X: DEFLECTION DISTORTION CORRECTION CIRCUIT (SIDE DPC CIRCUIT) ............................................................................................... 82 1. DEFLECTION DISTORTION CORRECTION IC (TA8859CP) ....................... 82 2. DIODE MODULATOR CIRCUIT ......................................................................... 83 3. ACTUAL CIRCUIT .................................................................................................. 84 SECTION XI: DIGITAL CONVERGENCE CIRCUIT ......................................... 87 1. OUTLINE .................................................................................................................. 87 2. CIRCUIT DESCRIPTION ...................................................................................... 87 3. PICTURE ADJUSTMENT ...................................................................................... 89 4. CASE STUDY ........................................................................................................... 97 5. TROUBLESHOOTING ........................................................................................... 98 6. CONVERGENCE OUTPUT CIRCUIT ................................................................. 99 7. CONVERGENCE TROUBLESHOOTING CHART ......................................... 101 OVERALL BLOCK DIAGRAM................................................................................102
SECTION I: OUTLINE
1. FEATURE
The TW40F80 is a first PJ-TV with a wide screen aspect ratio of 16:9 we introduce to North U.S.A. markets. As the basic chassis N5SS chassis is used. The future of the model TW40F80 is the use of the N5SS chassis. This chassis introduces a new bus system, developed by the PHILIPS company, called the I2C (or IIC) bus. IIC stands for Inter-Integrated Circuit control. This bus coordinates the transfer of data and control between ICs inside the TV. It is a bi-directional serial bus consisting of two lines, named SDA (Serial DATA), and SCL (Serial CLOCK). This bus control system is made possible through the use of digital-to analog converters built into the ICs, allowing them to be addressed and controlled by strings of digital instructions. The TW40F80 is a first wide TV with a double window system we introduce to North U.S.A. markets. The size of the main and sub screens separated in left and right on the screen is the same as each other. So it is possible to enjoy two programs or video and TV program at the same time. The sub screen is equipped wit 9 screen search function and this is very convenient convenient to search a program you desire.
2. MERITS OF BUS SYSTEM
2-1. Improved Serviceability
Most of the adjustments previously made by resetting variable resistors and/or capacitors can be made on the new chassis by operating the remote control and seeing the results on the TV screen. This allows seeing adjustments to be made without removing servicing speed and efficiency.
2-2. Reduction of Parts Count
The use of digital-to-analog converters built into the ICs, allowing them to be controlled by software, has eliminated or reduced the requirement for many discrete parts such as potentiometers and trimmers, etc.
2-3. Quality Control
This central control of the adjustment data makes it easier to understand, analyze, and review the data, thus improving quality of the product.
Note:
Only the different points from the manual "N5SS Chassis" with its file No. 026-9506 are described on this manual. For other parts common with "N5SS Chassis", please refer to the original manual with its File No. 0269506.
5
***
3. SPECIFICATIONS
Model
CRT CRT Source GENERAL 7" Hitach 7" Hitach 7" Hitach 7" Hitach
C-Chassis
7" Hitach 7" Hitach 7" Hitach 7" Hitach 7" Hitach 7" Hitach 7" Hitach
TW56F80 TW40F80 TP61F90 TP61F80 TP55F80 TP55F81 TP50F90 TP50F60 TP50F61 TP50F50 TP50F51
Remote H/U RMT Keys PIP
Intell 52 key 2-TN
Univ 36 key 2-TN
Intell 52 key 2-TN
Univ 36 key 2-TN
Univ 36 key 2-TN
Univ 36 key 2-TN
Intell 52 key 2-TN
Univ 36 key 2-TN
Univ. 36 key 2-TN
A-Univ 42 key 1-TN
A-Univ 42 key 1-TN
Dolby Surr Surround SAP SOUND Cyclone SBS Audio (W)
ProLgc Dsp4Ch q q q
ProLgc Dsp4Ch q
Dy-Sur Dsp4Ch q
Dy-Sur Dsp4Ch q
Dy-Sur Dsp4Ch q
ProLgc Dsp4Ch q q q q q q q q q
q 28W
q 28W
q 28W
q 28W
q 28W
q 28W
q 28W
q 28W
q 28W
q 28W
q 28W
Center Rear Comb-Filter
+20W +20W 3D-Y/C 3D-Y/C
20W 20W 3D-Y/C 20W 3D-Y/C 20W DIG 20W DIG
20W 20W DIG DIG DIG DIG DIG
DQF Scan-Modul VCC PICTURE Black-Expan Color-D.E Pic-Prefer Color-Temp Flesh-Tone Nois-Reduce Hori-Resolu q q q q q q q q 800 q q q q q q q q 800
q q
q q
q q
q q q q q q q
q q q q q q 800
q q q q q q 800
q q q q q q 800
q q q q q q 800
q q q q q q 800
q q q q q q 800
q q q q q q 800
q q q q q q 800
q q q q q q 800
Fav-Channel Ch-Label 3-Language OTHERS Clock Ch-Lock/Off C.Caption EDS New-OSD S/Sight S-Video In AV-In/Out Front-Term TERMINAL A(Var)-Out 2RF-Term SPK-Term PIP Audio C-Ch-Input E/Jack S/S-Jack IR-B & 75W ACCE Adapter Rod-Antenna SPK-Box EZ RMT
q q q q q q
q q q q q q q
q q q q q q
q q q q q q q
q q q q q q q q
q q q q q q q q
q q q q q q
q q q q q q q
q q q q q q q q
q q q q q q q
q q q q q q q
q q 1+1 1+2/1 q q q q
q
q q
q
q q
q
1+1 1+2/1 q q q q
1+1 1+2/1 q q q q q
1+1 1+2/1 q q q q
1+1 1+2/1 q q q q
1+1 1+2/1 q q q q
1+1 1+2/1 q q q q q
1+1 1+2/1 q q q q
1+1 1+2/1 q q q q
1 2/1
1 2/1
q
q
q
q
q
q
q
q q q q
q q q q q q
q q q q q q q
q q TW56D90 40W30E
q q
q
q q New New New New New
*
Cabinet
TP61E90 TP61E80 TP55E80 TP55E81
6
4. FRONT VIEW
POWER indicator
POWER
POWER button Press to open the door.
ANT / VIDEO button ** ENTER button Behind the door
S-VIDEO
VIDEO
AUDIO L/MCNO R DEMO
ANT/ VIDEO
VOLUME
CHANNEL
IN-VIDEO 3
MENU
ENTER
MENU button
CHANNEL / / buttons
buttons
VIDEO 3 INPUTS
DEMO button VOLUME / / buttons buttons
Fig. 1-1 Note: [No] Owner's manual page.
7
5. REAR VIEW
TV front
Behind the door
S-VIDEO VIDEO AUDIO L/MCNO R
IN-VIDEO 3
VIDEO / AUDIO INPUT jacks (VIDEO 3)
S-VIDEO INPUT jack (VIDEO 3)
Fig. 1-2
TV rear
S-VIDEO INPUT jack (VIDEO 1)
VARIABLE AUDIO OUTPUT jacks
ANT (75 ½) S-VIDEO R AMP L VAR ACC
VIDEO TV (+) (+) L VIDEO (Ð) EXT SPEAKER EXT INT VIDEO1 VIDEO2 N (Ð) AMP AUDIO R
Y C4 L VIDEO/AUDIO R
AMP
VIDEO
AUDIO R
MAIN SPEAKER
DVD CUT
EXTERNAL SPEAKER terminal MAIN SPEAKER switch
VIDEO / AUDIO INPUT jacks (VIDEO 1)
VIDEO / AUDIO INPUT jacks (VIDEO 2) DVD INPUT jacks
VIDEO / AUDIO OUTPUT jacks
Fig. 1-3
8
6. REMOTE CONTROL VIEW
Aim at the remote sensor on the TV
RECALL* [ 26 ] TIMER* [ 38, 39 ] TV / CABLE / VCR switch [ 15 ] Set to " TV " to control the TV. TV / VIDEO* [ 55 ]
TV CABLE VCR
PIC -SIZE RECALL
POWER
TV/VIDEO
MUTE
POWER [ 20 ] MUTE* [ 26 ]
1 4
Channel Number* [ 25 ]
2 5 8 0
3
CH
CHANNEL
/
[ 25 ]
6
CH RTN* [ 26 ]
7 100
EDS* [ 27 ] ENTER [ 19 ] FAN POP CH * [ 46 ] * [ 40 ]
FAV EDS
9
CH RTN VOL
VOLUME
/
[ 25 ]
ENT
¥
MENU
ADV/ POP CH
MENU [ 18 ] POP CH * [ 40 ] / [ 18 ]
ENTER
FAV
/ FAN
/
RESET
EXIT
* [ 46 ]
RESET * [ 33 ]
ADV/ POP CH
STOP SCURCE PLAY POP
EXIT * [ ON ] Owner's Manual page
REC
TV/VCR
REW
FF
POP functions* [40] (For " TV " and " CABLE " positions)
CH SEARCH
STILL
SWAP
TOSHIBA
* These function do not have duplicate locations on the TV. They can be controlled only by the Remote Control.
Fig. 1-4 Note: [No] Owner's Manual page.
9
TUNER DOLBY DSP F.SUR COHB FDS N.OSD STARSIGHT MODE1 2 TW40F80 3DYC TW56F80 PRO 4CH 3DYC 2
PC BOARD (chip)
330 249 4 : AV.EXT SPK
: DIGITAL CONVER
249 242 10 14
:AUDIO LIVE
330
1 : MAIN
7
: NEW OSD/ FRONT SURROUND
160
2pcs
CHIP DOUBLE FACED
139
5 - 4 : FRONT-LED
1pcs
4
-1: A.V -2: SPEAKER
2pcs
6pcs
CHIP SINGLE FACED
294
165
165
1pc
7
-1: NEW OSD -2: FRONT SURROUND
4
7
TW56F80 ONLY
242 11
:DUAL
242 15
:SIARSIGHT
7. CHASSIS LAYOUT
330 2pcs
CHIP DOUBLE FACED
330
249
1pcs
139
5 - 5 : FRONT-CON 2 : DEFELECTION
5
:
CRT-1pcs D/FRONT/SHV 8
: SW DVD
5
-5: FRONT CON -6: SVH
126
294
249
1pc
5
-1: CRTÐD(R) -2: CRTÐD(G) -3: CRTÐD(B)
165
4pcs 242 12
:3D Y/C
CHIP DOUBLE FACED
242 16
:DOLBY PRO
5 5
5
155
5
-4: FRONT LED
2pcs
CHIP DOUBLE FACED
249 6 : POWER 1
: POWER S.S
249 9 2pcs
113
330 3 : CONV / POWER2
2pcs
CHIP DOUBLE FACED TW56F80 ONLY
5 - 6 : SVM 1pc
TW56F80 ONLY
FOCUS PACK 1pc
189 13
:MAC
294
165
249
139
4pcs
CHIP DOUBLE FACED
10
5 3 : CONVERTER/POWER 2 REAR ANP (TW56F80 ONLY) CENTER AMP (TW56F80 ONLY) -3 : CRT-D(B) To FOCUS PACK To CRT F.B.T J-BOX 4 - 3 : DPC 6 : POWER 1
5
-1 : CRT-D(R)
5
-2 : CRT-D(G)
2 : DEFLECTION
1 : MAIN
10 : DIGITAL CONVER
14 : AUTOLIVE 13 :WAC
8 : SW DVD
DOLBY PRO 16 -2: 7 FRO. SURR
12
YCS
11 - 6 : DUAL
9 POWER STARSIGHT (TW56F80 ONLY)
15 : STARSIGHT
7 - 1: NEW OSD
4 - 2 : SPEAKER
4 - 1 : A/V
Fig. 1-5
8. CONSTRUCTION OF CHASSIS
A110 A110B 2pcs A505 BIDT2 4x12 2pcs
A401 A522 BIDT2 4X12 18pcs
K601 A126 A520 PP 5x18 4pcs A110A
A101 A512 BIDT2 4x12 6pcs A201 A517 PBI 4X16 8pcs
A517
A902 A521 BRT TBS 4x16 2pcs A502 PMM 4x16 4pcs
Z410 B202
A351 A127
A353
A128 PMM 4x16 A205 A506 2pcs BRB TBS 4x16 4pcs A515 PMM 4X16 4pcs W661~ W664 A501 BTA 4x16 16pcs A106 A508 BIDT2 4x12 2pcs K511 A523 PMM 4x16 2pcs A102 A509 BTA 4x16 4pcs A107 A511 PP4x14 4pcs K103 L462~ L464 A503 PMM 4x16 8pcs A519 BIDT2 4x12 5pcs
A516 PMS 3.8x28 3pcs A202
A105 A104 A105 A508 BIDT2 4x12 4pcs A513 BIDT2 4x12
L472~ L474 A510 BRBTB 5x16 4pcs
A104 V901R V902G V903B
A108
Fig. 1-6
11
SECTION II: TUNER, IF/MTS/S. PRO MODULE 1. CIRCUIT BLOCK
IF/MTS/S.PRO Module MVUS34S EL466L Tuner RF AGC
C-IN R-IN L-IN TP12 Video output TV R-OUT TV L-OUT R-OUT C-OUT L-OUT (L+R) -OUT
SAW Filter
VIF/SIF Circuit
SIF output
Sound Multiplex Circuit
S.PRO Circuit
AFT output
To A/V switch circuit
Fig. 2-1 Block diagram
1-1. Outline
(1) RF signals sent from an antenna are converted into intermediate frequency band signals (video: 45.75 MHz, audio: 41.25 MHz) in the tuner. (Hereafter, these signals are called IF signals.) The IF signals are band-limited in passing through a SAW filter. The IF signals band-limited are detected in the VIF circuit to develop video and AFT signals. The band-limited IF signals are detected in the SIF circuit and the detected output is demodulated by the audio multiplexer, developing R and L channel outputs. These outputs are fed to the A/V switch circuit. A sound processor (S.PRO.) is provided. (6) (7) (5) VIF/SIF circuit uses PLL sync detection system to improve performances shown below: · · · Telop buzz in video over modulation DP, DG characteristics (video high-fidelity reproduction) Cross color characteristic (coloring phenomenon at color less high frequency signal objects)
(2) (3) (4)
HIC SBX1637A-22 is used in the audio multiplexer circuit to minimize the size with increased performance. As a sound control processor, TA1217N is used. I2Cbus data control the DAC inside the IC to perform switching of the audio multiplexer modes.
(5)
1-2. Major Features
(1) (2) (3) (4) The VIF/SIF circuit is fabricated into a small module by using chip parts considerably. As the tuner, EL466L that which contains an integrated PLL circuit is employed. Wide band double SAW filter F1802R used. FS (frequency synthesizer) type channel selection system employed.
12
1-3. Audio Multiplex Demodulation Circuit
The sound multiplex composite signal FM-detected in the PIF circuit enters pin 12 of HIC (hybrid IC) in passing through the separation adjustment VR RV2 and amplified. After the amplification, the signal is split into two: one enters a de-emphasis circuit, and only the main signal with the L-R signal and a SAP signal removed enters the matrix circuit. At the same time, the other passes through various filters and trap circuits, and the L-R signal is AM-demodulated, and the SAP is FM-demodulated.
Then, both are fed to the matrix circuit. At the same time, each of the stereo pilot signal fH and the SAP pilot signal 5fH is also demodulated to obtain an identification voltage. With the identification voltage thus obtained and the user control voltage are used to control the matrix. The audio signals obtained by demodulating the sound multiplex signal develop at pin 10 and 11 of HIC and develop the terminals of 12 and 14 of the module.
MVUS34S
MPX Out
9 10 11
TV TV DAC-out1 R-Out (SURR ON/OFF) L-Out
12 13 14
DAC-out2 (RFSW)
15
Monitor the input pin for multiplex sound IC
Stereo 0V Other 5V
SAP 0V Other 5V
OFF 0V ON 9V
RF1 RF2
0V 9V
TV waveform detection TV waveform detection output (R) output (L) To AV select circuit
Fig. 2-2 Block diagram of MVUS34S Note: Table 2-1 Matrix for broadcasting conditions and reception mode Output OSD display Broad- Switching 12 pin 14 pin casted mode Stereo SAP (R) (L) Stereo STE SAP MONO Mono STE SAP MONO Stereo STE + SAP SAP MONO Mono + SAP STE SAP MONO R R L+R L+R L+R L+R R SAP L+R L+R SAP L+R L L L+R L+R L+R L+R L SAP L+R L+R SAP L+R Of the mode selection voltages, switching voltages for STE, SAP, MONO do not output outside the module. They are used inside the module to control the BUS.
· · ·
· · ·
· · · · · · ·
: Available, : Not available
13
1-4. A.PRO Section (Audio Processor)
The S.PRO section has following functions. (1) (2) (3) (4) Woofer processing (L+R output) High band, low band, balance control Sound volume control, cyclone level control Cyclone ON/OFF
All these processing are carried out according to the BUS signals sent from a microcomputer. Fig. 2-3 shows a block diagram of the A.PRO IC.
TA1217N
1
27 29 22 32 36
30
9
8
28
Lin Rin Cin
34 BALANCE 30 2 TONE CONTROL Center LEVEL
26 25 VOLUME 18 10 Woofer LEVEL 17 16 I/O 15 14
L out R out
C out W out
Win
3
LPF
SDA SCL
20 I C 21 4 5 6 7 31
2
13 D/A CONV 12 11 24 23 22 19 SAP Ident. STE Ident.
R-in
C-in
L-in
SCL
SDA
W-out O-out
L-out
From From A/V Dolby
From A/V
to Q670 to Q640 to Q670 Via QS101
to Q670
Fig. 2-3 A.PRO block diagram
14
Configuration of the audio circuit and signal flow are given in Fig. 2-4
A/V PCB VIF+MTS+S.PRO MODULE R 12 L 14 R
VIDEO 1 VIDEO 2 OR DVD VIDEO 3 (FRONT INPUT) EQ ER 6 R 7 L
ICV01
MOTHER TV CHILD TV
FOR POP IF MODULE L 29 R 31 L 2 R 1
VIDEO OUTPUT TERMINAL
AUDIO L R PIP OUT (AUDIO) (TW40F80 NOT USE)
L L
R
11 L 13 R 3 L 9 R 15 L 17 R
VIDEO 1 VIDEO 2
PIP OUTPUT
R
L
VIF+MTS+A.PRO MODULE
R OUT 25
+
Q601 R R
2 11
VIDEO 3
R 35 L 37
AS AR
FRONT SURROUND UNIT
16 R 18 L
W OUT 22 L OUT 24
+
L
5
7
L
R L
VARIABLE AUDIO OUTPUT TERMINAL AI AJ
Fig. 2-4
15
2. POP TUNER
Label Name Lot No.
1
15
TUNER SECTION
SAW FILTER
VIF/SIF CIRCUIT
Terminal No.
RF AGC
Name NC 32V S-CLOCK S-DATA NC ADDRESS 5V RF AGC 9V AUDIO GND AFT NC GND VIDEO
1 2
VIDEO AUDIO AFT OUTPUT OUTPUT OUTPUT
3 4 5 6 7 8 9 10 11 12 13 14 15
Fig. 2-5
2-1. Outline
The POP tuner (EL922L) consists of a tuner and an IF block integrated into one unit. The tuner receives RF signals induced on an antenna and develops an AFT output, video output, and audio output. The tuner has receive channels of 181 as in the tuner for the main screen and it is also controlled through the I 2C-bus. As the IC for the IF, a PLL complete sync detection plus audio inter carrier system are employed.
Fig. 2-6 Tuner terminal layout
16
SECTION III: CHANNEL SELECTION CIRCUIT 1. OUTLINE OF CHANNEL SELECTION CIRCUIT SYSTEM
The channel selection circuit in the N5SS chassis employs a bus system which performs a central control by connecting a channel selection microcomputer to a control IC in each circuit block through control lines called a bus. In the bus system which controls each IC, the I2C bus system (two line bus system) developed by Philips Co. Ltd. in the Netherlands has been employed. The ICs controlled by the I2C bus system are: IC for V/C/D signal processing (Q501), IC for A/V switching (QV01), IC for non volatile memory (QA02), Main and sub U/V tuners (H001, HY01), IC for deflection distortion correction (Q302), IC for POP and Double Window signal processing (QY03), IC for closed caption control (QM01), IC for WAC control (QX01), IC for 3D-YCS (QZ01), IC for AUTOLIVE (QK06). Differences from N5SS chassis are as follows; 1. On-screen function inside microcomputer is used. Separate IC is not used for on-screen. 2. The microcomputer does not have the closed caption function, but controls separate IC for closed caption. 3. The system uses two channels of I2C bus. One is only for non-volatile memory.
2. OPERATION OF CHANNEL SELECTION CIRCUIT
Toshiba made 8 bit microcomputer TLCS-870 series for TV receiver, TMP87CS38N-3320 is employed for QA01. With this microcomputer, each IC and circuit shown below are controlled. (1) CONTROL OF VIDEO/CHROMA/DEF SIGNAL PROCESS IC (Q501 Toshiba TA1222AN) · · · Adjustments for uni-color, brightness, tint, color gain, sharpness and PIP uni-color Setting of adjustment memory values for subbrightness, sub-color and sub-tint, etc. Setting of memory values for video parameters such as white balance (RGB cutoff, GB drive) and gcorrection, etc. Setting of video parameters of video modes (Standard, Movie, Memory) (7) (5) (4) CONTROL OF U/V TUNER UNIT (H001 Toshiba ELA12L, HY01 Toshiba EL922L) · A desired channel can be tuned by transferring a channel selection frequency data (divided ratio data) to the I2C bus type frequency synthesizer equipped in the tuner, and by setting a band switch data which selects the UHF or VHF band.
CONTROL OF DEFLECTION DISTORTION CORRECTION IC (Q302 Toshiba TA8859P) · Sets adjustment memory value for vertical amplitude, linearity, horizontal amplitude, parabola, corner, trapezoid distortion.
(6)
· (2)
CONTROL OF POP & Double Window SIGNAL PROCESS IC (QY03 Toshiba TC9092AF, QY91 Sony CXP85116B-514Q) · Controls ON/OFF and 9 pictures serch of POP. CONTROL OF CLOSED CAPTION/EDS (QM01 Motorola XC144144P) · Controls Closed Caption/EDS. Controls Wide Aspect. Controls ON/OFF of 3 Dimension Y/C separator. CONTROL OF WAC (QX01 Toshiba TC9097F) · CONTROL OF 3D-YCS (QZ01 Toshiba TC9086F) ·
CONTROL OF A/V SWITCH IC (QV01 Toshiba TA1218N) · · Performs source switching for main screen and sub screen Performs source switching for TV and three video inputs
(8) (9)
(3)
CONTROL OF NON-VOLATILE MEMORY IC (QA02 Microchip 24LC08BI/P) · Memorizes data for video and audio signal adjustment values, volume and woofer adjustment values, external input status, etc. Memorizes adjustment data for white balance (RGB cutoff, GB drive), sub-brightness, sub color, sub tint, etc. Memorizes deflection distortion correction value data adjusted for each unit. 17
(10) CONTROL OF VERTICAL AMPLITUDE (QK06 Toshiba TMP87CM36N) · Controls Wide Mode. (11) CONTROL OF OSD (Do not I2C BUS) (QR60 Fujitsu MB90091) · Controls of OSD Menu.
·
·
3. MICROCOMPUTER
Microcomputer TMP87CS38N-3320 has 60k byte of ROM capacity and equipped with OSD function inside. The specification is as follow. · · · · · · · · Type name : TMP87CS38N-3320 ROM : 60k byte RAM : 2k byte Processing speed : 0.5m s (at 8MHz with Shortest command) Package : 42 pin shrink DIP I2C-BUS : two channels PWM : 14 bit x 1, 7 bit x 9 ADC : 8 bit x 6 (Successive comparison system, Conversion time 20ms)
2
· · ·
Self diagnosis function which utilizes ACK function of I2C is equipped Function indication is added to service mode. Remote control operation is equipped, and the control by set no touch is possible. (Bus connector in the conventional bus chassis is deleted.) Substantial self diagnosis function (1) B/W composite video signal generating function (micom inside, green crossbar added) (2) Generating function of audio signal equivalent to 1kHz (micom inside) (3) Detecting function of power protection circuit operation (4) Detecting function of abnormality in IIC bus line (5) Functions of LED blink indication and OSD indication (6) Block diagnosis function which uses new VCD and AV SW
·
IIC device controls through I C bus. (Timing chart : See Fig. 3-1) · LED uses big current port for output only. · · For clock oscillation, 8MHz ceramic oscillator is used. I2C has two channels. One is for EPROM only.
SDA SCL Start condition
1-7 Address
8 R/W
9 Ack
1-7 Data
8
9 Ack
1-7 DATA
8
9 Ack Stop condition
Approx.180µS
Some device may have no data, or may have data with several bytes continuing.
Fig. 3-1
18
4. MICROCOMPUTER TERMINAL FUNCTION
TMP87CS38N3320 (QA01)
GND BAL REM OUT MUTE SP MUTE NC POWER LED SSRST DVD CONT IIC -BUS SCL0 SDA0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 I O O O O O O O I O IO I 0 I I I I O O
GND P40 (PWM0) P41 (PWM1) P42 (PWM2) P43 (PWM3) P44 (PWM4) P45 (PWM5) P46 (PWM6) P47 (PWM7) P50 (PWM8/TC2) P51 (SCL1) P52 (SDA1) P53 (AINO/TC1) P54 (AIN1) P55 (AIN2) P56 (AIN3) P60 (AIN4) P61 (AIN5) P62 P63 VSS
VDD P57 P32 P57 SDA0 SCL0 (TC3)P31 (RXIN)P30 P20 RESET XOUT XIN TEST 0SC2 0SC1 VD OSD RESET DATA BUSY CS CLK I I I IO O I I I I O I I O I I 0 O I O O
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
VDD ACP SS VD I 2C STOP SDA1 SCL1 IICBUS
SYNC AV1 RMT IN EXT SP RESET XOUT XIN GND 0SC1 0SC2 VSYNC OSD RESET DATA BUSY CS CLK
SYNC VCD PIPRST AFT2 AFT1 KEY-A KEY-B SGV SGA GND
Fig. 3-2
19
<< MICROCOMPUTER TERMINAL NAME AND OPERATION LOGIC >> No. Terminal Name Function In/Out Logic 1 GND 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 BAL REM OUT MUTE SP MUTE DEF POW POWER LED SS RST DVD CONT SCL0 SDA0 SYNC VCD PIP RST AFT2 IN AFT1 KEY A KEY B SGV SGA VSS CLK CS BUSY DATA OSD RESET VSYNC OSC1 OSC2 TEST XIN XOUT RESET EXT SP RMT IN SYNC AV1 SCL1 SDA1 I2C STP SS VD ACP VDD INPUT BALANCE REMOTE CONTROL SIGNAL OUT SOUND MUTE OUT SPEAKER MUTE POWER ON/OFF OUT POWER LED OUTPUT STARSIGHT RESET DVD CONTROL IIC BUS CLOCK OUT Out Out Out Out Out Out Out Out Out Out PWM out Remote control output Sound mute output In muting = H Power control In ON = H Power LED on-control LED lighting = L Reset = L DVD = L, Other = H IIC bus clock output 0 IIC bus data input/output 0 Main picture H. sync signal input Reset = L Sub tuner AFT S-curve input Main tuner AFT S-curve signal input Local key detection: 0 to 5V Local key detection: 0 to 5V Test signal output In normal = L Test audio output In normal = L 0V: Gounding voltage
Remarks 0V
0V 0V
IIC BUS DATA IN/OUT In/Out H SYNC INPUT In PIP RESET UV MAIN S-CURVE SIGNAL LOCAL KEY INPUT LOCAL KEY INPUT TEST SIGNAL OUT TEST AUDIO OUT POWER GROUNDING CLOCK OSD CHIP SELECT BUSY OSD DATA OSD RESET OSD DISPLAY CLOCK DISPLAY CLOCK TEST MODE SYSTEM CLOCK SYSTEM CLOCK SYSTEM RESET EXTERNAL SPEAKER REMOTE CONTROL SIGNAL INPUT HSYNC INPUT IIC BUS CLOCK OUT IIC BUS DATA IN/OUT IIC BUS STOP STARSIGHT VD NSYNC INPUT POWER Out In In In In Out Out -- Out Out In Out Out In Out In In In Out In In In In Out In/Out In In In -- 20
0V 0V 0V At display on: Pulse At display on: Pulse At display on: Pulse At display on: Pulse Pulse Pulse Pulse 0V 8MHz pulse 8MHz pulse 5V In reception of remote pulse Pulse Pulse Pulse Pulse 5V
Reset = L VSYNC 4.5MHz GND fixed System clock input System clock output 8MHz System reset input (In reset = L) EXTERNAL = L, INT = H In remote control pulse input = L External H. sync signal input IIC bus clock output 1 IIC bus data input/output 1 STOP = L VSYNC for Starsight AC pulse input 5V
5. EEPROM (QA02)
EEPROM (Non volatile memory) has function which, in spite of power-off, memorizes the such condition as channel selecting data, last memory status, user control and digital processor data. The capacity of EEPROM is 8k bits. Type name is 24LC08BI/P or ST24C08CB6, and those are the same in pin allocation and function, and are exchangeable each other. This IC controls through I2C bus. The power supply of EEPROM and MICOM is common. Pin function of EEPROM is shown in Fig. 3-3.
EEPROM(QA02)
A0 Device adress GND A1 A2 Vss
1 2 3 4
8 Vcc + 5V 7 NC 6 SCL I2C-BUS line 5 SDA
Fig. 3-3
6. ON SCREEN FUNCTION
The OSD system of TW40F80 employs the external OSD IC (QR60, MB90091) to obtain high quality OSD. QR60 is controlled by the microprocessor QA01 with the exclusive control signals of CLK, DATA, CS, BUSY, RESET.
QA01 Microprocessor
QR60 MB90091
CLK
22
54
SCLK
R OUT
59
CS
23
56
SCS
G OUT
60
BUSY
24
58
TRE
B OUT
61
DATA
25
55
SIN
OSD RESET
26
16
RESET
VIDEO (YM)
64
VOB2
Fig. 3-4
21
7. SYSTEM BLOCK DIAGRAM
QA01 TMP87CS38N-XXXX QA02 Memory 24LC08BI/P SDA SCL 5 6 11 SCL 0 12 SDA 0 V.sync pulse 40 INT4 27 VSYNC KEY-A 17 KEY-B 18 33 42 1 21 7 41 8 SDA 1 38 SCL 1 37 RMT 35 Remote controller light receiving unit Key switch Power supply circuit HO01 Main U/V tuner ELA12L SDA SCL
HY01 Sub U/V tuner EL922L SDA SCL
Remote controller output
3
RST VDD GND VSS RMT OUT POWER ACP LED MUTE SP MUTE
Q501 VCD TA1222AN SDA SCL 27 28 HO02 IF/MPX/A.PRO MVUS5345 SDA SCL 21 20
Audio mute Speaker mute
4 5
XIN 31 XOUT 32
8MHz Clock
25 22 23 24 26
DATA CLK CS BUSY RESET
SGV 19 SGA 20
Signal output
QV01 AV SW TA1218N SDA SCL 24 25
DPC unit Main screen SYNC-AV1 36 Sync det. AFT1 IN 16 AFT det. Sub screen SYNC-AV2 13 Sync det. AFT det. AFT2 IN 2 DATA CLK
QZ01 YCS TC9086F SDA SCL 20 19 QY91 DUAL microprocessor SDA SCL QY03 POP TC9092F
QR60 OSD MB90091 CLK DATA CS BUSY 55 56 58 54 QX01 WAC TC9097F SDA SCL 60 59
QH30 C/C,EDS XC144144P SDA SCL 14 15 Q701 CONVER T7K64 SDA SCL 44 43
QK06 AUTO LIVE SDA SCL 40 39
Fig. 3-5
22
8. LOCAL KEY DETECTION METHOD
Local key detection in the N5SS chassis is carried out by using analog like method which detects a voltage appears at local key input terminals (pins 17 and 18) of the microcomputer when a key is pushed. With this method using two local key input terminals (pins 17 and 18), key detection up to maximum 14 keys will be carried out. The circuit diagram shown left is the local key circuit. As can be seen from the diagram, when one of keys among SA01 to SA-08 is pressed, each of two input terminals (pins 17 and 18) developes a voltage VIN corresponding to the key pressed. (The voltage measurement and key identification are carried out by an A/D converter inside the microprocessor and the software.
17 SA08
18
SA01
SA06
SA02
SA05
SA03
SA07
SA04
Fig. 3-6 Local key assignment
Table 3-1 Local key assignment Key No. SA-02 SA-03 SA-04 SA-05 SA-06 SA-07 SA-08 Function POWER CH UP CH DN VOL UP VOL DN ANT/VIDEO, ADV MENU Key No. SA-01 Function DEMO START/STOP
23
9. REMOTE CONTROL CODE ASSIGNMENT
Custom codes are 40-BFH (TV set for North U.S.A.) Code 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH Function 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 6 Channel 8 Channel 8 Channel 100 Channel ANT 1/2 RESET AUDIO PICTURE/FUNC TV/VIDEO MUTE CHANNEL SEARCH POWER MTS ADD/ERASE TIMER/CLOCK AUTO PROGRAM CHANNEL RETURN DSP/SUR (TV/CATV) CONTROL UP VOLUME UP CHANNEL UP RECALL CONTROL DOWN VOLUME DOWN CHANNEL DOWN PIP LOCATE PIP LOCATE PIP LOCATE PIP LOCATE CARVER SURROUND UP SURROUND DOWN VOCAL ZOOM CHANNEL LOCK PIP CHANNEL UP PIP CHANNEL DOWN PIP STILL/RELEASE PIP ZOOM, ZOOM SIZE PIP LOCATE (CH SEARCH) PIP SOURCE Applicable to remote control Applicable Contito TV set nuity
Custom codes are 40-BFH (TV set for North U.S.A.)
Code
50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH 90H 91H 92H 93H 94H 95H 96H 97H 98H 99H 9AH 9BH 9CH 9DH 9EH 9FH
Function
Applicable to remote Applicable Contito TV set nuity control
PIP STILL PIP ON/OFF Do not use. Old type core power ON PIP SWAP PIC SIZE DSP F/R WIDE/SCROLL CAPTION EXIT CYCLONE, SBS SET UP OPTION SUB WOOFER UP SUB WOOFER DOWN
MENU EDS ADV UP ADV DWN GUIDE THEME LIST PIP CONTROL ENTER/TUNE PAGE UP DATA UP PAGE DN DATA DN CANCEL REC
Do not use. Old type core power ON
NOISE CLEAN
PIP VOLUME UP PIP CONTROL PIP VOLUME DOWN
24
Custom codes are 40-BFH (TV set for North U.S.A.) Code A0H A1H A2H A3H A4H Function SUB-BRIGHT ADJUSTMENT G. DRIVE ADJUSTMENT B. DRIVE ADJUSTMENT Applicable Contito TV set nuty Code
Custom codes are 40-BFH (TV set for North U.S.A.) Function Applicable Contito TV set nuty
CUTOFF DRIVE 40H INITIALIZING, HORIZONTAL ONE LINE A5H R. CUTOFF ADJUSTMENT A6H G. CUTOFF ADJUSTMENT A7H B. CUTOFF ADJUSTMENT A8H MEMORY ALL AREA INITIALIZE A9H PIP BRIGHT ADJUSTMENT AAH SUB CONTRAST ADJUSTMENT ABH HOR, VER PICTURE POSITON ADJUSTMENT ACH SUB COLOR ADJUSTMENT ADH SUB TINT ADJUSTMNET AEH ADJUSTMENT-UP AFH ADJUSTMENT-DOWN B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H C1H C2H C3H C4H C5H C6H C7H C8H C9H CAH CBH CCH CDH CEH CFH HORIZONTAL ONE LINE: SERVICE DSP ON/OFF TEXT-1 TV/PIP VIDEO CHANGE-OVER CAPTION-1
D0H D1H D2H Do not use. Old type core power ON D3H D4H D5H D6H D7H PIP VIDEO ADJ. D8H STILL, FRAME ADVANCE D9H DAH SPEED DBH DCH ZOOM DDH DEH DFH E0H E1H PINCUTION/EW CORER (PARA/CNR) VERTICAL S-CUVE CORRECTION/ VERTICAL M-CURVE CORRECTION (VSC/FVC)
TV/CABLE CHANGE-OVER IN SAME TIME ON MAN AND SUB HOTEL SETTING MENU DATA 4 TIMES SPEED UP DATA 4 TIMES SPEED DOWN CHANGE-OVER OF HOTEL/NORMAL PIP CENTER M MODE CAPTON OFF ALL CHANNEL PRESET DIRECT WIDE 1 DIRECT FULL
E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH E0H E1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH
HORIZONTAL WIDTH (WID/PARA) TRAPEZOIDE CORRECTION (TRAP) TEST TONE DOLBY 3 DIMENTIONAL Y/C SEPARATION DPC STANDARD (HEIGHT LINEARITY) (VLIN/HIT) WIDE (HEIGHT ® LINEARITY) (VLIN) SCROOL WIDE 1, 2, 3
25
9-1. Optional Setting for Each Model
OPT0 MODELS CN35F90 CN35F95 CX35F70 TW56F80 TW40F80 TP61F90 TP61F80 TP55F80 TP55F81 TP50F90 TP50F60 TP50F61 D7 0 0 1 0 1 0 0 0 0 0 1 1 D6 D5 0 0 0 0 0 0 0 0 0 0 0 0 D4 0 0 1 0 1 0 1 1 1 0 1 1 D3 D2 0 0 0 0 0 0 0 0 0 0 0 0 D1 0 0 1 1 1 1 1 1 1 1 1 1 D0 HEX 00H 00H 02H 02H 92H 02H 12H 12H 12H 02H 92H 92H D7 0 0 0 0 0 0 0 0 0 0 0 0 D6 0 0 0 0 0 0 0 0 0 0 0 0 D5 0 0 0 0 0 0 0 0 0 0 0 0 D4 0 0 0 1 1 1 1 1 1 1 1 1
OPT1 D3 0 0 0 1 1 1 0 0 0 0 0 0 D2 0 0 0 1 0 1 0 0 0 1 0 0 D1 D0 HEX 00H 00H 00H 1CH 18H 1CH 18H 10H 10H 14H 10H 10H
* * * * * * * * * * * *
* * * * * * * * * * * *
* * * * * * * * * * * *
* * * * * * * * * * * *
* * * * * * * * * * * *
Normal 0/f0 STOP 1
Normal 0/Free run 1
CYC0/SBS1
DSP0/SRD1
NOT USED
NOT USED
NOT USED
NOT USED
· When the character generation is changed from MB90091-107 TO MB90091-108, D5 bit of OPT0 in the design data should be set to "1".
26
NOT USED
PP0/MP1
Normal00 STD: 01 HRC: 10 1RC: 11
NON0/DOLBY1
MODE: Fixed NON0/CONV1 NON0/3DYC
SS/0 NONSS/1
10. ENTERING TO SERVICE MODE
1. PROCEDURE (1) (2) (3) (4) Press once MUTE key of remote hand unit to indicate MUTE on screen. Press again MUTE key of remote hand unit to keep pressing until the next procedure. In the status of above (2), wait for disappearing of indication on screen. In the status of above (3), press MENU (Channel setting) key on TV set.
12. SERVICE ADJUSTMENT
1. ADJUSTMENT MENU INDICATION ON/OFF : MENU key (on TV set) 2. During display of adjustment menu, the followings are effective. a) Selection of adjustment item : POS UP/DN key (on TV/remote unit) b) Adjustment of each item : VOL UP/ DN key (on TV / remote unit) c) Direct selection of adjustment item R CUTOFF : : : : : 1 POS (remote unit) 2 POS (remote unit) 3 POS (remote unit) 4 POS (remote unit) 6 POS (remote unit) VIDEO (on TV set) G CUTOFF B CUTOFF SUB CONTRAST SUB COLOR : SUB TINT f) Test signal selection :
2. Service mode is not memorized as the last-memory. 3. During service mode, indication S is displayed at upper right corner on screen.
d) Data setting for PC unit adjustment
11.
TEST SIGNAL SELECTION
5 POS (remote unit)
1. In OFF state of test signal, SGA terminal (Pin 20) and SGV terminal (Pin 21) are kept "L" condition. 2. The function of VIDEO test signal selection is cyclically changed with VIDEO key (remote unit). Table 3-2
Test Signal No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name of Pattern Signal OFF All black signal + R single color (OSD) All black signal + G single color (OSD) All black signal + B single color (OSD) All black signal All white signal W/B Black cross bar White cross bar Black cross hatch White cross hatch White cross dot Black cross dot H signal (bright area) H signal (dark area) Black cross + G signal color
e) Horizontal line ON/OFF :
VIDEO (remote unit)
* In service mode, serviceable items are limited. 3. Test audio signal ON / OFF : * Test audio signal : 1 kHz 4. Self check display : 9 POS (remote unit) 8 POS (remote unit)
* Cyclic display (including ON/OFF) 5. Initialization of memory : CALL (remote unit) + POS UP (on TV set) 6. Initialization of self check data : CALL (remote unit) + POS DN (on TV set) 7. BUS OFF : CALL (remote unit) + VOL UP (on TV set)
(3)
SGA (audio test signal) output should be square wave of 1 kHz. 27
13. FAILURE DIAGNOSIS PROCEDURE
Model of N5SS chassis is equipped with self diagnosis function inside for trouble shooting.
13-1. Contents to be Confirmed by Customer
Table 3-3
Contents of self diagnosis A. DISPLAY OF FAILURE INFORMATION IN NO PICTURE (Condition of display) 1. 2. When power protection circuit operates; When I2C-BUS line is shorted;
Display items and actual operation Power indicator lamp blinks and picture does not come. 1. 2. Power indicator red lamp blinks. (0.5 seconds interval) Power indicator red lamp blinks. (1 seconds interval)
If these indication appears, repairing work is required.
13-2. Contents to be Confirmed in Service Work (Check in self diagnosis mode)
Table 3-4
Contents of self diagnosis Contents of self diagnosis < Countermeasure in case that phonomenon always arises > B. Detection of shortage in BUS line. C. Check of comunication status in BUS line. D. Check of signal line by sync signal detection. E. F. Indication of part code of microcomputer (QA01). Number of operation of power protection circuit. Display items and actual operation Display items and actual operation
(Example of screen display) SELF CHECK
NO. 239XXXX POWER: 000000 BUS LINE: OK BUS CONT: OK BLOCK: UV Part coce of QA01 Number of operation of power protection circuit Short check of bus line Communication check of busline V1 V2 QV01, QV01S E F B C D
13-3. Executing Self Diagnosis Function
[CAUTION] (1) When executing block diagnosis, get the desired input mode (U/V BS VIDEO1, 2, 3) screen, and then enter the self diagnosis mode. When diagnos other input mode, do again diagnosis operation. 13-3-1. Procedure (1) (2) Set to service mode. Pressing "9" key on remote unit displays self diagnosis result on screen. Every pressing changes mode as below. SERVICE mode (3) SELF DIAGNOSIS mode
(2)
To exit from service mode, turn power off.
28
13-4. Understanding Self Diagnosis Indication
In case that phenomenon always arises. See Fig. 3-7 .
(Example of screen display) SELF CHECK
NO. 239XXXX POWER: 000000 BUS LINE: OK BUS CONT: OK BLOCK: UV Part coce of QA01 Number of operation of power protection circuit Short check of bus line Communication check of busline V1 V2 QV01, QV01S E F B C D
Fig. 3-7
Table 3-5
Item BUS LINE Contents Detection of bus line short Instruction of results Indication of OK for normal result, NG for abnormal Indication of OK for normal result Indication of failure place in abnormality (Failure place to be indicated) QA02 NG, H001 NG, Q501 NG, H002 NG, QV01 NG, Q302 NG, QY02 NG, HY01 NG, QD04 NG, QM01 NG, Q701 NG BUS CONT Communication state of bus line Note: The indication of failure place is only one place though failure places are plural. When repair of a failure place finishes, the next failure place is indicated. (The order of priority of indication is left side.) BLOCK: UV1 UV2 V1 V2 The sync signal part in each video signal supplied from each block is detected. Then by checking the existence or non of sync part, the result of self diagnosis is displayed on screen. Besides, when "9" key on remote unit is pressed, diagnosis operation is first executed once. * Indication by color · Normal block · Non diagnosis block : Green : Cyan
29
13-4-1. Clearing method of self diagnosis result In the error count state of screen, press "CHANNEL DOWN" button on TV set pressing "DISPLAY" button on remote unit.
White Yellow Cyan Green Magenta Red
CAUTION: All ways keep the following caution, in the state of service mode screen. · Do not press "CHANNEL UP" button. This will cause initialization of memory IC. (Replacement of memory IC is required.) · Do not initialize self diagnosis result. This will change user adjusting contents to factory setting value. (Adjustment is required.) 13-4-2. (1) Method utilizing inner signal (COLOR BAR SIGNAL) Color elements are positioned in sequence of high brightness.
Blue
(VIDEO INPUT 1 terminal should be open.) With service mode screen, press VIDEO button on remote unit. If inner video signal can be received, QV01 and after are normal. With service mode screen, press "8" button on remote unit. If sound of 1 kHz can be heard, QV01 and after are normal.
(2)
* By utilizing signal of VIDEO input terminal, each circuit can be checked. (Composite video signal, audio signal)
30
14. TROUBLESHOOTING CHART
14-1. TV does Not Turned ON
TV does not turned on. YES Relay sound NO Check of voltage at pin 7 of QA01 (DC 5V). OK Check power circuit. NG NG
8MHz oscillation waveform at pin 32 of QA01. OK
Check OSC circuit. Replace QA01. NG Pulse output at pins 37 and 38 of QA01. OK Voltage check at pin 32 of QA01 (DC 5V) OK Check reset circuit. NG
Check relay driving circuit.
Replace QA01.
31
14-2. No Acception of KEY-IN
Key on TV
Voltage change at pins 17, 18 of QA01 (5V to 0V). OK Replace QA01.
NG
Check key-in circuit.
Remote unit key
Pulse input at pin 35 of QA01, When remote unit key is pressed. OK
NG
Replace QA01
Check tuner power circuit.
14-3. No Picture (Snow Noise)
No picture
Voltage at pins of +5V, and 32V. OK
NG
Check H001.
Check tuner power circuit.
32
14-4. Memory Circuit Check
Memory circuit check NG Voltage check at pin 8 of QA02 (5V).
OK
Check power circuit.
NG Pulse input at pins 5 and 6 of QA02 in memorizing operation. OK Check QA01. Replace QA02. Note: Use replacement parts for QA02.
Adjust items of TV set adjustment.
14-5. No Indication On Screen
No indication on screen. NG Check of RESET at 5V. OK Replace QA01 or QR60 or QR63. Check of CLK, CS, BUSY, DATA at pin 22, 23, 24, 25 of QA01. "H" = 5V or puls? OK NG
Replace QA01 or QR60. NG
Check of character signal at pin 59, 60, 61 of QR60 (5V(p-p)). OK
Replace QR60. Check V/C/D circuit.
33
SECTION IV: DVD SWITCH CIRCUIT 1. DVD SWITCH BLOCK DIAGRAM
Q501 VCD TA1222AN Y 53 Q 52 I Y 51 4 DVD SWITCH UNIT QW01 TC4053BP L Y H Q 5 13 C 15 Y I 6 L Q (B - Y) H L I (R - Y) H ZY01 Y/C SEPARATOR Sub Y. Sub V. Sub C. "L" = Normal "H" = DVD QV01 AV SW TA1218N MAIN 36 Y 34 C 21 QA01 MAICROPROCESSOR
DVD CONTROL
WAC UNIT Y
DUAL UNIT Y
Q
Q
I
Y C
I
42 Sub V. I C BUS
2 2
10
I C BUS
VIDEO2/ Y, Cr, Cb DVD
Insertion detection
VIDEO VIDEO 3 1
Fig. 4-1
34
2. OUTLINE
In this model, the DVD input terminals are provided in order to receive the color difference signals (Y, Cr, Cb) output from a DVD player. The luminance (Y) signal input for DVD input uses the VIDEO input terminal in common with the VIDEO 2 input. The terminals for color difference signal inputs Cr (R Y) and Cb (B Y) are used exclusively. The input identification for VIDEO 2 and DVD is carried out by setting pin 21 of QV01 TA1218N (AV SW IC) from "L" to "H" when the cable is connected to the Cb input terminal with a switch equipped. The main microprocessor QA01 sets pin 10 of QA01 from "L" to "H" through I2C bus when pin 21 of AW SW IC develops "H".
Open : at Cb input Cb to DVD SW unit Cb input RV28 100k RV26 75 RV27 10k +9v
21 QV01 TA1218N
Fig. 4-2
35
SECTION V: WAC CIRCUIT 1. OUTLINE
A wide aspect conversion (hereafter called WAC) process (3/4 compression process in 4:3 mode and 1/2 compression process on left screen in double window mode) is performed inside the WAC unit (PB6348) in TW40F80. Screen modes for TF40F80 contain THEATER WIDE1, THEATER WIDE 2, THEATER WIDE3, FULL, NORMAL and DOUBLE WINDOW modes. The video signal compression is carried out only when either the NORMAL or DOUBLE WINDOW mode is selected. In the modes other than the NORMAL and DOUBLE WINDOW mode, the video signal input to WAC unit is output without performing any process. The screen in the DOUBLE WINDOW mode creates a single screen by superimposing the left screen processed in the WAC unit on the right screen processed in the DUAL unit. On the left screen, the video signal sent is time-compressed to 1/ 2 in horizontal direction to fit in the left half of the wide screen with 16:9 aspect ratio. In this case, a black level of DC is attached on the right half of the screen in this circuit. However, this is superimposed on the right screen, so nothing is visible on the screen. In the normal screen, the video signal is 3/4 time-compressed and side panels in the black level are added on sides of the screen. and pass a low pass filter and amplifiers in the same way as the Y signal, and enter pins 1 and 78 of QX01 respectively. The Y , I and Q signals entered are clamped by built-in clamp circuit, converted into digital signals by the built-in A/D converter. Moreover, their read/write operations are rated up by twice or 3/4 times to perform a compression process of 1/2 or 3/4 times inside the built-in line memory. And then, a black level signal is added to the open area (right half, or both sides of screen). Next, the signal is converted to an analog Y, I, and Q signals by a built-in D/A converter and output from pins 17, 13, and 9. Parameters of 1/2, 3/4 phase of the video signal, phase of the side panel, etc. are controlled through I 2C bus, control signals of which enters from pins 7 and 8 of PX01. Thus processed signals are fed to a low pass filter to remove high frequency noises generated in QX01 and then fed to the QX03 switching IC. The compressed signal and a not compressed signal entered from PX01 are directly fed to QX03, and switched by a signal showing compression/not compression (NCS = output from pin 61 of QX01 and fed to the receive unit through pins 5, 6, and 7 of PX02. 2-2-2. Clock Generation The system clock for QX01 is generated by QX02 according to an H reference signal supplied from pin 3 of PX02 and fed to QX01 through QX19 and QX40. (The frequency is adjusted to 28.7 ± 0.2 MHz with LX18). The compressing operation is carried out by setting the write clock to 1/2 or 3/4 times by the built-in VCO with the reading clock fed to pin 47 of QX01. 2-2-3. Timing Pulse Generation Moreover, the WAC unit generates following timing pulses. (1) VPout Reference signal entered through pin 2 of PX02 enters pin 3 of QX01, and outputs at pin 8 of PX02 after delayed by an amount required. The vertical reference signal is output in modes other than the normal and double window and fed to the vertical circuit. Accordingly, the raster becomes an horizontal one when the unit is disconnected. (2) 2-2-1. Signal Flow Fig. 5-1 shows a block diagram of this circuit. A Y signal entered through pin 6 of PX01 passes a low pass filter an a 6 dB amplifier, and enters pin 3 of QX01. On the other hand, I and Q signals enter through pin 4 and 5 of PX01, 36 HVBLK This pulse is a timing pulse showing a black extension mask period in the normal and double window modes. It outputs at pin 1 of PX02 and enters pin 30 of Q501 in the receive unit.
2. CIRCUIT OPERATION
2-1. Configuration
The WAC unit consists of a wide aspect conversion IC (QX01, TC9097F, working as a central device), clock generation IC (QX02, TA8667F), switch IC (QX03, TC4053BF), and peripheral circuits (LPF, AMP, emitter follower, etc.). The QX01 (TC9097F) contains an A/D converter, D/A converter, clamp circuit, VCO circuit, etc. and performs compression process, etc. inside the IC for analog video signals entered according to controls through IIC bus, thus providing the signal as an analog signal.
2-2. Operation
QX01 TC9097F PX02 VBL 50 1 HVBLK
PX01
9V-2
1
5V-3 QX19 RCK 47 VMO 52 AMP QX28 QX29 LX14 etc QX15 78 QSI LPF QX20 LX15 etc 3 YSI ISO 13 QX11 59 IBC QSO 9 LPF QX22 LX16 etc LPF QX24 LX17 etc 60 IBD VDP 57 NCS 61 9 10 11 I Q Y 1 3 I TH Q TH 13 Y TH QX25 QX23 5 Q WA QX21 2 I WA QX13 YSO 17 12 Y WA LPF LX13 etc LPF LX12 etc AMP QX26 QX27 AMP QX10 QX06 LPF 1 ISI HRE 51 10 11 18
2
VDI 30 QX02 TA8667F QX18
2
VD IN
GND
3
3 ADJ LX18
HD IN
I IN
4
4
GND
Q IN
5
5 QX30 6 QX31 7 QX32 8
YD
Fig. 5-1 Wide aspect conversion unit block diagram (PB6348)
37
Y IN
6
ID
SCL 2
7
QD
SDA 2
8
VP OUT
QX03 TC4053BF
· Pin Function
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
NC
QSI
NC
NC
TDI0
VRA1
TDI1
NC
VSS1(AD)
TDI2
TDI3
VBA
VDD1(AD)
1 2 3 4 5 6 7 8 9
ISI VRA2 YSI NC VBC VRD2 VBD4 VDD3(DA2) QSO
VSS(DIG)
TDI4
BCP(TDI5) 64 NC 63 SE42(TDI6) 62 NCS(TDI7) 61 SDA 60 SCL 59 ACP(TMO0) 58 VDP(TMO1) 57 ISL(TMO2) 56 NC 55 QSL(TMO3) 54 SPT(TMO4) 53 VMO(TMO5) 52 HRF(TMO6) 51 VBL(TMO7) 50 NC 49 HBL(TMO8) 48 RCK 47 WCK 46 VDD(DIG) 45 NC 44 VSS5(VCO2) 43 NC 42
10 NC 11 VBD3 12 VSS3(DA2) 13 ISO 14 VRD1 15 NC 16 VDD2(DA1) 17 YSO 18 VBD2 19 VSS2(DA1) 20 VBD1 21 VSS4(VCO1) 22 VBV 23 NC
VDD4(VCO1)
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Fig. 5-2 Pin function of TC9097F (QFP 80 pin)
38
VDD5(VCO2)
24 VFL1
VBM
VFL2 41
VDD(DIG)
VSS(DIG)
RESET
TST0
TST1
TST2
VLM
HDF
HDI
VDI
NC
NC
NC
NC
Table 5-1 Names and functions of TC9097F
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Name ISI VRA2 YSI NC VBC VBD2 VBD4 AVDD QSO NC VBD3 AGND ISO VRD1 NC AVDD YSO VBD2 AGND VBD1 AGND NC VFV VFL1 AVDD VLM VDD HDI NC VD1 RESET NC NC TST0 TST1 TST2 NC I/O I I O O O I I I I I I I I color signal input Reference voltage (low level) for AD1, AD2 Y signal input Bias for clamp 1 Reference voltage for DA2, DA3 Bias 2 (high level) for DA2, DA3 Analog power Q color signal output Bias 2 (low level) for DA2, DA3 Analog ground I signal output Reference voltage for DA1 Analog power Y signal output Bias 1 (high level) for DA1 Analog ground Bias 2 (high level) for DA1 Analog ground Connected to VSS or VDD Connected to VDD Analog power 1/2 VDD for line memory Digital power Composite sync signal input V sync signal input Reset input (Normally: High level, Reset: Low level) Test mode setting (normally connected to VSS) Test mode setting (normally connected to VSS) Test mode setting (normally connected to VDD) Function
39
No. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
Name HDF GND AVDD VFL2 NC AGND CKSEL VDD WCK RCK HBL NC VBL HRF VMO SPT QSL NC ISL VDP ACP SCL SDA NCS SE42 NC BCP TD14 TD13 TD12 TD11 TD10 NC GND NC NC AVDD VRA1
I/O I I O O O I I I I I I I Analog power Reference voltage for AD1, AD2 V blanking signal H AFC reference signal H AFC mask signal Side panel timing signal Q signal select pulse I signal select pulse V drive pulse Later stage clamp pulse I2C SCL signal input I2C SDA signal input/output Prefilter switch signal 1 Prefilter switch signal 2 Prestage clamp pulse output Ext. H sync signal input Digital ground Analog power Loop filter for VCO2 Analog ground VDD Digital power
Function
Ext. clock input (memory write clock) Ext. clock input (memory read clock) H blanking signal
Test input (normally connected to VSS) Test input (normally connected to VSS) Test input (normally connected to VSS) Test input (normally connected to VSS) Test input (normally connected to VSS) Digital ground
40
No.
80
79
78
77
76
VLM VDD2(DA1) LINE MEMORY (1248x8) VBD1 YSO LINE MEMORY (1248x8) DA1 VRD1 VBD4 POST FILTER Y AD1 VSS2(DA1)
VDD1(AD)
VSS1(AD)
NC
QSI
Name
VBM
VBA
AGND
Y PRE FILTER
YSI
CLAMP1
VBC
3. BLOCK DIAGRAM
VRA1
VBA ISO LINE MEMORY (624x8) VBD2 AD2 LINE MEMORY (624x8) VBD3 Q POST FILTER QSO DA3 VDD3(DA2&3) VSS3(DA2&3) VRD2 DA2 POST FILTER I
VRA2
I
PRE FILTER
ISI
I
Q PRE FILTER
QSI
MPX & CLAMP2
I/O
VBM
HDF
HBL(TMO8) VBL(TMO7) HRF(TMO6) VMO(TMO5) SPT(TMO4) QSL(TMO3) TEST CIRCUIT ISL(TMO2) VDP(TMO1) ACP(TMO0) SCL 1/2 1/456 1/2 I2 C BUS DECODER VCO2 1/2 1/2 1/2 NCS(TDI7) SE42(TDI6) BCP(TDI5) TIMING CONTROLER
Analog ground
Bias for AD1, AD2
Q color signal input
Bias for MPX, clamp 2
Fig. 5-3 TC9097F system block diagram
VFL2 FILTER SCL SDA TDI WCK RCK TST
41
HDI
VDI
VDD(Digital)
VSS(Digital)
VDD(Digital)
VSS(Digital)
Function
VDD4(VCO1)
VSS4(VCO1)
VDD5(VCO2)
VCO1
VSS5(VCO2)
VFL1
FILTER
4. WIDE ASPECT CONVERSION CIRCUIT FAILURE ANALYSIS PROCEDURES
4-1. Left Screen Picture Failure in Normal Mode/Double Window Modes (No Picture, Sync Distributed)
Picture fallure (Normal/DW mode)
Super live mode OK? Y
N
Output at pins 5 , 6 , 7 of PX02 OK? N
Y
Check circuits other than WAC unit.
Check around of QX03. LX18 adjustment OK? Y N Readjustment
I2 C bus pin 7 , 8 of PX01 OK? Y
N
I2 C bus line check.
Is clock at pin 47 of QX01 OK? Y
N
Output at pin 3 (HD) of PX02 OK? N
Y
Check around QX02.
Check receive circuit. Signals at pins 5 , 6 , Y 7 of PX02 OK? N Receive circuit check.
QX01 input / output OK? Y
N
Replace E 2 PROM OK?
Replace QX01.
Check associated circuit (Tr.etc).
END
42
4-2. Raster Horizontal One
Horizontal one
Output at pin 8 of PX02 OK? N
Y
Check V circuit.
Output at pin 2 of PX02 OK? Y
N
Check receive circuit.
Is output OK at I 2 C bus? Y
N
Check I 2 C bus line.
Data initlalization OK? Y
N
Replace QX01.
END
4-2-1. Adjustment Method (1) (2) (3) (4) Disconnect any video inputs Open RX-40. Connect frequency counter to QX19 emitter. Adjust LX18 until frequency reading of "28.7 MHz ± 0.5 MHz" is obtained.
43
SECTION VI: DUAL CIRCUIT
1. OUTLINE
DUAL circuit performs the signal process, etc. on the sub screen and is composed of the followings as shown in Fig. 61. · Video/color/deflection (V/C/D) process · On-screen display (OSD) superimposing process · Sub-screen process, memory · Main/Sub screen picture superimposing process · Sub screen control microprocessor · 9-screen multi-search process The sub screen process IC (TC9092AF) is the IC using the programmable technology and can realize various functions such as sub screen 1/2 compression, 9-screen multi-search, etc. by switching the program. The 9-screen multi-search process is carried out by selecting the channel on the right half of the wide screen with 16:9 aspect ratio and the picture images received are projected on the 9 screens from the upper left screen in order. The search is carried out by approx. every 2 seconds repeatedly. When the next picture image is searched, the picture image on the previous screen becomes a still picture. When the 9 screens are finished projecting (to the picture image on the right bottom screen), the search operation is carried out repeatedly from the upper left screen.)
2. PRINCIPLES OF OPERATION
DUAL circuit is composed of the following functions. (1) (2) (3) (4) Double window sub screen 1/2 compression process Sub screen still process 9-screen multi-search process Main/Sub screen superimposing process by YIQ signal.
44
3. SYSTEM COMPONENT DIAGRAM OF DUAL UNIT
2M memory X2 MSM518221-30ZS
Y From tuner SY Video/color/ deflection process IC µPC1832GT SC R- Y B- Y R- Y B- Y I Q
ON-screen display super impose TC4W53F MC74HC4053F
Y I Q
Sub screen process IC TC9092AF I2 C BUS
Main/Sub picture superimpose MC74HC4053F
OSD
Sub screen control microprocessor CXP85116B-514Q I2 C BUS From main microprocessor From tuner SY SC
Y
I
Q
Y
I
Q
Wide aspect conversion TC9097F
Control
Y
I
Q V/C/D IC TA1222N
To CRT G B R
Fig. 6-1
45
4. CIRCUIT OPERATION
4-1. Video/Color/Deflection Process Section
The video/color/deflection section is shown in Fig. 6-2. The luminance signal is supplied from pin Y08 of PY01 and its frequency bandwidth is limited by the low pass filter (LPF) and then input to pin 36 of V/C/D IC (VIDEO IN). The Y signal output from pin 12 of PY01 superimposes the character signal on the video signal by QY49 and QY44, and then output to the sub screen process section. QY49 and QY44 work as the analog switches. When the screen is displayed in DW, the switch operation is not carried out and the same signal as the input signal is output, and when the 9-screen multi-search process is carried out, the switch operation is carried out. The OSD signal superimposes the shade of character signal by QY49 and the character signal by QY44 on Y signal. On the other hand, the color signal is supplied from pin Y15 of PY01, limited its frequency bandwidth by the band pass filter (BPF) and then input to pin 34 of QY01 (COLOR IN). The color difference signals of the demodulated signal (R Y) and ( B Y) are output from pins 13 and 14 of QY01. In the same way as the Y signal, the (R Y) and (B Y) signals are superimposed on the character signal with OSD signal by QY44. The GBR matrix circuit which converts the Y, R Y and B Y signals into three primary color signal of G, B and R is used to convert the (R Y) and (B Y) signals into I and Q signals. In the GBR matrix circuit, each G, B and R output is output as G Y, B Y and R signals when the Y signal is not input. Then the B Y signal is converted to Q signal, R Y to I signal pseudically by turning the phase by an angle of 33°. Thus, R Y and B Y signals are input to pins 18 and 19 of QY01, and the output signals from pins 23 and 24 are developed as the I and Q converted signals pseudically. The amplitude of the signals is amplified by 6 dB amplifier of QY23 and the signals are output to the sub screen process section. Since the sync signal is added to the luminance signal, the signal is input to pin 39 of QY01 (SYNC SEP IN) and the sync signals of HD and VD are output to pins 10 and 11 of QY01. The HD signal is waveshaped by QY42. The HD signal (WHD1, WHD2) is used as the horizontal pulse for sub screen write and the VD signal (WVD) is as the vertical pulse for sub screen write in the sub screen process section. In the sub screen microcomputer section, various kinds of control signals (brightness, density, hue, etc.) are output from the sub screen control microprocessor QY91 and the signals are used for the level matching adjustment. So the setting for the sub screen cannot be made by the user. Furthermore, the OSD signal for OSD superimposing is output. The sub screen process IC control program is stored in the nonvolatile memory of the sub screen control microprocessor QY91 in order to control the sub screen process IC (TC9092AF), and the data is sent via I2C bus.
46
Signal reception circuit
Sub screen microprocessor section PY01 SCL SDA QY91 CXP85116B-514Q SCLP 50
I2 C BUS(SCL,SDA) OSD OSD QY01 µPC1832GT V/C/D IC 20 COLOR 21 TINT 37 SUB COL. 38 CONTRAST 41 fsc SELECT 42 PAL/NTSC Control R OUT(I) 23 39 SYNC SEPA IN 36 VIDEO IN B OUT(Q) 24 R-Y IN 18 B-Y IN 19 QY22 MM1031XMR 3 3 6dB. Amp 6dB. Amp 1 1 I Q Y OUT 12 R-Y OUT 13 B-Y OUT 14 QY49 TC4W53F 5 OSD superimpose 1 12 5 2 QY44 MC74HC4053F 9 11 14 4 15 Y
Y13 Y14
49 SCL2 SDAP 48 47 SDA2 BLK 46 B 43 COL 53 TIN 54 S.COL 51 CON 52 fsc SEL 62 PAL/NTSC 61 3.58 2 Sub screen control microprocessor
7
Y08
PIP VIDEO
L.P.F
QY23 MM1031XMR QY42 TC74HC123AF
OSD superimpose
Y15
PIP C
B.P.F
34 CHROMA IN
HD OUT 10
1 1A
Waveform shape
1Q 13 2Q 5
WHD2 WHD1 WVD
VD OUT 11
Fig. 6-2
47
To Sub screen process section
4-2. Sub Screen Process Section
The sub screen process section is shown in Fig. 6-3. The Y, I and Q signals from the video/color/deflection process section are limited in their frequency bandwidth by the LPF in the prceeding stage and input to pins 6, 13 and 15 of QY03. The frequency of 18.5 MHz generated by LY102 is multiplied by 1/2 inside QY03. The Y signal is sampled by 9.25 MHz and the I and Q signals are sampled by 4.63 MHz (1/2 frequency to multiplex) and then the signals are converted into 8-bit digital signals. The horizontal sync signal WHD (the signal mixed with WHD1 and WHD2 by QY43) for writing input to pins 21 and 20 of QY03 and the vertical sync signal WVD for trigger writing on the field memory QY10 and QY11. The horizontal sync signal RHD for reading-out and the vertical sync signal RVD for reading out input to pins 75 and 77 of QY03 trigger the reading at 18.0 MHz which is created by 2/3-multiplying 27.0 MHz developed in LY101and then output as the analog signal. The Y, I and Q signals converted for the sub screen are output from pins 95, 100 and 97 of QY03. The output signals are used for the input signals compressed by 1/2 in the horizontal direction in the double window mode and for the input signal compressed by 1/6 in the horizontal direction and by 1/3 in the vertical direction in 9-screen multi-search mode. Then the signals are smoothed by the LPF in the next stage then input to the main/sub screen superimposing section.
QY03 TC9092AF Sub screen process IC Y I
Video/color/deflection process section
L.P.F L.P.F
13 R-Y IN 15 B-Y IN
R-Y OUT(I) 100 B-Y OUT(Q) 97
L.P.F L.P.F
I Q
Q
I2 C BUS (SCL, SDA)
79 SCL 80 SDA
YS OUT 70 QY10, QY11 MSM518221-30ZS
YS
WVD WHD2 WHD1 1 2 OR circuit WHD
20 FVS 4 21 FHS 24 OSCSI 25 OSCSO LY102 77 FVM
MWD 0 48
2M memory Date in
MWD15 32
QY43 TC7S32F
MRD 0 51 Date out MRD15 65
PY01 RVD RHD YS Y01 LY101
75 FHM 72 OSCMI 73 OSCMO
Signal reception circuit
Y11 Y12
Fig. 6-3 Sub screen process section
48
To Main/Sub pictore superimposing process section
L.P.F
6
Y IN
Y OUT 95
L.P.F
Y
4-3. Main/Sub Screen Superimposing Section
The main/sub screen superimposing section is shown in Fig. 6-4. The sub screen Y, I and Q signals sent from the sub screen process section and the main screen Y, I and Q signals sent from the digital unit through the receive circuit and etnered pins 3, 2, and 1 of PY02 are clamped at a same electrical potential and the former are fed to pins 1, 3, 13 and the latter fed to pins 2, 5 and 12 of QY48. The clamp circuit contains a clamp pulse waveshaping SCP at pin 4 of PY02, analog switches for ever-voltage source E, QY46 and QY47 and clamp capacitors CY2