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SCHEMATIC DIAGRAM-7
PANEL CIRCUIT : +B SIGNAL LINE
C922
0.01
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
R970 R969 R965
COM0
COM1
COM2
COM3
SEG6
SEG10
SEG12
SEG13
SEG14
SEG0
SEG1
SEG2
SEG3
SEG15
SEG19
SEG20
SEG4
SEG16
SEG18
SEG17
SEG5
SEG7
SEG11
SEG8
SEG9
82K 82K 68K
1 VLC1 SEG21 75
C923
0.01 2 VLC2 SEG22 74
3 VLC3 SEG23 73
R959 1K
4 NC SEG24 72
R957 1K
5 NC SEG25 71
R956 1K
6 DMT SEG26 70
R971 2.2K ______
7 /MUTEA SEG27 69
R972 2.2K
C933 C927 8 PCONT SEG28 68
X901
RSXZ6M00D01T 47P 82P 9 MBP1 SEG29 67
6.00MHz 10 MBP2 SEG30 66
X901 R964
1K 11 VSS IC901 SEG31 65
Q904 Q903 C934 C926 R967
1M
12 OSC1 MN101C57DAA SEG32 64
47P 82P
13 OSC2 MICRO PROCESSOR SEG33 63
14 MMOD SEG34 62
C932 C931 C921 18P
1000P 1000P 15 X1 SEG35 61
X900 16 X0 SEG36 60
X900 C929
Q903 RSXD32K7S02 R966 17 VDD SEG37 59
18P _____
2CS2712GRT5T 330K 18 NRST PHOTO 58
BEAT PROOF CONTROL
19 VDO MOTOR_H 57
C920 R960 10K
Q904 22P 20 NC E_CS 56
2CS2712GRT5T 21 SUBQ CD_CLOSE 55
BEAT PROOF CONTROL
22 SQCK CD_OPEN 54
23 MCLK/PLLCLK SP_DATA/E_DATA 53 B
M_DATA/PLLDA
A
CD_OPEN_SW
24 RDS_DATA SP_CLK/E_CLK 52
25 RDS_CLK DIMMER 51
REST_SW
VOL_JOG
CD_RST
REGION
PLL_DO
PLL_CE
RMT_IN
REC_H
BLKCK
VREF+
1SS380TE-17
1SS380TE-17
VREF-
PDET
KEY1
KEY2
PL_H
HALT
STAT
MLD
VDD
AN4
AN7
SD
BP
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
C925 R968
100
100
100
0.01 47K
1K
1K
1K
1K
1K
1K
1K
1K
1K
Q902
KRC104STA
D908
D911
C928 C916 4700P
50V1 RESET SWITCH
R963
R962
R961
R955
R954
R953
R952
R950
R949
R948
R945
R944
C915 4700P
C914 4700P
Q902
10K
1K
C913 4700P
1K
1K
100
C912 4700P
C924 C919 C911 4700P
R926
R925
R943
R941
50V1 100P
100
100
C910 4700P
R940
D913
4.7K
1SS380TE-17 C909 4700P
M_DATA/PLLDA
CD_OPEN_SW
MCLK/PLLCLK
R936
PLL_DO/ST
AN4 R939
R938
RDS_DATA
REST_SW
RDS_CLK
100
VOL_JOG
LOADING
CD_RST
PLL_CE
/MUTEA
RMT_IN
PCONT
______
R951
BLKCK
SUBQ
SQCK
KEY1
KEY2
STAT
DMT
MLD
AN7
SD
BP
R942
HALT
MOTOR_H
R932 R935
PL_L
SYS6V
A9V
10K 3.3K 2.2K
R934 R933
820 2.7K
R947
1K
Q900 Q901 R946 L901
22K 3.3