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FO-77U UX-66U
CHAPTER 5. CIRCUIT DESCRIPTION
[1] Circuit description
1. General description
The compact design of the control PWB is obtained by using CONEXANT fax engine in the main control section and high density printing of surface mounting parts. Each PWB is independent according to its function as shown in Fig. 1.
3. Operational description
Operational descriptions are given below:
·
Transmission operation When a document is loaded in standby mode, the state of the document sensor is sensed via the 1 chip fax engine (FC200). If the sensor signal was on, the motor is started to bring the document into the standby position. With depression of the START key in the off-hook state, transmission takes place. Then, the procedure is sent out from the modem and the motor is rotated to move the document down to the scan line. In the scan processor, the signal scanned by the CIS is sent to the internal image processor and the AD converter to convert the analog signal into binary data. This binary data is transferred from the scan processor to the image buffer within the RAM and encoded and stored in the transmit buffer of the RAM. The data is then converted from parallel to serial form by the modem where the serial data is modulated and sent onto the line.
2. PWB configuration
TEL/LIU PWB CIS CONTROL PWB
·
Receive operation There are two ways of starting reception, manual and automatic. Depression of the START key in the off-hook mode in the case of manual receive mode, or CI signal detection by the LIU in the automatic receive mode. First, the FC200 controls the procedure signals from the modem to be ready to receive data. When the program goes into phase C, the serial data from the modem is converted to parallel form in the modem interface of the 1 chip fax engine (FC200) which is stored in the receive buffer of the RAM. The data in the receive buffer is decoded software-wise to reproduce it as binary image data in the image buffer. The data is DMA transferred to the recording processor within the FC200 which is then converted from parallel to serial form to be sent to the thermal head. The data is printed line by line by the FC200 which is assigned to control the motor rotation and strobe signal.
LCD PWB
POWER SUPPLY PWB PANEL PWB TX/RX MOTOR AC CORD
Fig. 1
1) Control PWB
The control PWB controls peripheral PWBs, mechanical parts, transmission, and performs overall control of the unit. This machine employs a 1 chip modem (FM209) which is installed on the control PWB.
·
Copy operation To make a copy on this facsimile, the COPY key is pressed when the machine is in stand-by with a document on the document table and the telephone set is in the on-hook state. First, depression of the COPY key advances the document to the scan line. Similar to the transmitting operation, the image signal from the CIS is converted to a binary signal in the DMA mode via the 1 chip fax engine (FC200) which is then sent to the image buffer of the RAM. Next, the data is transferred to the recording processor in the DMA mode to send the image data to the thermal head which is printed line by line. The copying takes place as the operation is repeated.
2) TEL/LIU PWB
This PWB controls connection of the telephone line to the unit.
3) Power supply PWB
This PWB provides voltages of +5V and +24V to the other PWBs.
4) Panel PWB
The panel PWB allows input of the operation keys.
5) LCD PWB
This PWB controls the LCD display.
51
FO-77U UX-66U
[2] Circuit description of control PWB
1. General description
Fig. 2 shows the functional blocks of the control PWB, which is composed of 4 blocks.
3) 27E010 (IC5): pin-32 DIP (ROM)
ROM of 1 Mbit equipped with software for the main CPU.
4) W24258S-70LE (IC3): pin-28 SOP (SRAM)
Line memory for the main CPU system RAM area and coding/decoding process. Used as the transmission buffer. Memory of recorded data such as daily report and auto dials. When the power is turned off, this memory is backed up by the lithium battery.
MAIN CONTROL BLOCK
(3) ROM
MODEM BLOCK
(1) FAX ENGINE (2) MODEM
(4) SRAM
Fig. 2 Control PWB functional block diagram
2. Description of each block (1) Main control block
The main control block is composed of CONEXANT 1 chip fax engine (FC200), ROM (1Mbit), SRAM (256kbit) and Modem (FM209). Devices are connected to the bus to control the whole unit.
1) FC200 (IC2) : pin-144 QFP (FAX ENGINE) 2) FM209 (IC4) : pin-128 QFP (MODEM)
The FAX ENGINE Integrated Facsimile Controllers. FC200, contains an internal 8 bit microprocessor with an external 16 Mbyte address space and dedicated circuitry optimized for facsimile image processing and facsimile machine control and monitoring.
MIRQN A[23:0] D[7:0] RDN WRN ROMCSN CSN[1:0] MCSN SYNC REGDMA WAITN RASN CASN[1:0] DWRN TONE
GPIO[0] GPIO[1]/SASTXD GPIO[2]/SASRXD GPIO[3]/SASCLK GPIO[4]/CPCIN GPIO[5]/SSCLK2 GPIO[6]/SSTXD2 GPIO[7]/SSRXD2 GPIO[8]/FWRN GPIO[9]/FRDN GPIO[10]/SSSTAT2 GPIO[11]/BE/SERINP GPIO[12]/CS2N GPIO[13]/CS3N GPIO[14]/CS4N GPIO[15]/CS5N GPIO[16]/IRQ8 GPIO[17]/IRQ5N GPIO[18]/IRQ9N GPIO[19]/RDY/SEROUT GPIO[20]/ALTTONE SM[3:0]/GPO[7:4] PM[3:0]/GPO[3:0]
MC24 CPU CONTROL IF MC24 MEGACELL(8BIT DATA,24BIT ADDRESS) WATCHDOG TIMER REAL TIME CLOCK CRYSTAL OSCILLATOR BATTERY BACK-UP CIRCUIT INTERRUPT CONTROLLER
WRPROTN SYSCLK TSTCLK DEBUGN RESETN XIN XOUT PWRDWNN BATRSTN
BUS INTERFACE
EXTERNAL CPU BUS
DRAM CONTROL INTERNAL & EXTERNAL BUS CONTROL INTERNAL & EXTERNAL DECODE DMA CONTROLLER
CPU BUS
OPERATOR PANEL IF 32 KEYS 8 LEDS LCD MODULE MOTOR POWER CONTROL RINGER SYNC SERIF 1
SEE "OPIF OUTPUTS" BELOW
GENERAL I/O TONE/ALTTONE GPIO CALLING PARTY CONTROL AUTOBAUD SYNC-ASYNC SASIF SYNC SERIF 2 FLASH MEMORY IF AUTOBAUD
INTERNAL CPU BUS
SEE "OPIF INPUTS" BELOW
SCANNER CONTROL & VIDEO PROCESSING 8-BIT PADC CCD/CIS SCANNER 5 ms,A4/B4 LINES SHADING CORRECTION(1:1,1:8) DITHERING MULTILEVEL B4-A4 REDUCTION ERROR DIFFUSION MTF
BI-LEVEL RESOLUTION CONVERSION PROGRAMMABLE REDUCTION & EXPANSION
T.4/T.6 CODEC MH,MR,MMR HARDWARE,ALTERNATE COMPRESSION & DECOMPRESSION
THERMAL PRINTER IF 5 ms LINE TIME A4/B4 LINES TPH ADC 4 STROBE TPH LATCHLESS TPH EXTEMAL DMA I/F
2.6kBYTE VIDEO RAM
DMA BUS
THADIN PCLK PDAT PLAT STRB[3:0] STRBPOL
START CLK1 CLK1N CLK2 VIDCTL0/FCS1N VIDCTL1/FCS2N
+VREF VREF VIN
OPIF INPUTS
OPIF OUTPUTS LEDCTL/GPO[16] LCDCS/GPO[17] OPO[0]/GPO[8]/SINPWR CTRL OPO[1]/GPO[9]/PMPWR CTRL OPO[2]/GPO[10]/RINGER OPO[3]/GPO[11] OPO[4]/GPO[12]/SSTXD1 OPO[5]/GPO[13] OPO[6]/GPO[14] OPO[7]/GPO[15]
PWR/GND
TEST
OPI[0]/GPIO[21]/SSRXD1 OPI[1]/GPIO[22]/SSSTAT1 OPI[2]/GPIO[23]/SSCLK1 OPI[3]/GPIO[24]
Fig. 3
52
FO-77U UX-66U
FC200 (IC2) Terminal descriptions
Pin Name Pin No. I/O Input Type HU H - TU TU - - - - - - - - - - - - Output Type Pin Description (Note: Active low signals have an "n" pin name ending.)
MIRQn SYSCLK TSTCLK A[23:0] [15:20][22:27] D[7:0] [141:144] RDn WRn ROMCSn CS1n CS0n MCSn SYNC REGDMA WAITn RASn CAS[1:0]n DWRn DEBUGn RESETn TEST XIN XOUT PWRDWNn BATRSTn WRPROTn
135 133 130 [1:6][8:13] [136:139] 128 127 120 122 57 121 126 124 125 113 [111:112] 109 129 131 58 59 60 62 61 110
I I O O I/O O O O O O O O O O O O O I I/O I I O I I O
CPU Control Interface - Modem interrupt, active low. (Hysteresis In, Internal Pullup.) - System clock. (Hysteresis In.) 123XT Test clock. Bus Control Interface 123XT Address bus (24-bit). 123XT Data bus (8-bit).
START CLK1 CLK1n CLK2 FCS1n/VIDCTL0 FCS2n/VIDCTL1 PCLK/DMAACK PDAT PLAT STRB[3:0] STRBPOL/DMAREQ OPO[0]/GPO[8]/ SMPWRCTRL OPO[1]/GPO[9]/ PMPWRCTRL OPO[2]/GPO[10]/ RINGER OPO[3]/GPO[11] OPO[4]/GPO[12]/ SSTXD1 OPO[5]/GPO[13] OPO[6]/GPO[14] OPO[7]/GPO[15] OPI[0]/GPIO[21]/ SSRXD1 OPI[1]/GPIO[22]/ SSSTAT1
101 100 99 98 96 97 29 30 31 [33:36] 37 47 46 44 43 42 40 39 38 52 51
O O O O O O O O O O I O O O O O O O O I/O I/O
123XT Read strobe. 123XT Write strobe. 123XT ROM chip select. 123XT I/O chip select. 123XT SRAM chip select. (Battery powered.) 123XT Modem chip select. 123XT Indicates CPU op code fetch cycle (active high). 123XT Indicates REGSEL cycle and DMA cycle. 123XT Indicates current TSTCLK cycle is a wait state or a halt state. 123XT DRAM row address select. (Battery powered.) 123XT DRAM column address select. (Battery powered.) 123XT DRAM write. (Battery powered.) Prime Power Reset Logic and Test HU - External non-maskable input (NMI). HU 2XO FC100/FC200 Reset. C - Sets Test mode (Battery powered). Battery Power Control and Reset Logic OSC - Crystal oscillator input pin. - OSC Crystal oscillator output pin. H - Used by external system to indicate -to FC200 - loss of prime power. (Results in NMI) H - Battery power reset input. (Battery powered.) Write protect during loss of VDD power. - 1XC NOTE:The functional logic is powered by battery power, but the output drive is powered by DRAM battery power. Scanner Interface - 2XS Scanner shift gate control. - 2XS Scanner clock. - 2XS Scanner clock-inverted. - 2XS Scanner reset gate control (or clock for CIS scanner). - 2XT Flash memory chip select or Video Control signal. - 2XT Flash memory chip select or Video Control signal. Printer Interface - 3XC Thermal Print Head (TPH) clock, or external DMAACK. - 2XP Serial printing data (to TPH). - 3XP TPH data latch. - 1XP Strobe signals for the TPH. C - Sets strobe polarity, active high/low or external DMA request. Operator Panel Interface - 2XL Keyboard/LED strobe [0] or GPO[8] or Scan Motor Power Control - - - - - - - HU HU 2XL 2XCT 2XL 2XL 2XL 2XL 2XL 2XC 2XC Keyboard/LED strobe [1] or GPO[9] or Print Motor Power Control Keyboard/LED strobe [2] or GPO[10] or RINGER Keyboard/LED strobe [3] or GPO[11] Keyboard/LED strobe [4] or GPO[12] or SSTXD1 (for SSIF1) Keyboard/LED strobe [5] or GPO[13] Keyboard/LED strobe [6] or GPO[14] Keyboard/LED strobe [7] or GPO[15] (Pullup, Hysteresis In) Keyboard return [0] or GPIO[21] or SSRXD1 (for SSIF1) (Pullup, Hysteresis In) Keyboard return [1] or GPIO[22] or SSSTAT1 (for SSIF1)
53
FO-77U UX-66U
FC200 (IC2) Terminal descriptions
Pin Name Pin No. I/O Input Type HU Output Type Pin Description
OPI[2]/GPIO[23]/ SSCLK1 OPI[3]/GPIO[24] LEDCTL LCDCS GPIO[0] GPIO[1]/SASTXD GPIO[2]/SASRXD GPIO[3]/SASCLK GPIO[4]/CPCIN GPIO[5]/SSCLK2 GPIO[6]/SSTXD2 GPIO[7]/SSRXD2 GPIO[8]/FWRn GPIO[9]/FRDn GPIO[10]/SSSTAT2 GPIO[11]/BE/ SERINP GPIO[12]/CS[2]n GPIO[13]/CS[3]n GPIO[14]/CS[4]n GPIO[15]/CS[5]n GPIO[16]/IRQ[8] GPIO[17] GPIO[18]/IRQ[9]n GPIO[19]/RDY/ SEROUT GPIO[20]/ALTTONE SM[3:0]/GPO[7:4] PM[3:0]/GPO[3:0] TONE -Vref/CLREF ADXG ADGA ADVA ADGD +Vref VIN THAD1 VSS(12)
50 49 55 54 94 93 92 91 90 89 87 86 85 84 83 82 80 79 78 77 76 75 74 73 107 [103:106] [115:118] 119 66 68 69 70 72 71 67 65 7,21,28,45, 53,56,64,88, 95,108,132, 134 14,32,41,48, 81,102,123, 140 63 114
I/O I/O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O I I
I I I
Operator Panel Interface 2XC (Pullup, Hysteresis In) Keyboard return [2] or GPIO[23] or SSCLK1 (for SSIF1) HU 2XC (Pullup, Hysteresis In) Keyboard return [3] or GPIO[24] - 4XC Indicates outputs OPO[7:0] are for LEDs. - 1XC LCD chip select. General Purpose I/O H 2XC (Hysteresis In) GPIO[0]. H 2XC (Hysteresis In) GPIO[1] or SASTXD (for SERIF). H 2XC (Hysteresis In) GPIO[2] or SASRXD (for SERIF). H 2XC (Hysteresis In) GPIO[3] or SASCLK (for SERIF). H 2XC (Hysteresis In) GPIO[4] or Calling Party Control Input. H 2XC (Hysteresis In) GPIO[5] or SSCLK2 (for SSIF2). H 2XC (Hysteresis In) GPIO[6] or SSTXD2 (for SSIF2). H 2XC (Hysteresis In) GPIO[7] or SSRXD2 (for SSIF2). H 2XC (Hysteresis In) GPIO[8] or flash write enable signal for NAND-type flash memory. H 2XC (Hysteresis In) GPIO[9] or flash read enable signal for NAND-type flash memory. H 2XC (Hysteresis In) GPIO[10] or SSSTAT2 (for SSIF2). H 1XC (Hysteresis In) GPIO[11] or bus enable or serial port data input for autobaud detection. H 2XC (Hysteresis In) GPIO[12] or I/O chip select [2]. H 2XC (Hysteresis In) GPIO[13] or I/O chip select [3]. H 2XC (Hysteresis In) GPIO[14] or I/O chip select [4]. H 2XC (Hysteresis In) GPIO[15] or I/O chip select [5]. H 1XC (Hysteresis In) GPIO[16] or external interrupt 8. H 1XC (Hysteresis In) GPIO[17]. H 1XC (Hysteresis In) GPIO[18] or external interrupt 9. H 1XC (Hysteresis In) GPIO[19] or ready signal or Serial port data output for autobaud detection. H 1XC (Hysteresis In) GPIO[20] or ALTTONE. Miscellaneous - 1XC Programmable: scan motor control pins or GPO pins. - 1XC Programmable: print motor control pins or GPO pins. - 1XC Tone output signal. Power, Reference Voltages, Ground -VR - Negative Reference Voltage for Video A/D or Reference Voltage for the Clamp Circuit. VXG - A/D Internal GND. (NOTE: This pin requires an external 0.22µF decoupling capacitor to ADGA.) VADG A/D Analog Ground VADV A/D Analog Power VADG A/D Digital Ground +VR Positive Reference Voltage for Video A/D. VA - Analog Video A/D input. TA - Analog Thermal A/D input. Power and Ground Digital Ground
VDD(8)
Digital Power
VBAT VDRAM
Battery Power DRAM Battery Power
54
FO-77U UX-66U (2) Panel control block
The following controls are performed by the FC200.
· ·
Operation panel key scanning Operation panel LCD display
(3) Mechanism/recording control block ·
Recording control block diagram (1)
PANEL/LCD PWB
OPERATOR PANEL, KEYPAD, LEDS & LCD
OPO[7:0]* OPI[3:0]* LEDCTL* LCDCS*
TEST BATRSTN RESETN
TELEPHONE LINE
TONE/ALTTONE TSTCLK REGDMA WAITN SYNC PWRDWNN RXIN TXOUT SPEAKER MICROPHONE CIRCUIT
MIC SPKR
THERMAL HEAD
PRINTER DATA CONTROI & SENSORS
STRB[3:0] STRBPOL THADI PDAT PCLK PLAT
LINE INTERFACE
TXA RXA
ANALOG SWITCH PM[3:0]* MOTOR PRINTER & SCANNER MOTOR DRIVERS SM[3:0]* SYSCLK MIRON MCSN EXTENDED FACSIMILE CONTROLLER A[4:0] D[7:0] RDN WRN MONOFAX FACSIMILE MODEM XIN XOUT RTC CRYSTAL
TXA2 TXA1
RIN SPKRLO SPKRHI
SCANNER CONTROLS & SENSORS CIS SCANNER VIDEO PREPROCESSING
START CLK2 CLK1 CLK1N VIDCTL[1:0]
RIN SPKR RXDAT TXDAT RMODE TMODE CLKIN SLEEPN
EXTERNAL BUS
XIA
VIN +VREF VREF A[23:0] D[7:0] RDN WRN ROMSCN CS[5:0]N* WRPROTN FRDN* FRWN* FCLE* FCS[0:2] DEBUGN VDD VDRAM VBAT VSS
GPIO
GPIO
SYNC PORTS (2) (SSIF)
SSCLK[2:1]* SSTXD[2:1]* SSRXD[2:1]* SSSTAT[2:1]*
CAS[0,1]N,RASN,DWRN D[7:0]
DRAM (OPTION)
GENERAL PURPOSE I/O
GPIO
FLASH MEMORY
SYNC/ASYNC SERIAL PORT
SASCLK SASTXD SASRXD
NOTES:*ALTERNATIVE GPO,GPI OR GPIO LINES SPEAKERPHONE ONLY VOICE OR SPEAKERPHONE
Fig. 4
55
FO-77U UX-66U (4) Modem (FM209) block
INTRODUCTION
The CONEXANT FM209 MONOFAX modem is a synchronous 9600 bits per second (bps) half-duplex modem with error detection and DTMF reception. It has low power consumption and requires a single +5V and +3.3V DC power supply. The modem is housed in a single VLSI device package. The modem can operate over the public switched telephone network (PSTN) through line terminations provided by a data access arrangement (DAA). The FM209 is designed for use in Group 3 facsimile machines. The modem satisfies the requirements specified in CCITT recommendations V.29, V.27 ter, V.21 Channel 2 and T.4, and meets the binary signaling requirements of T.30. The modem can operate at 9600, 7200, 4800, 2400, or 300 bps, and also includes the V.27 ter short training sequence option. The modem can also perform HDLC framing according to T.30 at 9600, 7200, 4800, 2400, or 300 bps. The modem features a programmable DTMF receiver and three programmable tone detectors which operate concurrently with the V.21 channel 2 receiver. The voice mode allows the host computer to efficiently transmit and receive audio signals and messages. The modem is available in either a 128-pin plastic quad flat pack (TQFP). General purpose input/output (GPIO) pins are available for host as signment in the 128-pin TQFP. The modem's small size, single voltage supply, and low power consumption allow the design of compact system enclosures for use in both office and home environments. MONOFAX is a registered trademark of CONEXANT.
TXD RXD OFFHOOK TALK RINGD LINEOUT LINEIN
FEATURES
·
Group 3 facsimile transmission/reception ITU-T V.29, V.27 ter, T.30, V.21 Channel 2, T.4 ITU-T V.17 and V.27 ter short train HDLC framing at all speeds Receive dynamic range: 0 dBm to -43 dBm Automatic adaptive equalization Fixed and programmable digital compromise equalization DTMF detect and tone detect ITU-T V.21 Channel 2 FSK 7E Flag Detect Ring detector Programmable transmits level Programmable single/dual tone transmission Full-duplex modes: TX = 75 bps. RX = 1200 bps TX = 1200 bps. RX = 75 bps Half-duplex mode: TX = RX = 1200 bps Serial and parallel data modes Programmable parallel data mode 5, 6, 7 or 8 data bits 1 or 2 Stop bits Mark, Space, Even, or Odd Parity Break function Transmitter squelch Compromise equalizer
·
V.23 and Type I Caller ID -
USART (OPTIONAL)
DCLK RTS# CTS# RLSD#
DAA
TELEPHONE LINE
-
· · ·
Programmable interface memory interrupt Eight General Purpose Input (GPI) and eight General Purpose Output (GPO) pins for host assignment DTE interface: two alternate ports Selectable microprocessor bus (6500 or 8085) ITU-T V.24 (EIA/TIA-232-E compatible) interface
SPKRP SPKRM READ# WRITE# DATA BUS
SPEAKER DRIVER (OPTIONAL)
HOST PROCESSOR (DTE)
FM209 MONOFAX MODEM
ADDR BUS
DECODER
CS# RESET# IRQ1# IRQ2# EYEXY XTLI EYECLK EYESYNC
· · ·
EYE PATTERN GENERATOR (OPTIONAL)
TTL and CMOS compatible 3.3V/5V operation Power consumption Operating Mode: 200 mW (Basic), 275 mW (-V option). 300 mW (-VS option) Sleep Mode: 1 ma (Basic. -V option and -VS option) 128-pin TQFP (thin quad flat pack)
CRYSTAL
XTLO
·
Packaging -
+3.3V
GND
POWER SUPPLY
Fig. 5
+5V
56
FO-77U UX-66U FM209 (IC4) Hardware Interface Signals
Pin Signals 128-Pin TQFP Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 Signal Name SR4IN/RESERVED SR3OUT/RESERVED EYESYNC EYECLK RXD SR1IO NC EYEXY SR4OUT VDD1 RLSD# DCLK EN85# GPI0 RTS# DGND1 TXD SA1CLK RS4 RS3 RS2 RS1 RS0 YCLK IACLK IA1CLK CTRLSIN S/NC RESERVED/NC SOUT S/NC SIN S/NC FSYNC S/NC IARESET S#/NC AGND1 LINEIN S/NC MICP S/NC MICM S/NC MICBIAS S/NC NC NC VREF S/NC VC S/NC VAA S/NC LINEOUT S/NC NC AGND2 SPKRP S/NC SPKRM S/NC AVDD S/NC RESERVED/NC ICLK S/NC MCLK P CTRLSIN P RESERVED SOUT P SIN P FSYNC P IARESET P# AGND3 NC LINEIN P MICP P MICM P MICBIAS P NC NC VREF P VC P VAA P LINEOUT P AGND4 SPKRP P I/O Type MI MI OA OA OA MI -- OA MI PWR OB OB IA IA IA GND IA MI IB IB IB IB IB I MI MI MI MI MI MI MI MI GND I I I O -- -- MI MI PWR O -- GND O O PWR MI MI MI MI MI MI MI MI MI GND -- I I I O -- NC MI MI PWR O GND O Pin Description Modem Interconnect Modem Interconnect Eye Pattern Circuit Eye Pattern Circuit DTE serial interface Modem Interconnect No Connection Eye Pattern Circuit Modem Interconnect 3.3V Digital Supply for DSP DTE Serial Interface DTE Serial Interface Host Parallel Interface Host Parallel Interface DTE Serial Interface DSP Digital Ground DTE Serial Interface Modem Interconnect Host Parallel Interface Host Parallel Interface Host Parallel Interface Host Parallel Interface Host Parallel Interface Modem Interconnect Modem Interconnect Modem Interconnect Modem Interconnect Modem Interconnect Modem Interconnect Modem Interconnect Modem Interconnect Modem Interconnect IA Analog Ground Line Interface Microphone Input Microphone Input Microphone Bias Output No Connection No Connection Modem Interconnect Modem Interconnect 5V IA Analog power Line Interface No Connection IA Analog Ground Speaker Interface Output Speaker Interface Output 5V IA Digital power Modem Interconnect Modem Interconnect Modem Interconnect Modem Interconnect Modem Interconnect Modem Interconnect Modem Interconnect Modem Interconnect Modem Interconnect IA Analog Ground No Connection Line Interface Microphone Input Microphone Input Microphone Bias Output No Connection No Connection Modem Interconnect Modem Interconnect 5V Analog Supply for IA Line Interface IA Analog Ground Speaker Interface Output
57
FO-77U UX-66U FM209 (IC4) Hardware Interface Signals
Pin Signals 128-Pin TQFP Pin No. 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Signal Name SPKRM P AVDD P NC ICLK P MCLK S/NC VDD2 D7 D6 D5 D4 D3 D2 DGND2 VDD3 D1 DGND3 D0 CSBR# WRITE# CS# READ# GPI2 GPI3 GPI4 GPI5 GPI6 GPI7 GPO7 VDD4 GPO6 GPO5 RESERVED GPO4 GPO3 DGND4 CTS# IRQ1# GPO2 GPO1 GPO0 VDD5 VGG DGND5 RESET# XTALI XTALO RESERVED XCLK GPI1 IRQ2# SR3IN RESERVED RESERVED DGND6 DVAA AGND5 RESERVED I/O Type O PWR -- MI MI PWR IB/OC IB/OC IB/OC IB/OC IB/OC IB/OC GND PWR IB/OC GND IB/OC IB IB IB IB IA IA IA IA IA IA OC PWR OC OC MI OC OC GND OB OB OC OC OC PWR PWR GND IB I O MI OB IA OA MI MI MI GND PWR GND MI Pin Description Speaker Interface Output 5V Digital power for IA No Connection Modem Interconnect Modem Interconnect 3.3V Digital Supply for DSP Host Parallel Interface Host Parallel Interface Host Parallel Interface Host Parallel Interface Host Parallel Interface Host Parallel Interface DSP Digital Ground 3.3V Digital Supply for DSP Host Parallel Interface DSP Digital Ground Host Parallel Interface Host Parallel Interface Host Parallel Interface Host Parallel Interface Host Parallel Interface General purpose input General purpose input General purpose input General purpose input General purpose input General purpose input General purpose output 3.3V DSP Digital Power General purpose output General purpose output Modem Interconnect General purpose output General purpose output DSP Digital Ground DTE Serial Interface Interrupt request General purpose output General purpose output GPO0 (IA reset) 3.3V DSP Digital Power 5V DSP Digital DSP Digital Ground External reset Crystal in Crystal out Modem Interconnect X clock output General purpose input Interrupt request Modem Interconnect Modem Interconnect Modem Interconnect DSP Digital Ground 3.3V DSP analog power DSP Analog Ground Modem Interconnect
Notes: I/O types: MI = Modem interconnect. IA, IB, = digital input OA, OB, OC = digital output I = analog input O = analog output P Signals: Primary IA S Signals: Secondary IA Reserved = No external connection allowed.
58
FO-77U UX-66U
[3] Circuit description of TEL/LIU PWB
(1) TEL/LIU block operational description
1) Block diagram
TEL/LIU PWB CONTROL PWB SP OUT ENABLE SPKRP-P
RTLOOP
TXOUT L1 C L2 B CI CML M
(0:1) (1:0) (0:0) (1:1)
MIC ENABLE SIN DAC DAC GAIN 0,6dB
SP DRIVER
RXIN
MICP
MIC GAIN MIC IN LPF 0,20,25,30dB
MIC 1 ENABLE 0
ADC TELIN HANDSET RX TELMUTE TX TELOUT LINEOUT LINEOUT ENABLE SPEAKER BIT7 DAC GAIN TXRX LOOP BIT6 BIT5 MIC GAIN BIT4 BIT3 BIT2 BIT1 BIT0 L/O E SPKR E ADC L/I E MIC E GAIN LINEOUT RXTXLOOP MICBIAS ATTENUATION SEL LINE SEL BZOUT CML SPMUTE SPMUTE MUTE,0, 6,12dB RCV VOL LINE DRIVER LNINSEL (0:0) (1:1) (1:0) LINEIN LINE IN LPF LINE IN 1 ENABLE 0
SOUT
ADC GAIN 0,4dB
RHS RANK DRSNS TXMUTE TELMUTE IA-RESET
MODEM FM209
IACR1 IACR2 IACR3
CUTI HS CI CSWI PESNS FRSNS ORGSNS PSNS VREFCONT MDMRST LEDON
FAX ENGINE FC200
RCVOL VTHON
Fig. 6
2) Circuit description
The TEL/LIU PWB is composed of the following 7 blocks. 1. Speech circuit section 2. Dial transmission section 3. Speaker amplifier section 4. Ringer circuit section 5. Externally connected TEL OFF HOOK detection circuit 6. CI detection circuit 7. Signal/DTMF transmission level
3) Block description
1. Speech circuit section
·
The receiver volume is an electronic volume type, this model is switched in 2 steps.
2. Dial transmission section
· · · ·
D.P. transmission: The CML relay is turned on and off for control in the DP calling system. (Refer to the attached sheet.) DTMF transmission: It is formed in the modem, and is output.
3. Speaker amplifier section Ringer volume : It is controlled by the combination of the attenuator value of the LINE DRIVER in the modem and the ringer sending level sent from the modem. Speaker volume: It is controlled by the attenuator value of the LINE DRIVER in the modem.
4. Ringer circuit section
·
The ringer sound is formed in the tone of modem when CI signal is detected. The amplifier circuit drives the speaker of the main body.
59
FO-77U UX-66U
5. Externally connected TEL OFF HOOK detection circuit section 4) Signal selection The following signals are used to control the transmission line of TEL/ FAX signal. For details, refer to the signal selector matrix table. [Control signals from output port] Signal Name CML Description
·
The circuit current detection is turned on together with OFF HOOK of main body or OFF HOOK of externally connected TEL. ON of CML OFF (HS=L) is judged as OFF HOOK of externally connected TEL.
6. CI detection circuit
·
CI is detected by the photocoupler which is integrated in series in the primary side TEL circuit well proven in the existing unit.
Line connecting relay and DP generating relay (The circuit is located H: Line make in the TEL/LIU PWB.) L: Line break SP MUTE
(The circuit is located in the TEL/LIU PWB.)
7. Signal/DTMF transmission level
· ·
Signal transmission level setting: ATT -10 dB Circuit output: -12 dBm. DTMF transmission level setting: HF -3.5 dBm Thus, set the level. LF -5.0 dBm
Speaker tone mute control signal H: Muting (Power down mode) L: Muting cancel (Normal operation) Handset reception mute control signal H: Muting L: Muting cancel Handset receiver volume control signal
TEL MUTE
RCVOL
(The circuit is located in the control PWB.)
Volume High RCVOL L
Low
DTMF sending and LOW
H
H
Note: The DTMF sending listed above is DTMF signal sending in the handset OFF-HOOK mode.
VOLUME SETTING Receiver volume setting Low High Fixed Fixed Low Middle High Low Middle High Low Middle High
LINEOUT A (HIGH) (LOW)
RCVOL 1 0 1
DTMF Transmission volume setting (Receiver) Key buzzer volume setting Speaker volume setting
Ringer volume setting
DTMF speaker volume setting
1 1 0 1 1 0 1 1 0
1 0 1 1 0 1 1 0 1
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FO-77U UX-66U
[Signals for status recognition according to input signals] Signal Name RHS CI [Other signals] Signal Name TEL IN TEL OUT SPOUT TXOUT RXIN Function Receiving signal from line or modem Transfer signal to line Speaker output signal Transmission (DTMF) analog signal output from modem Reception (DTMF, others) analog signal input into modem Function H:The handset is in the on-hook state. L: The handset is in the off-hook state. Incoming call (CI) detection signal NO 1 2 3 4 5 6 Signal Name (CNLIUA) TELOUT TELIN TELMUTE CI HS RHS NO 7 8 9 10 11 12 Signal Name (CNLIUA) RXIN TXOUT CML +5V DG +24V
(Example: TEL speaking)
TEL/LIU PWB
CONTROL PWB
SP OUT ENABLE SPKRP-P
RTLOOP
TXOUT L1 C L2 B CI CML M
(0:1) (1:0) (0:0) (1:1)
MIC ENABLE SIN DAC DAC GAIN 0,6dB
SP DRIVER
RXIN
MICP
MIC GAIN MIC IN LPF 0,20,25,30dB
MIC 1 ENABLE 0
ADC TELIN HANDSET RX TELMUTE TX TELOUT LINEOUT LINEOUT ENABLE SPEAKER IACR1 IACR2 IACR3 BIT7 DAC GAIN TXRX LOOP BIT6 BIT5 MIC GAIN BIT4 BIT3 BIT2 BIT1 BIT0 L/O E SPKR E ADC L/I E MIC E GAIN LINEOUT RXTXLOOP MICBIAS ATTENUATION SEL LINE SEL SPMUTE BZOUT CML SPMUTE TEL SPEAKING: FAX SENDING/RECEIVING: MUTE,0, 6,12dB RCV VOL LINE DRIVER LNINSEL (0:0) (1:1) (1:0) LINEIN LINE IN LPF LINE IN 1 ENABLE 0
SOUT
ADC GAIN 0,4dB
RHS RANK DRSNS TXMUTE TELMUTE IA-RESET
MODEM FM209
CUTI HS CI FAX ENGINE FC200 CSWI PESNS FRSNS ORGSNS PSNS VREFCONT MDMRST LEDON
RCVOL VTHON
Fig. 7
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FO-77U UX-66U
[4] Circuit description of power supply PWB
1. Block diagram
F1 2.5A/250V AC IN Noise Filter Circuit Rectifying Smoothing Circuit Switching Circuit (RCC system)
Stabilizer Circuit
+5V +24V
F2 4A/72V
Photo Coupler
Fig. 8
2-1. Noise filter circuit
The input noise filter section is composed of L and C, which reduces normal mode noise from the AC line and common mode noise to the AC line.
The overcurrent protection is performed by bringing Q1 to OFF state through detection of voltage increase in the auxiliary winding of T1 by R5 and R7.
2-4. +5V circuit
Each DC voltage supplied by rectifying the output of transformer T1 with diode D9 is stabilized.
2-2. Rectifying/smoothing circuit
The AC input voltage is rectified by diode D1, 2, 3, 4 and smoothed by capacitor C5 to supply DC voltage to the switching circuit section. Power thermistor TH1 suppresses inrush current at power switch-on.
2-3. Switching circuit
This circuit employs the self excited ringing choke convertor (RCC) system. In this system, the DC voltage supplied from the rectifying/smoothing section is converted into high frequency pulses by ON/OFF repetition of MOS FET Q1. Energy is charged in the primary winding of T1 during ON period of Q1, and discharged to the secondary winding during OFF period. The output voltage is controlled by adjusting ON period of Q1 which changes charge time of C9 through operation of photo-coupler PC1 from +24V output.
[5] Circuit description of CIS unit
1. CIS (Contact Image Sensor)
Cis is an image sensor which puts the original paper in close contact with the full-size sensor for scanning, being a monochromatic type with the pixel number of 1,728 dots and the main scanning density of 8 dots/mm. It is composed of sensor, rod lens, LED light source, light-conductive plate, control circuit and so on, and the reading line and focus are previously adjusted as the unit. Due to the full-size sensor, the focus distance is so short that the set is changed from the light weight type to the compact type.
øT 1.984µs CISCLK
2. Waveforms
The following clock is supplied from FC200 of the control board, and VO is output.
5ms Approx.5V 0V
VO
2V(TYP) (White original paper)
Fig. 9
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