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A B C D E
Compal Confidential
Model Name : V5WE2/T2 (EA/EG)
File Name : LA-9532P
1 1
Compal Confidential
2 2
EA50 UMA M/B Schematics Document
Intel Shark Bay ULT (Hasswell + Lynx PointLP)
3 2013-04-18 3
REV:1.0
ZZZ
Part Number Description
4 DAZ0VR00200 PCB V5WE2 LA-9532P LS-9531P/9532P/9533P 4
V5WE2_PCB
ZZZ1
Security Classification Compal Secret Data Compal Electronics, Inc.
2012/07/10 2013/07/10 Title
HDMI_ROYALTY
Issued Date Deciphered Date Cover Page
ROYALTY HDMI W/LOGO+HDCP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RO0000003HM AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
45@ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V5WE2 M/B LA-9532P Schematic
Date: Thursday, April 18, 2013 Sheet 1 of 42
A B C D E
A B C D E
CRT Conn. eDP & LVDS
Fan Control
page 21 Co-lay Conn. page 30
page 18
DP to VGA HDMI Conn. eDP to LVDS
1
ITE IT6511FN page 19
RTD2132R 1
page 17 204pin DDR3L-SO-DIMM X1
page 20 Intel Haswell ULT BANK 0, 1, 2, 3 page 15
DP x 2 lanes HDMI x 4 lanes eDP Memory BUS
2.7GT/s 2.97GT/s Dual Channel
DDI
Haswell ULT
Processor 1.35V DDR3L 1333/1600 204pin DDR3L-SO-DIMM X1
BANK 4, 5, 6, 7 page 16
MINI Card OPI
WLAN
USB port 8 page 24
PCIe 2.0 USB 3.0 USB 2.0 CMOS Touch
5GT/s conn x1 conn x2 Camera Module
2
port 4
Lynx Point - LP USB port 0 USB/B (port 1,2) USB port 7 USB port 6
2
Flexible IO
page 26 page 26 page 18 page 18
PCH
PCIe 2.0 48MHz
5GT/s USBx8
SATA3.0 SATA3.0
port 3 6.0 Gb/s 6.0 Gb/s
port 0 port 1 HD Audio 3.3V 24MHz
LAN(GbE) SATA HDD SATA CDROM
Boardcom Conn. Conn. HDA Codec
57786 page 1168pin BGA ALC3225
22 page 25 page 25
page 04~14 page 29
SPI
3
Card Reader LPC BUS 3
2 in 1 SPI ROM x2
(SD/MMC) CLK=24MHz Int. Speaker Int. MIC Combo Jack
page 23 page 07
ENE page 29 page 29 page 29
RTC CKT. Sub Board KB9012/KB932
page 27
page 06
LS-9531P
PWR/B
Power On/Off CKT. page 26 Touch Pad Int.KBD
page 28 page 28
page 28
LS-9532P
USB/B (port 1,2)
DC/DC Interface CKT. page 26
page 31 EC ROM x1
4 4
LS-9533P (KB932) 27
page
Power Circuit DC/DC BATT/B
page 33 Security Classification Compal Secret Data Compal Electronics, Inc.
page 32~40
2012/07/10 2013/07/10 Title
Issued Date Deciphered Date Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V5WE2 M/B LA-9532P Schematic
Date: Monday, April 08, 2013 Sheet 2 of 42
A B C D E
A B C D E
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
BATT+ Battery power supply (12.6V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
1 1
+CPU_CORE Core voltage for CPU ON OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+0.675VS +0.675VSP to +0.675VS switched power rail for DDR terminator ON OFF OFF
+1.35V +1.35VP to +1.35V power rail for DDRIIIL ON ON OFF
+1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF
Board ID / SKU ID Table for AD channel
+1.8VS +3VS to 1.8V switched power rail to CPU ON OFF OFF
+3VALW +3VALW always on power rail ON ON ON*
Vcc 3.3V +/- 5%
+3VLP B+ to +3VLP power rail for suspend power ON ON ON
Ra/Rc/Re 100K +/- 5%
Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+3VS +3VALW to +3VS power rail ON OFF OFF
+5VALW +5VALWP to +5VALW power rail ON ON ON*
0 0 0 V 0 V 0 V
+5VS +5VALW to +5VS switched power rail ON OFF OFF
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+VSB +VSBP to +VSB always on power rail for sequence control ON ON ON*
2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+RTCVCC RTC power ON ON ON
3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+1.05VS_VTT +1.05VSP to +1.05VS_VTT switched power rail for cpu ON OFF OFF
4 56K +/- 5% 1.036 V 1.185 V 1.264 V
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V
2 2
BOARD ID Table
Board ID PCB Revision BTO Option Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
0 0.1 BTO Item BOM Structure
1 0.2 EC 9012 9012@
EC SM Bus1 address EC SM Bus2 address 2 0.3 EC 940 940@
3 0.4 Unpop @
Device Address Device Address 4 1.0 TPM Circuit TPM@
Smart Battery 0001 011X b On Board Thermal Senser 1001_101xb 5 eDP mode EDP@
PCH SM Bus address 6 eDP to LVDS TL@
7 Connector CONN@
Device Address GSensor GSEN@
ChannelA DIMM0 A0 1010 000X JDIMM1(SPD)
USB Port Table XDP (Debug Port) XDP@
BOM config KB Backlight BL@
USB 3.0 Port
Debug Only DEG@
3
1 USB Port(Left 3.0)
3
PCB P/N DA60000XR00 : PCB 0VR LA-9532P REV0 M/B MEC requirement EMC@
2
EVT BOM config 9012@ ; AMIC@ ; CHR@ ; BL@ ; EMC@ ; AOAC@ 11/1 Del XDP@ XHCI MEC requirement unpop XEMC@
3
DVT BOM config 9012@ ; BL@ ; EMC@ ; EDP@ (L01~L04) GPU_Select VGA@
4
9012@ ; BL@ ; EMC@ ; TL@ (L05) reserve 3,5V MOS 35V@
PVT BOM config 9012@ ; EMC@ ; EDP@ ; 1ROM@ ; IOAC@ 3 External BIOS 8M Solution 1ROM@
USB 2.0 USB 1.1 Port
PreMP BOM config 9012@ ; EMC@ ; EDP@ ; 1ROM@ ; IOAC@ USB Port BIOS 4+2M Solution 2ROM@
0 USB Port(Left 3.0) IOAC Function IOAC@
UHCI0
1 USB Port(Right 2.0) Touch screen Function TS@
43 level BOM table 2 USB Port(Right 2.0)
UHCI1
3
43 Level Description EHCI1
4 Mini Card(WLAN)
4319LWBOL01 SMT MB A9532 V5WE2 UMA I7 QDA7 HDMI UHCI2
5
4319LWBOL02 SMT MB A9532 V5WE2 UMA I5 QDJB HDMI
6 Touch Screen
4319LWBOL03 SMT MB A9532 V5WE2 UMA I5 QDJ7 HDMI UHCI3
7 Camera
4319LWBOL04 SMT MB A9532 V5WE2 UMA I5 QDJ9 HDMI
4319LWBOL05 SMT MB A9532 V5WE2 UMA I5 QDJB LVDS HDMI
4 4
4319LWBOL06 SMT MB A9532 V5WE2 UMA WO/CPU HDMI
4319LWBOL07 SMT MB A9532 V5WE2 UMA I5 QEA4 HDMI
4319LWBOL08 SMT MB A9532 V5WE2 UMA I5-4200 HDMI
4319LWBOL09 SMT MB A9532 V5WE2 UMA I3-4010 HDMI
SMT MB A9532 V5WE2 UMA I5-4250 HDMI
Security Classification Compal Secret Data Compal Electronics, Inc.
4319LWBOL10 2012/07/10 2013/07/10 Title
4319LWBOL21 SMT MB A9532 V5WC2 UMA I5-4200 HDMI
Issued Date Deciphered Date Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
4319LWBOL22 SMT MB A9532 V5WC2 UMA I3-4010 HDMI AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V5WE2 M/B LA-9532P Schematic
Date: Friday, April 12, 2013 Sheet 3 of 42
A B C D E
5 4 3 2 1
HASWELL_MCP_E
U1A
C54 C45
20 CPU_DP1_N0 DDI1_TXN0 EDP_TXN0 EDP_TXN0 18
C55 B46
20 CPU_DP1_P0 DDI1_TXP0 EDP_TXP0 EDP_TXP0 18
B58 A47
20 CPU_DP1_N1 DDI1_TXN1 EDP_TXN1 EDP_TXN1 18
DP to CRT 20 CPU_DP1_P1
C58
B55 DDI1_TXP1
DDI1_TXN2
EDP_TXP1
B47
EDP_TXP1 18
A55 C47
A57 DDI1_TXP2 EDP_TXN2 C46 +VCCIOA_OUT
B57 DDI1_TXN3 EDP_TXP2 A49
DDI1_TXP3 DDI EDP EDP_TXN3 B49
D D
C51 EDP_TXP3
19 CPU_DP2_N0 DDI2_TXN0
C50 A45 EDP_AUXN 18
19 CPU_DP2_P0 DDI2_TXP0 EDP_AUXN
C53 B45 EDP_AUXP 18
19 CPU_DP2_N1 DDI2_TXN1 EDP_AUXP
HDMI 19
19
CPU_DP2_P1
CPU_DP2_N2
B54
C49 DDI2_TXP1
DDI2_TXN2 EDP_RCOMP
D20 EDP_COMP R1 1 2
B50 A43 24.9_0402_1%
19 CPU_DP2_P2 DDI2_TXP2 EDP_DISP_UTIL
A53
19 CPU_DP2_N3 DDI2_TXN3
B53 Trace width=20 mils
19 CPU_DP2_P3 DDI2_TXP3 EDP_DISP_UTIL 18
Spacing=25mil
Max length=100mils
1 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168
+1.35V
Reserved for ESD
HASWELL_MCP_E
U1B
1
C94 1 2 6.8P_0402_50V8C
R184 XEMC@ T20 @ D61
T2 @ K61 PROC_DETECT MISC
470_0603_5% CATERR
N62 J62 XDP_PRDY# @ T157
27 H_PECI PECI PRDY K62 XDP_PREQ# @ T158
2
2 1 R68 R8 JTAG
PREQ E60 XDP_TCK @ T159
+1.05VS_VTT PROC_TCK
62_0402_5% 56_0402_5% E61 XDP_TMS @ T160
1 2 H_PROCHOT#_R K63 PROC_TMS E59 XDP_TRST# @ T161
DIMM_DRAMRST# 15,16 27,32,33 H_PROCHOT# PROCHOT PROC_TRST
THERMAL F63 XDP_TDI @ T162
PROC_TDI
C Reserved for ESD C95 1 2 6.8P_0402_50V8C
PROC_TDO
F62 XDP_TDO @ T163 C
XEMC@
R6 1 2 10K_0402_5% H_CPUPWRGD C61
PROCPWRGD PWR
Reserved for ESD C60 1 2 6.8P_0402_50V8C
BPM#0
J60 XDP_OBS0 @ T164
XEMC@ H60 XDP_OBS1 @ T165
BPM#1 H61
BPM#2 H62
R11 1 2 200_0402_1% SM_RCOMP0 AU60 BPM#3 K59
R13 1 2 120_0402_1% SM_RCOMP1 AV60 SM_RCOMP0 DDR3 BPM#4 H63
R41 1 2 100_0402_1% SM_RCOMP2 AU61 SM_RCOMP1 BPM#5 K60
DIMM_DRAMRST# AV15 SM_RCOMP2 BPM#6 J61
DDR_PG_CTRL AV61 SM_DRAMRST BPM#7
15 DDR_PG_CTRL SM_PG_CNTL1
2 DDR3 Compensation Signals Rev1p2
2 OF 19
C993 HASWELL-MCP-E-ULT_BGA1168
6.8P_0402_50V8C
1
XEMC@
Reserved for ESD
B B
U1 U1
CPU_SR170 _C1 CPU_SR16Q _C1
SR170@ SR16Q@
A A
SA00006SMB0 SA00006SX70
U1 U1 U1 U1 U1 U1
Security Classification Compal Secret Data Compal Electronics, Inc.
2012/07/10 2013/07/10 Title
Issued Date Deciphered Date HSW MCP(1/11) DDI,MSIC,XDP
CPU_QDJB_B1 CPU_QDJ7_B1 CPU_QDJ6_B1 CPU_QDJ9_B1 CPU_QEVE _C0 CPU_QEVG_C0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
QDJB@ QDJ7@ QDJ6@ QDJ9@ QEVE@ QEVG@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
SA000067060 SA000067H50 SA00006FY20 SA00006G120 SA00006SM30 SA00006SX30 Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. V5WE2 M/B LA-9532P Schematic
Date: Friday, April 12, 2013 Sheet 4 of 42
5 4 3 2 1
5 4 3 2 1
U1C HASWELL_MCP_E
U1D HASWELL_MCP_E
DDR_A_D0 AH63 AU37
SA_DQ0 SA_CLK#0 SA_CLK_DDR#0 15
DDR_A_D1 AH62 AV37
SA_DQ1 SA_CLK0 SA_CLK_DDR0 15
DDR_A_D2 AK63 AW36 DDR_B_D0 AY31 AM38
SA_DQ2 SA_CLK#1 SA_CLK_DDR#1 15 SB_DQ0 SB_CK#0 SB_CLK_DDR#0 16
DDR_A_D3 AK62 AY36 DDR_B_D1 AW31 AN38
SA_DQ3 SA_CLK1 SA_CLK_DDR1 15 SB_DQ1 SB_CK0 SB_CLK_DDR0 16
DDR_A_D4 AH61 DDR_B_D2 AY29 AK38
SA_DQ4 SB_DQ2 SB_CK#1 SB_CLK_DDR#1 16
DDR_A_D5 AH60 AU43 DDR_B_D3 AW29 AL38
SA_DQ5 SA_CKE0 DDRA_CKE0_DIMMA 15 SB_DQ3 SB_CK1 SB_CLK_DDR1 16
DDR_A_D6 AK61 AW43 DDR_B_D4 AV31
SA_DQ6 SA_CKE1 DDRA_CKE1_DIMMA 15 SB_DQ4
DDR_A_D7 AK60 AY42 DDR_B_D5 AU31 AY49
SA_DQ7 SA_CKE2 SB_DQ5 SB_CKE0 DDRB_CKE0_DIMMB 16
DDR_A_D8 AM63 AY43 DDR_B_D6 AV29 AU50
SA_DQ8 SA_CKE3 SB_DQ6 SB_CKE1 DDRB_CKE1_DIMMB 16
D DDR_A_D9 AM62 DDR_B_D7 AU29 AW49 D
DDR_A_D10 AP63 SA_DQ9 AP33 DDR_B_D8 AY27 SB_DQ7 SB_CKE2 AV50
SA_DQ10 SA_CS#0 DDRA_CS0_DIMMA# 15 SB_DQ8 SB_CKE3
DDR_A_D11 AP62 AR32 DDR_B_D9 AW27
SA_DQ11 SA_CS#1 DDRA_CS1_DIMMA# 15 SB_DQ9
DDR_A_D12 AM61 DDR_B_D10 AY25 AM32
SA_DQ12 SB_DQ10 SB_CS#0 DDRB_CS0_DIMMB# 16
DDR_A_D13 AM60 AP32 DDRA_ODT0 @ T4 DDR_B_D11 AW25 AK32
SA_DQ13 SA_ODT0 SB_DQ11 SB_CS#1