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5 4 3 2 1
D D
Discrete/UMA Schematics Document
Sandy Bridge
C
Intel PCH C
2011-01-19
REV : XXX
B
DY :None Installed B
UMA:UMA platform installed
PARK:DIS PARK platform installed
MADISON:DIS MADISON platform installed
Colay :Manual modify BOM
MUX : PX
A BOM A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cover Page
Size Document Number Rev
A3
LZ57 -1
Date: Tuesday, March 29, 2011 Sheet 1 of 102
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USB BD
##OnMainBoard
Block Diagram SYSTEM DC/DC
RT8208B
INPUTS
48
OUTPUTS
CPU DC/DC
NCP6131
INPUTS
42~44
OUTPUTS
POWER BD
48.4IH03.0SA
(UMA/Optimus co-lay) DCBATOUT 0D85V_S0 DCBATOUT
SYSTEM DC/DC
VCC_CORE
VRAM UP6111CQHC 45
1GB/512MB INPUTS OUTPUTS
D
Finger Printer BD 88,89,90,91
4
Project code : 91.4PA01.001 DCBATOUT 1D05V_VTT
D
48.4IH04.0SA
DDR3
PCB P/N : 10290 SYSTEM DC/DC
UP6183AQAG 41
800MHz Intel CPU Revision : -SC INPUTS OUTPUTS
IO BD
48.4IH02.0SA 5V_AUX_S5
3D3V_AUX_S5
Sandy Bridge DDRIII 1066/1333/1666 Channel A DDRIII Slot 0 DCBATOUT 5V_S5
3D3V_S5
AV BD NVIDIA PCIe x 16 1066/1333/1666 14
(Discrete only) SYSTEM DC/DC
DDRIII 1066/1333/1666 Channel B DDRIII Slot 1 UP6111C 46
N12P-GE/GV DDRIII: 1066/1333/1666 MHz
1066/1333/1666 15 INPUTS OUTPUTS
1D5V_S3
4,5,6,7,8,9,10 DCBATOUT
83.84,85,86,87 DDR_VREF_S3
SYSTEM DC/DC
HDMI FDI x 4 x 2 NCP5911 44
C 51 (UMA only) DMI x 4 C
INPUTS OUTPUTS
HDMI DCBATOUT VCC_GFXCORE
LCD
49
LVDS PCIE x 1
GLAN RJ45 VGA
RTL8111E CONN 59 RT8208B 92
RGB CRT
Intel 31
INPUTS OUTPUTS
CRT 50
BD
PCH PCIE x 1/USB2.0 x 1 Mini-Card
DCBATOUT VGA_CORE
USB x 2 Cougar Point WLAN 65 TI CHARGER
BQ24745 40
14 USB 2.0/1.1 ports Mini-Card INPUTS OUTPUTS
Bluetooth USB2.0 x 5 PCIE x 1/USB2.0 x 1
63 +DC_IN_S5
ETHERNET (10/100/1000Mb) 66 SIM +PBATT DCBATOUT
WWAN 66
High Definition Audio 26
CAMERA SATA ports (6) MB LDO
49 35 47
PCIE x 1 NEC RT9025
PCIE ports (8) USB 3.0 x 1
uPD720200 62 INPUTS OUTPUTS
LPC I/F
Finger Print 64 ACPI 1.1 3D3V_S5 1D8V_S0
B B
USB 2.0 x 1/SATA x 1 E-SATA/USB SYSTEM DC/DC
CardReader USB 2.0 x 1 comb 57
G9091-180T11U 24,93
SD/MMC+/MS/
INPUTS OUTPUTS
MS Pro/xD 74 Realtek 17,18,19,20,21,22,23,24,25 26
3D3V_S5 1D5V_S5
SATA x 2 HDD
RTS5139 AZALIA 56 3D3V_S0 1D8V_VGA_S0
LDO
SPI
ODD 46
RT9026
LPC Bus
56
Internal DMIC Azalia
INPUTS OUTPUTS
CODEC
I/O BD
5V_S5 0D75V_S0
HP1 Realtek Flash ROM LPC debug port
RTC8111E 4MB 60 71
MIC IN G1454
PCB LAYER
29 L1:Top L5:VCC
L2:GND L6:Signal
KBC SMBus L3:Signal L7:GND
A
NUVOTON L4:Signal L8:Signal
A
BOM
NPCE795 27
2CH SPEAKER Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Touch Int. Thermal Block Diagram
G-Sensor Fan
PAD KB EMC2103-2-AP 28
Size
A3
Document Number Rev
79 69 69 2528 LZ57 -1
Date: Tuesday, March 29, 2011 Sheet 2 of 102
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A
PCH Strapping Huron River Schematic Checklist Rev.0_7
B C
Processor Strapping D
Huron River Schematic Checklist Rev.0_7
E
Name Schematics Notes Pin Name Strap Description Configuration (Default value for each bit is Default
SPKR Reboot option at power-up 1 unless specified otherwise) Value
Default Mode: Internal weak Pull-down.
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with CFG[2] PCI-Express Static 1: Normal Operation.
8.2-k Lane Reversal 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 1
- 10-k weak pull-up resistor.
INIT3_3V# Weak internal pull-up. Leave as "No Connect".
Disabled - No Physical Display Port attached to
GNT3#/GPIO55 GNT[3:0]# functionality is not available on Mobile. CFG[4] 1: Embedded DisplayPort.
4 GNT2#/GPIO53
GNT1#/GPIO51
Mobile: Used as GPIO only
Pull-up resistors are not required on these signals.
Enabled - An external Display Port device is
0: connectd to the EMBEDDED display Port
0
4
If pull-ups are used, they should be tied to the Vcc3_3power rail.
CFG[6:5] PCI-Express 11 : x16 - Device 1 functions 1 and 2 disabled
Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor. Port Bifurcation 10 : x8, x8 - Device 1 function 1 enabled ;
SPI_MOSI
Straps function 2 disabled 11
Left floating, no pull-down required.
Disable Danbury: 01 : Reserved - (Device 1 function 1 disabled ;
function 2 enabled)
00 : x8, x4, x4 - Device 1 functions 1 and 2
Enable Danbury: Connect to +NVRAM_VCCQ with 8.2-kohm enabled
weak pull-up resistor [CRB has it pulled up
NV_ALE with 1-kohm no-stuff resistor] CFG[7] PEG DEFER TRAINING 1: PEG Train immediately following xxRESETB de assertion
1
0: PEG Wait for BIOS for training
Leave floating (internal pull-down)
Disable Danbury:
NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.
Low (0) - Flash Descriptor Security will be overridden. Also,
when this signals is sampled on the rising edge of PWROK
then it will also disable Intel ME and its features. Voltage Rails
HAD_DOCK_EN# High (1) - Security measure defined in the Flash Descriptor will be enabled. POWER PLANE VOLTAGE DESCRIPTION
ACTIVE IN
/GPIO[33] Platform design should provide appropriate pull-up or pull-down depending on 5V_S0 5V
3 the desired settings. If a jumper option is used to tie this signal to GND as
required by the functional strap, the signal should be pulled low through a weak
3D3V_S0
1D8V_S0
3.3V
1.8V
3
1D5V_S0 1.5V
pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. 1D05V_VTT 1.05V
Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal 0D85V_S0 0.95 - 0.85V
pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for 0D75V_S0 0.75V
VCC_CORE 0.35V to 1.5V S0
strapping functions. VCC_GFXCORE 0.4 to 1.25V
1D8V_VGA_S0 1.8V CPU Core Rail
HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. 3D3V_VGA_S0 3.3V Graphics Core Rail
1V_VGA_S0 1V
HDA_SYNC Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no 5V_USBX_S3 5V
GPIO15 1D5V_S3 1.5V S3
confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher DDR_VREF_S3 0.75V
suite with confidentiality
Note : This is an un-muxed signal.
BT+ 6V-14.1V AC Brick Mode only
This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. DCBATOUT 6V-14.1V
Sampled at rising edge of RSMRST#. 5V_S5 5V All S states
CRB has a 1-kohm pull-up on this signal to +3.3VA rail. 5V_AUX_S5 5V
3D3V_S5 3.3V
GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down 3D3V_AUX_S5 3.3V
GPIO8 using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of 3D3V_LAN_S5 3.3V WOL_EN Legacy WOL
RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is
enabled.
2 Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for
3D3V_AUX_KBC 3.3V DSW, Sx ON for supporting Deep Sleep states
2
GPIO27
analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter Powered by Li Coin Cell in G3
3D3V_AUX_S5 3.3V G3, Sx and +V3ALW in Sx
circuits for analog rails.
USB Table
Pair Device
SMBus ADDRESSES
PCIE Routing 0 Touch Panel / 3G SIM
1 USB Ext. port 1 (HS) I2 C / SMBus Addresses
HURON RIVER ORB
2 Fingerprint Device Ref Des Address Hex Bus
LANE1 Mini Card2(WWAN)
3 BLUETOOTH
EC SMBus 1 BAT_SCL/BAT_SDA
LANE2 Onboard LAN SATA Table 4 Mini Card2 (WWAN) Battery BAT_SCL/BAT_SDA
CHARGER BAT_SCL/BAT_SDA
LANE3 Card Reader 5 CARD READER
SATA EC SMBus 2 SML1_CLK/SML1_DATA
6 X PCH
Pair Device SML1_CLK/SML1_DATA
LANE4 Mini Card1(WLAN) 7 X eDP SML1_CLK/SML1_DATA
1 LANE5 USB3.0 0 HDD1 8 USB Ext. port 4 / E-SATA /USB CHARGER
BOM
1
1 HDD2 9 USB Ext. port 2 PCH SMBus
Wistron Corporation
PCH_SMBDATA/PCH_SMBCLK 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
LANE6 Intel GBE LAN 2 N/A 10 USB Ext. port 3 SO-DIMMA (SPD) PCH_SMBDATA/PCH_SMBCLK Taipei Hsien 221, Taiwan, R.O.C.
SO-DIMMB (SPD) PCH_SMBDATA/PCH_SMBCLK
Digital Pot PCH_SMBDATA/PCH_SMBCLK Title
LANE7 Dock 3 N/A 11 Mini Card1 (WLAN) G-Sensor PCH_SMBDATA/PCH_SMBCLK
4 ODD 12 CAMERA MINI PCH_SMBDATA/PCH_SMBCLK Table of Content
Size Document Number Rev
LANE8 New Card 5 ESATA 13 New Card A3
LZ57 -1
Date: Tuesday, March 29, 2011 Sheet 3 of 102
A B C D E
5
SSID = CPU 4 3 2 1
Signal Routing Guideline:
PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
1D05V_VTT
CPU1A 1 OF 9
J22 PEG_IRCOMP_R R401 1 2 24D9R2F-L-GP
PEG_ICOMPI
Note:
19 DMI_TXN[3:0] DMI_TXN0 B27
SANDY PEG_ICOMPO
J21
H22
DMI_RX#0 PEG_RCOMPO
D Intel DMI supports both Lane
Reversal and polarity inversion
DMI_TXN1
DMI_TXN2
DMI_TXN3
B25
A25
B24
DMI_RX#1
DMI_RX#2
K33 PEG_RXN15
PEG_RXN[0..15]
PEG_RXN[0..15] 83
D
DMI_RX#3 PEG_RX#0 PEG_RXN14
but only at PCH side. This is 19 DMI_TXP[3:0] PEG_RX#1
M35
DMI_TXP0 B28 L34 PEG_RXN13
enabled via a soft strap. DMI_TXP1 DMI_RX0 PEG_RX#2 PEG_RXN12
B26 J35
DMI_RX1 PEG_RX#3
DMI
DMI_TXP2 A24 J32 PEG_RXN11
DMI_TXP3 DMI_RX2 PEG_RX#4 PEG_RXN10
B23 H34
DMI_RX3 PEG_RX#5 PEG_RXN9
H31
19 DMI_RXN[3:0] DMI_RXN0 PEG_RX#6 PEG_RXN8
G21 G33
DMI_RXN1 DMI_TX#0 PEG_RX#7 PEG_RXN7
E22 G30
DMI_RXN2 DMI_TX#1 PEG_RX#8 PEG_RXN6
F21 F35
DMI_RXN3 DMI_TX#2 PEG_RX#9 PEG_RXN5
D21 E34
DMI_TX#3 PEG_RX#10 PEG_RXN4
E32
19 DMI_RXP[3:0] DMI_RXP0 PEG_RX#11 PEG_RXN3
G22 D33
DMI_RXP1 DMI_TX0 PEG_RX#12 PEG_RXN2
D22 D31
DMI_TX1 PEG_RX#13
PCI EXPRESS* - GRAPHICS
DMI_RXP2 F20 B33 PEG_RXN1
DMI_RXP3 DMI_TX2 PEG_RX#14 PEG_RXN0
C21 C32
DMI_TX3 PEG_RX#15 PEG_RXP[0..15]
PEG_RXP[0..15] 83
J33 PEG_RXP15
PEG_RX0 PEG_RXP14
L35
PEG_RX1 PEG_RXP13
K34
19 FDI_TXN[7:0] FDI_TXN0 PEG_RX2 PEG_RXP12
A21 H35
FDI_TXN1 FDI0_TX#0 PEG_RX3 PEG_RXP11
H19 H32
FDI_TXN2 FDI0_TX#1 PEG_RX4