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AUO-P303.11
PMIC for TFT-LCD TV Panels
General Description Features
The AUO-P303.11 is a programmable multi-functional 9.5V to 14V Input Supply Voltage
power solution for TFT-LCD panels. The AUO-P303.11 4.3A Boost Internal and External Option Regulator
contains a step-up converter for main power and step- for AVDD with Programmable 13.69V to 19.02V
Output and 500kHz to 2MHz Switching Frequency
down converters to provide the driver and logic voltages
4.3A SEPIC Internal and External Option Regulator
for the system. Moreover, a positive charge pump regulator
for AVDD with Programmable 5.63V to 14.08V Output
and external MOSFET Boost Control provides the
and 500kHz to 2MHz Switching Frequency
adjustable gate-high voltage, VGH, with the temperature
2.5A Sync. / Async Buck Converter for VLOGIC with
compensation; a negative charge pump regulator and
2.2V to 3.7V Programmable Output and 750kHz /
external MOSFET inverting control provides the gate-low
1.5MHz Switching Frequency
voltage, VGL, with a negative regulator, VSS. The 1-CH 2.5A Sync. Buck Converter for V CORE with
DVCOM control with temperature compensation is also Programmable 0.968V to 2.02V Output and 500kHz
integrated. All channel outputs and power sequence can / 750kHz / 1MHz Switching Frequency
be programmed by I2C interface and integrated Multiple- VLOGIC / VCORE Buck Converter Use Chip Inductor
Time Programmable (MTP) non-volatile memory. The AUO- with One Half Current Limit
P303.11 is available in the VQFN-40L 5x5 package. Negative Charge Pump Regulator and External
MOSFET Inverting Control for VGL with -14V to
- 4V Programmable Output and Temperature
Ordering and Marking Information
Compensation
Marking
Part No. Package Type Negative Regulator for VSS with - 11.5V to
Information
- 4V
VQFN-40L 5x5
AUO-P303.11 AUO P303-11 Positive Charge Pump Regulator and External
(V-Type)
MOSFET Boost Control for VGH with 19V to 34V
Programmable Output and Temperature
Pin Configurations Compensation
1-CH DVCOM Control with Temperature
(TOP VIEW)
Compensation
VCOMNEG
ADD_EGD
Internal AVDD Isolation P-MOSFET
DRVSS
GATEP
VCOM
Integrated MTP Non-Volatile Memory
OSO
SDA
VSS
SCL
OSI
Programmable Sequencing
40 39 38 37 36 35 34 33 32 31
Over-Temperature Protection (OTP)
LX/AVDD_CS 1 30 DRVP/VGH_CS
LX/AVDD_CS 2 29 VGH Over-Voltage Protection (OVP)
PGND 3 28 PGND Over-Current Protection (OCP)
AVDD_GATE 4 27 COMPGH
NWR 5 26 VT Under-Voltage Protection (UVP)
PGND
COMPA 6 25 EN Short-Circuit Protection (SCP)
VC 7 24 VDC
I2C-Compatible Interface for Register Control
PGND 8
41
23 AGND
LX_VC 9 22 VIN Thin 40-Lead VQFN Package
LX_VC 10 21 VIN RoHS Compliant and Halogen Free
11 12 13 14 15 16 17 18 19 20
VIN_VC
VIN_VC
GATEN
A0
DRVN
VGL
VGL_CS
OUTB
LXB
LXB
Applications
TFT-LCD TV Panel
VQFN-40L 5x5
TFT-LCD Monitor Panel
Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
AUO-P303.11-00 September 2015 www.richtek.com
1
AUO-P303.11
Typical Application Circuit
L1 D1
10µH SK34 AVDD_F
VIN
12V C1 C3
10µF x 2 10µF x 2
21, 22 AUO-P303.11
VIN
1, 2
11, 12 LX/AVDD_CS
VIN_VC
L2
10µH 39
VLOGIC 19, 20 OSI
3.3V LXB
C7 D2 38 AVDD
10µF x 3 OSO
LX SS24 15.77V
COUT
18 R12 10µF x 4
OUTB 33k
R1 R2 L3 6
COMPA LXB
4.7 4.7 4.7µH C15
VCORE 9, 10 LX_VC 1nF VGL
1.2V C10 -10V
10µF x 3 R15 R16
17
0.47µF VGL 4.7 4.7
7 C19
VC
R13 10µF
D3 D4 0 C17
16 Q2
AVDD_F DRVN 0.47µF
C11 27 BTC2881M3
BAT54S/IN4148 COMPGH R14
0.1µF
R3 10k D5 D6
10k
R4 24
VDC C18
0
BTB5140N3
30
DRVP/VGH_CS R17
C16 0.1µF BAT54S/IN4148
Q1 1µF
VGH 29 0
VGH 25
30V C12 EN
4.7µF
Q4
26 BTC2881M3
VT VGL VSS
R5 C20 5 40 -6V
NWR NWR AVDD_EGD R18
5.6k 0.1nF C21 C22
32 4.7µF 10k 4.7µF
SCL SCL
R7 R6 R19 4.7k 34
NCP15WL DRVSS
683B03RC 150k 3.3V 35
VSS
R20 4.7k
33
SDA SDA 13
VGL_CS
36 VCOMNEG 14
GATEN
R10
0 15
37 A0
To VCOM VCOM
C14 R18
10µF AGND PGND 47k
23 3, 8, 28,
41 (Exposed Pad)
Figure 1. Charge Pump Type + Internal GD-MOS
Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
www.richtek.com AUO-P303.11-00 September 2015
2
AUO-P303.11
L1 D1 Q1
10µH SK34 SI3483CDV
VIN AVDD_F AVDD
12V C1 C3, C4 15.77V
10µF x 2 10µF x 2 C5 C6 COUT
AUO-P303.11 47nF 2.2nF 10µF x 4
21, 22
VIN
1, 2
11, 12 LX/AVDD_CS
VIN_VC
L2
10µH 39
VLOGIC 19, 20 OSI
LXB
3.3V C7 D2 40
AVDD_EGD
10µF x 3 SS24
38
18 OSO
AVDD OUTB
L3
4.7µH R11
VCORE 9, 10 33k VIN
L4 LX_VC 6
22µH 1.2V C10 COMPA
D3 C18
10µF x 3
SR26 1nF C23
7 R12 R13 10µF
VC 20k 100m
R17 13
0 VGL_CS
Q2 31 R16
GATEP Q3
SI2308 14 0 SI2309
30 GATEN
DRVP/VGH_CS
R3 D4
R1 R2 24 SR26 VGL
100m 20k 120k 27 VDC
COMPGH C21 C19, C20 -10V
C15 R14 1µF L4 4.7µF x 2
120pF 0 10µH
25
VGH EN
29
VGH 17
30V C13, C14 VGL
26
4.7µF x 2 VT
R4 C20 Q4
5.6k 0.1nF BTC2881M3
5 VGL VSS
NWR NWR 16 -6V
DRVN C21 R18 C22
R6 R5 32 10k 4.7µF
NCP15WL SCL SCL 4.7µF
150k
683B03RC R19 4.7k 34
3.3V DRVSS
35
R20 4.7k VSS
33
SDA SDA
36 VCOMNEG
R9
0 15
37 A0
To VCOM VCOM
C17 R15
AGND PGND 47k
10µF
23 3, 8, 28,
41 (Exposed Pad)
Figure 2. DC/DC Converter Type + External GD-MOS
Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
AUO-P303.11-00 September 2015 www.richtek.com
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AUO-P303.11
L1 D1 Q1
10µH SK34 AVDD_F SI3483CDV
VIN AVDD
12V C1 C3, C4 15.77V
10µF x 2 10µF x 2 C5 C6 COUT
47nF 2.2nF 10µF x 4
21, 22 4 Q1
VIN AVDD_GATE
AO3402
11, 12 R1 (IPD09N03L)
VIN_VC 20k
L1 1, 2
LX/AVDD_CS
10µH
VLOGIC 19, 20 AUO-P303.11
3.3V LXB R2 R3
C7 D2 100m 100m
10µF x 3 SS24
AVDD 18
OUTB
L2 39
4.7µH OSI
L3 VCORE 9, 10 LX_VC 40
22µH 1.2V C10 AVDD_EGD
D3 38
SR26 10µF x 3 OSO
7
VC R14
R19 33k VIN
0 31 6
Q2 GATEP COMPA
C18
SI2308 1nF C23
30 R15 R16
DRVP/VGH_CS 10µF
R6 20k 100m
R4 R5 13
120k 27 VGL_CS
100m 20k COMPGH R20
C15 0 Q3
120pF 14 SI2309
GATEN
VGH 29 D4 SR26 VGL
VGH 24
30V VDC -10V
C13, C14 26 C21 C19, C20
4.7µF x 2 VT R17 1µF L4 4.7µF x 2
R7 C22 0
25 10µH
5.6k 0.1nF 5 EN
NWR NWR
32 VGL 17
R9 R8 SCL SCL
NCP15WL Q4
150k R19 4.7k BTC2881M3
683B03RC VGL VSS
3.3V 16 -6V
DRVN C21 R18 4.7µF
R20 4.7k 4.7µF 10k C22
33
SDA SDA
34
36 DRVSS
R12 VCOMNEG 35
0 VSS
37 15
To VCOM VCOM
C17 A0
10µF AGND PGND R18
23 3, 8, 28, 47k
41 (Exposed Pad)
Figure 3. AVDD Controller Type
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AUO-P303.11
L1 Coupled C23 D1 Q1
10µH 1µF x 2 SK34
VIN AVDD_F SI3483CDV AVDD
12V C1 C3, C4 11V
10µF x 2 10µF x 2 C5 C6 COUT
L2 47nF 2.2nF 10µF x 4
21, 22 AUO-P303.11 10µH
VIN
11, 12
VIN_VC
L1 1, 2
LX/AVDD_CS
10µH
VLOGIC 19, 20
3.3V LXB
C7 D2
10µF x 3 SS24
AVDD 18
OUTB
L2 39
4.7µH OSI
L3 VCORE 9, 10 LX_VC 40
22µH 1.2V C10 AVDD_EGD
D3
SR26 10µF x 3 38
OSO
7
VC R14
R19 100k VIN
0 31 6
Q2 GATEP COMPA
C18
SI2308
30 330pF
DRVP/VGH_CS R15 R16
R6 20k 100m
R4 R5 13
120k 27 VGL_CS
100m 20k COMPGH R20
C15 0 Q3
120pF 14
GATEN SI2309
VGH 29 D4 VGL
VGH 24 SR26
30V VDC -10V
C13, C14 26 C21 C19, C20
4.7µF x 2 VT R17 1µF L4 4.7µF x 2
R7 C22 0
25 10µH
5.6k 0.1nF EN
5
NWR NWR
32 VGL 17
R9 R8 SCL SCL Q4
NCP15WL 150k
683B03RC R19 4.7k BTC2881M3 VSS
VGL
3.3V 16 -6V
DRVN C21 R18 C22
R20 4.7k 4.7µF 10k 4.7µF
33
SDA SDA
36 VCOMNEG 34
DRVSS
R12 35
0 37 VSS
To VCOM VCOM 15
C17 A0
10µF AGND PGND R18
23 3, 8, 28, 47k
41 (Exposed Pad)
Figure 4. AVDD SEPIC Controller Type
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AUO-P303.11
L1 D1 Q1
10µH SK34 AVDD_F SI3483CDV
VIN AVDD
12V C1, C2 C3, C4 15.77V
10µF x 2 10µF x 2 C5 C6 COUT
AUO-P303.11 47nF 2.2nF 10µF x 4
21, 22
VIN
11, 12 1, 2
VIN_VC LX/AVDD_CS
L2
VLOGIC 10µH
19, 20 39
3.3V LXB OSI
C7, C8, C9 D2
10µF x 3 SS24 40
AVDD_EGD
AVDD 18 38
OUTB OSO
L3
L4 4.7µH 9, 10 R11
VCORE LX_VC 33k
22µH 1.2V 6
D3 C10, C11, C12 COMPA
SR26 10µF x 3 C18 LXB
7 VGL
VC 1nF
-10V
R16
Q2
0 31
GATEP VGL 17 R14 R15
C19 4.7 4.7
SI2308
30 10µF
DRVP/VGH_CS 16 R12 Q3 C21
DRVN
R3 BTC2881M3 0.47µF
R1 R2 R13
100m 20k 120k 27
COMPGH 10k
C15 D4 D5
120pF
C20 BAT54S/IN4148
VGH 29 24 0.1µF
VGH VDC
30V C13, C14 C21
26 R14
4.7µF x 2 VT 1µF Q4
C22 0
R4 25 BTC2881M3 VSS
5.6k 0.1nF 5 EN VGL
NWR NWR -6V
C21 R18 C22
32 4.7µF 10k 4.7µF
R6 R5 SCL SCL
NCP15WL 150k R19 4.7k
683B03RC 34
DRVSS
3.3V 35
R20 4.7k VSS
33 13
SDA SDA VGL_CS
36 VCOMNEG
R9 14
GATEN
0 37
To VCOM VCOM 15
C17 A0
10µF R15
AGND PGND
47k
23 3, 8, 28,
41 (Exposed Pad)
Figure 5. VGH Boost + VGL Charge Pump
Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
www.richtek.com AUO-P303.11-00 September 2015
6
AUO-P303.11
L1 D1 Q1
10µH SK34 AVDD_F SI3483CDV
VIN AVDD
12V C1, C2 C3, C4 15.77V
10µF x 2 10µF x 2 C5 C6 COUT
47nF 2.2nF 10µF x 4
21, 22 AUO-P303.11
VIN
11, 12 1, 2
VIN_VC LX/AVDD_CS
L2
VLOGIC 6.8µH
19, 20 39
3.3V LXB OSI
C7, C8, C9
10µF x 3 40
AVDD_EGD
AVDD 18 38
OUTB OSO
L3
L4 4.7µH 9, 10 R11
VCORE LX_VC 33k
22µH 1.2V 6
D3 C10, C11, C12 COMPA
SR26 10µF x 3 C18 LXB
7 VGL
VC 1nF
R16 -10V
Q2
0 31
GATEP VGL 17 R14 R15
C19 4.7 4.7
SI2308
30 10µF
DRVP/VGH_CS 16 R12 Q3 C21
DRVN
R3 BTC2881M3 0.47µF
R1 R2 R13
100m 20k 120k 27
COMPGH 10k
C15 D4 D5
120pF
C20 BAT54S/IN4148
VGH 29 24 0.1µF
VGH VDC
30V C13, C14 C21
26 R14
4.7µF x 2 VT 1µF
C22 0 Q4
R4 5 25 BTC2881M3 VSS
5.6k 0.1nF NWR NWR EN VGL
-6V
32 C21 R18 C22
SCL SCL 4.7µF 10k 4.7µF
R6 R5
NCP15WL R19 4.7k
150k 34
683B03RC 3.3V DRVSS
R20 4.7k 35
33 VSS
SDA SDA 13
VGL_CS
36 VCOMNEG 14
R9 GATEN
0 37
To VCOM VCOM 15
C17 A0
10µF R15
AGND PGND
47k
23 3, 8, 28,
41 (Exposed Pad)
Figure 6. VCORE and Sync. VLOGIC used Chip Inductor
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AUO-P303.11
Timing Diagram
2
§ this timing disable I C interface to NVM and register value won't
be changed when input outer signals
UVLO = 7.9V UVLO = 7.6V
2 VIN = 8V
§ VIN lower than 8V, disable I C interface to NVM and register
VIN value won't be changed when input outer signals
Load Data from MTP
EN / VDC 2ms Re-Load Data
§ Load Data check data mapping, if It over 3 times fail, then IC shut down
MTP Signal
§ UVLO 2ms waiting for power stable and IC do nothing
VIN
LX_VC INPUT = VIN
TSSC
VCORE
1.5ms
VIN
LXB
1.5ms
TSSIO
VLOGIC
DLY_3D3
VGL 4ms
TSS_VGL
DLY_GL
4ms
VSS