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DATA SHEET
SPHE8281D
DVD Single Chip MPEG A/V
Processor
Preliminary
MAY 19, 2005
Version 0.1
Sunplus Technology reserves the right to change this documentation without prior notice. Information provided by Sunplus Technology is believed to be
accurate and reliable. However, Sunplus Technology makes no warranty for any errors which may appear in this document. Contact Sunplus Technology to
obtain the latest version of device specifications before placing your order. No responsibility is assumed by Sunplus Technology for any infringement of patent
or other rights of third parties which may result from its use. In addition, Sunplus Technology products are not authorized for use as critical components in life
support systems or aviation systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without
the express written approval of Sunplus.
Preliminary
SPHE8281D/Dx
Table of Contents
PAGE
1. GENERAL DESCRIPTION............................................................................................................................................................................... 3
2. FEATURE .......................................................................................................................................................................................................... 4
3. BLOCK DIAGRAM ........................................................................................................................................................................................... 6
4. SIGNAL DESCRIPTION ................................................................................................................................................................................... 7
4.1. PIN MAP ..................................................................................................................................................................................................... 7
4.2. GROUP MAP ............................................................................................................................................................................................... 8
4.3. PIN DESCRIPTION........................................................................................................................................................................................ 9
5. FUNCTIONAL DESCRIPTIONS .................................................................................................................................................................... 22
5.1. PLL AND CLOCKGEN ................................................................................................................................................................................ 22
5.2. POWER CONTROL ..................................................................................................................................................................................... 22
5.3. EMBEDDED 32-BIT RISC CONTROLLER ..................................................................................................................................................... 22
5.4. ROM/FLASH/SRAM CONTROLLER ........................................................................................................................................................... 23
5.5. CSS DECRYPTION HARDWARE ................................................................................................................................................................. 24
5.6. MPEG VIDEO DECODER ........................................................................................................................................................................... 24
5.7. VIDEO POST PROCESSING ........................................................................................................................................................................ 24
5.8. PROGRAMMABLE AUDIO DECODER............................................................................................................................................................ 25
5.9. AUDIO INTERFACE ..................................................................................................................................................................................... 25
5.10. AUDIO DAC .............................................................................................................................................................................................. 25
5.11. I/O PROCESSOR ....................................................................................................................................................................................... 25
5.12. SDRAM CONTROLLER ............................................................................................................................................................................. 25
5.13. SUB- PICTURE DECODER ........................................................................................................................................................................... 25
5.14. ON SCREEN DISPLAY ................................................................................................................................................................................ 25
5.15. DISPLAY INTERFACE .................................................................................................................................................................................. 26
5.16. VIDEO DAC .............................................................................................................................................................................................. 26
5.17. GPIO........................................................................................................................................................................................................ 26
5.18. UART ....................................................................................................................................................................................................... 26
6. ELECTRICAL SPECIFICATIONS .................................................................................................................................................................. 27
6.1. ABSOLUTE MAXIMUM RATINGS .................................................................................................................................................................. 27
6.2. DC OPERATING CONDITIONS .................................................................................................................................................................... 27
6.3. CAPACITANCE ........................................................................................................................................................................................... 27
6.4. AC CHARACTERISTICS .............................................................................................................................................................................. 28
6.4.1. SDRAM interface timing diagrams .............................................................................................................................................. 28
6.4.2. ROM / flash interface timing diagrams........................................................................................................................................ 29
6.4.3. Audio interface timing diagrams .................................................................................................................................................. 30
6.4.4. Video timing diagrams ................................................................................................................................................................. 31
7. PACKAGE/PAD LOCATION .......................................................................................................................................................................... 33
7.1. OUTLINE DIMENSIONS ............................................................................................................................................................................... 33
8. DISCLAIMER .................................................................................................................................................................................................. 34
9. REVISION HISTORY ...................................................................................................................................................................................... 35
© Sunplus Confidential 2 MAY. 19, 2005
Contents are subject to change without Notice Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
DVD SINGLE CHIP MPEG A/V PROCESSOR
1.GENERAL DESCRIPTION
SPHE8281D A/V decoder is a single-chip integrated DVD A/V ISO/IEC 11172 MPEG1, 13818 MPEG2 sources. Besides MPEG
decoder. It is designed to maximize system performance with A/V decoding, it supports Dolby Digital and MPEGI/II Layer1/2,
minimum cost. It integrates DVD/CD controller, host processor, PCM, LPCM audio playback.
A/V decoding hardware, audio quality DAC and a 6-channel SPHE8281D also combines all the functions required for a
multi-format TV-encoder. high-performance progressive-scan DVD system. Built-in
de-interlacing hardware allows high quality DVD playback. The
SPHE8281D supports DVD and CD physical formats. For logical embedded digital audio decoder is able to support key control and
formats it supports DVD-Video, Super Video CD, Video CD, audio sound effects for Karaoke.
CD-DA, OKO, and CD-ROM discs.
Development tools of SPHE8281D include complete compiler
SPHE8281D performs real-time decoding and playback of tools, programming guide and system application libraries.
Application utilizing the SPHE8281D is presented below:
IR
4-ch video
VFD output
front panel
SPHE8281D 2-ch audio analog
output Audio
Audio amplifier
DVD-loader 2~8ch
DAC
USB
SDRAM
devices
ROM
Figure 1-1 Sample SPHE8281D application
© Sunplus Confidential 3 MAY. 19, 2005
Contents are subject to change without Notice Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
2.FEATURE
Single Chip Integrated DVD Servo and A/V Decoder SDRAM controller
Integrated DVD/CD Servo Controller -- High Performance SDRAM controller
-- Support 1x ~ 2x DVD format reading -- Support 16 or 32 bit operation
-- Support 1x ~ 8x CD format reading -- Support up to 2 SDRAM devices
Embedded 32-bit RISC Processor without external host -- Support 16M/64M SDRAM devices
controller Video Display
Embedded Audio Processor supports multiple audio standards -- De-interlacing of interlaced video source
Embedded 8-bit I/O processor supports programmable -- Flexible vertical interpolation
interface control -- Flexible horizontal interpolation with optional CIF filter
Embedded TV encoder with multi-channel built-in high-speed -- Powerful cropping and panning effect
video DAC supports various display standards -- Support YUV422, 8-bit indexed color format
Embedded 2-channel 24-bit audio DAC OSD
Built-in system PLL and audio PLL generate all clock sources -- Multiple OSD regions with different formats
required from single 27MHz crystal input -- Support 2/4/16 indexed color
Support following disc format: -- Support 16/24-bit direct color
-- DVD Navigation 1.0 Embedded TV encoder
-- SVCD (Chaoji VCD) -- Simultaneous multi-channel output
-- OKO disc -- Support 480i/480p/576i/576p format
-- VCD 2.0/1.1/1.0 -- Support CVBS and S-Video output
-- CDDA / HDCD -- Support Component (YUV / YPbPr) or SCART-RGB output
-- CDROM (game, WMA and JPEG disc) -- Support WSS and CGMS/A
TM 3
CSS/CPPM hardware -- Macrovision 7.1.D1 and Macrovision AGC v1.03
-- Built-in CSS hardware analog copy protection
-- Built-in CPPM C2_DCBC and C2_D/C2_E function Interface
Video Decoder -- 27MHz crystal driver
-- Real time MPEG2 MP@ML decoding -- 16/32-bit SDRAM interface
-- Real time MPEG4 ASP D1 resolution decoding -- 8-bit ROM/FLASH/SRAM interface
-- Real time MPEG1 D1 (720x480x30 /720x576x25) decoding -- One UART port
-- DivX 3.11, 4.0 and 5.x version compatible -- IR and VFD support
-- Hardware accelerated JPEG decoding -- 4-channel 12-bit video DAC analog output
-- Advanced decoding and display control -- Simultaneous 8-channel audio DAC output
Sub-picture Decoder -- IEC958/SPDIF digital input / output
-- Advanced Sub-Picture Decoder for DVD SVCD and OKO -- 2-channel 24-bit audio DAC analog output
-- Support hardware vertical scaling -- External ADC digital input interface (optional)
Audio Decoder -- Optional ATAPI and I2S interface support
-- Flexible Programmable DSP Architecture -- Optional Parallel Port interface support
-- Support CDDA Low power
TM 1
-- Support LPCM, PCM, and WMA playback -- Advanced low power design
-- Support MPEGI/II layer 1/2 and MPEG 2.5 playback (with -- Selective standby mode
optional down-mixing) -- Programmable low speed operation
TM 2
-- Support Dolby Digital AC3 playback Technology
-- Support Key Shift of 2 channels -- Advanced CMOS technology
-- Support equalization, reverb and special sound field -- 216-pin LQFP package
-- 3v (I/O) and 1.8v (kernel) power supplies
-- 5v I/O tolerance
1
WMA is a trademark of Microsoft Corporation
2 3
Dolby is a trademark of the Dolby Laboratories Macrovision is a trademark of Macrovision Corporation
© Sunplus Confidential 4 MAY. 19, 2005
Contents are subject to change without Notice Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
% Licensing Notice
In order to take care of different royalties, Sunplus SPHE8281D series have different combinations for different royalties.
For detail information, please contact with Sunplus Sales.
Supply of the implementation of Dolby, WMA, Macrovision ... technologies do not imply of a right or convey a license
under any patent, or any Intellectual Property Right of each respective company. Companies plan to use the
implementations MUST obtain respective license from respective licensor. Additional royalties may be required and are to
be paid by purchaser to each respective licensor
Dolby is a trademark of the Dolby Laboratories. "This product includes technology owned by Dolby Laboratories cannot be
used or further distributed without a license from Dolby Laboratories."
WMA is a trademark of Microsoft Corporation. "This product includes technology owned by Microsoft Corporation cannot
be used or further distributed without a license from Microsoft."
DivX is a trademark of the DivXNetworks Inc. "This product includes technology owned by DivXNetworks Inc. cannot be
used or further distributed without a license from DivXNetworks Inc."
Macrovision is a trademark of the Macrovision Corporation. "This product includes technology owned by Macrovision
Corporation cannot be used or further distributed without a license from Macrovision Corporation."
All other trademarks are owned and trademarks of their respective holders and companies, which are used for
identification purposed only
© Sunplus Confidential 5 MAY. 19, 2005
Contents are subject to change without Notice Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
3.BLOCK DIAGRAM
PLLv PLLa Servo
EPROM/ RISC loader inf.
EPROM/SRAM SRAM Power control Control
interface icache dcache
RF loader RF input
Audio
Intr. control DSP ECC
USB 1.1
USB1.1 bus
host Timer icache mem
I/O
IR/VFD/(I2C)
RISC DMA Bootstrap processor
SDRAM
SDRAM /16 or /32
controller GPIO GPIO
HOST
OSD DMA UART UART
decoder
Video
encoder DAC DAC analog out
Sub-picture
decoder MPEG
Video output Video DAC video Audio
Video post- IEC 958 I/O
decoder Interface
processing ADC digital in
Figure 3-1 SPHE8281D block diagram
© Sunplus Confidential 6 MAY. 19, 2005
Contents are subject to change without Notice Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
4.SIGNAL DESCRIPTION
4.1. Pin Map
VSS_O5/VSS_K5
VSS_O4/VSS_K4
VSS_O3/VSS_K3
M_DQM2/GPIO
M_DQM3/GPIO
M_DQM0/GPIO
M_DQM1/GPIO
M_CKE/GPIO
M_BA1/GPIO
M_A11/GPIO
M_CLKO
R_WE_B
VDD_O4
VDD_O3
R_OE_B
VDD_K4
VDD_K3
M_A10
R_A12
R_A10
R_A11
R_A13
R_A14
R_A17
M_A3
M_A2
M_A1
M_A0
M_A4
M_A5
M_A6
M_A7
M_A8
M_A9
M_D8
M_D9
R_A7
R_A6
R_A5
R_A4
R_A3
R_A2
R_A1
R_A0
R_D0
R_D1
R_D2
R_D3
R_D4
R_D5
R_D6
R_D7
R_A9
R_A8
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
R_A15 163 108 M_D10
DAC_REF 164 107 M_D11
DAC_L 165 106 M_D12
DAC_R 166 105 VDD_K2
DAC_VDD 167 104 M_D13
DAC_VSS 168 103 M_D14
R_A16 169 102 M_D15
R_A18 170 101 M_BA0
A_IEC_TX/GPIO 171 100 M_CS0_B/GPIO
A_DATA0/GPIO 172 99 VSS_O2/VSS_K2
VDD_O5 173 98 M_RAS_B
A_DATA1/GPIO 174 97 M_CAS_B
A_DATA2/GPIO 175 96 M_WE_B
A_DATA3/GPIO 176 95 M_D0
A_LRCK/GPIO 177 94 M_D1
VSS_K6/VSS_O6 178 93 M_D2
A_BCK/GPIO 179 92 VDD_O2
A_XCK/GPIO 180 91 M_D3
UA0_RX/GPIO 181 90 M_D4
UA0_TX/GPIO 182 89 M_D5
V_COMP 183 88 M_D6
V_BIAS
V_FSADJ
V_REFOUT
TV_DAC0
VDD_TVA0
184
185
186
187
188
SPHE8281D 87
86
85
84
83
M_D7
VDD_PLLV
VSS_PLLV
VDD_PLLA
VSS_PLLA
VSS_TVA0 189 82 USB_DM
VDD_TVA1
VSS_TVA1
TV_DAC3
190
191
192
8202D-216P 81
80
79
USB_DP
USB_VDD
USB_GND
TV_DAC4
VDD_TVA2
TV_DAC5
193
194
195
216 PIN LQFP 78
77
76
CLKOUT
CLKIN
R_A19
24x24mm2
VSS_TVA2 196 75 R_A20/E_MX10
PLL_AVDD 197 74 VFD_DATA/GPIO
LPFO 198 73 VFD_STB/GPIO
LPFN 199 72 VFD_CLK/GPIO
VREFO 200 71 IR_IN/GPIO
PDFLT 201 70 RST_B
FDFLT 202 69 R_CS1_B/GPIO
LPFNIN 203 68 R_CS2_B/GPIO
LGIN 204 67 R_CS3_B/GPIO
PLL_DS_AVSS 205 66 R_CS4_B/GPIO
RFI 206 65 GPIO
CNIN 207 64 VDD_O1
SLVL 208 63 GPIO/ttio3_7
DS_AVDD 209 62 GPIO/ttio2_6
RF_AVDD 210 61 GPIO/ttio1_5
GMRES 211 60 VSS_O1/VSS_K1
AGCCAP 212 59 GPIO/ttio0_4
RFRP 213 58 GPIO/TRAY_IS_OUT
RFO 214 57 GPIO/TRAY_IS_IN
FLTIP 215 56 VDD_K1
FLTIN 216 55 DFCT/GPIO
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
1
2
3
4
5
6
7
8
9
AGCON
DPDA
DPDB
DPDC
DPDD
DVDD
DVDC
DVDB
DVDA
CDB
CDA
APC_SRV_AVDD
R33K
RFRPPH
RFRPBH
RFRPMEAN
SBADPH
SBAD
OPVIN
SRV_AD_AVSS_VRGD
AD_DA_AVDD
AGCOP
DVDMDI
CDMDI
RFIP
RFIS
CDE
RF_AVSS
APC_AVSS
TEOLP
OPVIP
OPVOP
DA_AVSS
CDF
SVOTST
V21
V165
E_MX8
E_MX9
RFSUM
DVDLDO
CDLDO
FEO
TEO
DATEO
DAFEO
SPDC_OUT/GPIO
SC_OUT/GPIO
SC1_OUT/GPIO
TRAY_OUT/GPIO
DMEA/GPIO
FGIN/GPIO
HOMESW/GPIO
LDSW/GPIO
Figure 4-1 SPHE8281D pin
© Sunplus Confidential 7 MAY. 19, 2005
Contents are subject to change without Notice Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
4.2. Group Map
VSS_* LPFO LPFN
System VDD_* VREFO
Interface CLKIN / CLKOUT PDFLT
RSTB FDFLT
LPFNIN
Audio DAC_VREF LGIN
analog output DAC_L RFI
interface DAC_R CNIN
SLVL
AU_XCK GMRES
Audio AU_BCK AGCCAP
digital output AU_LRCK RFRP
interface AU_DATA[3:0] RFO
A_IEC_TX FLTIP FLTIN
AGCON AGCOP
RFIP RFIS RFSUM
R_CS_B[3:0] DPDA DPDB DPDC DPDD
R_OE_B DVDA DVDB DVDC DVDD
ROM/flash SERVO
R_WE_B CDB CDA CDF CDE
interface R_A[19:0] DVDLDO
R_D[7:0] CDLDO
DVDMDI
M_CLKO CDMDI
M_RAS_B
M_CAS_B
SPHE8281D R33K
V165
M_WE_B (216pin) SVOTST
M_CS0_B RFRPPH RFRPBH RFRPMEAN
SDRAM
M_BA0 SBADPH
interface M_BA1 SBAD
M_A11 FEO TEO
M_A[10:0] TEOLP
M_D[15:0] OPVIP
M_DQM[3:0] OPVIN
OPVOP
IR_IN VRGD
IR VFD_CLK DATEO DAFEO
VFD VFD_STB
UART VFD_DATA SPDC_OUT
GPIOs UA0_RX UA0_TX SC_OUT
Other GPIOs SC1_OUT
TRAY_OUT
V_COMP DMEA
V_BIAS FGIN
SERVO
V_FSADJ HOMESW
Video
V_REFOUT LDSW
output
V_DAC0 DFCT
interface V_DAC3 TRAY_IS_OUT
V_DAC4 TRAY_IS_IN
V_DAC5 ttio*
Figure 4-2 SPHE8281D pin groups
© Sunplus Confidential 8 MAY. 19, 2005
Contents are subject to change without Notice Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
4.3. Pin Description
Symbol Pin No. I/O Description
AGCON 1 O Differential AGC output #N
AGCOP 2 O Differential AGC output #P
RFIP 3 I Differential RF signal input #P
RFIS 4 I Single-ended RF equalizer input.
RFSUM 5 O RF summing amplified output.
DPDA 6 I AC coupled RF inputs for the DPD #A, from the main beam photo detector.
DPDB 7 I AC coupled RF inputs for the DPD #B, from the main beam photo detector.
DPDC 8 I AC coupled RF inputs for the DPD #C, from the main beam photo detector.
DPDD 9 I AC coupled RF inputs for the DPD #D, from the main beam photo detector.
DVDD 10 I DVD RF inputs #A, from the main beam photo detector.
DVDC 11 I DVD RF inputs #B, from the main beam photo detector.
DVDB 12 I DVD RF inputs #C, from the main beam photo detector.
DVDA 13 I DVD RF inputs #D, from the main beam photo detector.
CDB 14 I CD RF inputs #B, from the main beam photo detector.
CDA 15 I CD RF inputs #A, from the main beam photo detector.
CDF 16 I CD tracking error inputs #F, from the sub-beam photo detector.
CDE 17 I CD tracking error inputs #E, from the sub-beam photo detector.
RF_AVSS 18 S Servo RF ground
APC_AVSS 19 S Servo APC ground
DVDLDO 20 O DVD APC output.
CDLDO 21 O CD APC output.
DVDMDI 22 I DVD APC input from monitor photo diode.
CDMDI 23 I CD APC input from monitor photo diode.
APC_SRV_AVDD 24 S Servo APC and analog 3.3V power (216pin only)
V21 25 - Reference DC bias voltage.
R33K 26 - External reference resistor input.
V165 27 - Reference DC bias voltage.
SVOTST 28 O RF peak hold external capacitor
RFRPPH 29 O RFRP peak hold signal output.
RFRPBH 30 O RFRP bottom hold signal output.
RFRPMEAN 31 O RFRP mean signal output.
SBADPH 32 O Sub-beam adds peak hold signal output.
SBAD 33 O Sub-beam adds signal output.
FEO 34 O Focus error signal output.
TEO 35 O Tracking error signal output.
TEOLP 36 A
OPVIP 37 I Op-amp 1 positive input.
OPVIN 38 I Op-amp 1 negative input.
OPVOP 39 O Op-amp output.
SRV_AD_VRGD_AV 40 S Servo/ADC analog ground
SS
AD_DA_AVDD 41 S Servo ADC/DAC 3.3V power
DATEO 42 A
DAFEO 43 A
© Sunplus Confidential 9 MAY. 19, 2005
Contents are subject to change without Notice Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
Symbol Pin No. I/O Description
DA_AVSS 44 S Servo DAC ground
E_MX8 45 I/O GPIO [70]
Priority selection Function Dir
sft_cfg2[5:4] =2'b01 UA1_RXD I
sft_cfg7[5:4]=2'b11 656_DATA[0] O
sft_cfg1[11:9]=3'b110 RISC_INT1_11 I
sft_cfg7[1]= 1'b 0, FM_GPIOB [12] I/O
sft_cfg0[11]= 1'b 1,
fm_gpio_len[3:0]>8
sft_cfg0[11]= 1'b 0, FM_GPIOB [29] I/O
fm_gpio_len[3:0]=4'b1100
Sft_cfg8[5]= 1'b 1 TV_EXT_DATA_Cr[7] I
(other) GPIO[70](default) I/O
E_MX9 46 I/O GPIO[71]
Priority selection Function dir
sft_cfg2[5:4] =2'b01 UA1_TXD O
sft_cfg7[5:4]=2'b11 656_DATA[1] O
sft_cfg1[11:9]=3'b110 RISC_INT1_12 I
sft_cfg7[1]= 1'b 0, FM_GPIOB [13] I/O
sft_cfg0[11]= 1'b 1,
fm_gpio_len[3:0]>8
sft_cfg0[11]= 1'b 0, FM_GPIOB [30] I/O
fm_gpio_len[3:0]=4'b1100
Sft_cfg8[5]= 1'b 1 TV_EXT_DATA_Cr[6] I
(other) GPIO[71](default) I/O
SPDC_OUT/GPIO 47 I/O Servo SPDC_OUT
Priority selection Function dir
sft_cfg2[11:10]=2'b01,2'b10 AT_RESET_B O
sft_cfg4[0]=1'b1 SPDC_OUT (default) I/O
Sft_cfg8[9]=1'b1 DAC_PDF I
sft_cfg8[8]=1'b1 OTP_TEST_ADDR[0] I
(other) GPIO[0] I/O
SC_OUT/GPIO 48 I/O Servo SC_OUT
Priority selection Function dir
sft_cfg2[11:10]=2'b01,2'b10 AT_DIOR_B O
sft_cfg4[1]=1'b1 SC_OUT (default) I/O
Sft_cfg8[9]=1'b1 DAC_PDE I
sft_cfg8[8]=1'b1 OTP_TEST_ADDR[1] I
(other) GPIO[1] I/O
SC1_OUT/GPIO 49 I/O Servo SC1_OUT
Priority selection Function dir
sft_cfg2[11:10]=2'b01,2'b10 AT_DIOW_B O
sft_cfg4[2]=1'b1 SC1_OUT (default) I/O
Sft_cfg8[9]=1'b1 DAC_PDD I
sft_cfg8[8]=1'b1 OTP_TEST_ADDR[2] I
(other) GPIO[2] I/O
© Sunplus Confidential 10 MAY. 19, 2005
Contents are subject to change without Notice Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
Symbol Pin No. I/O Description
TRAY_OUT/GPIO 50 I/O Servo TRAY_OUT
Priority selection Function dir
sft_cfg2[11:10]=2'b01,2'b10 AT_IORDY I
sft_cfg4[3]=1'b1 TRAY_OUT (default) I/O
Sft_cfg8[9]=1'b1 DAC_PDC I
sft_cfg8[8]=1'b1 OTP_TEST_ADDR[3] I
(other) GPIO[3] I/O
DMEA_OUT/GPIO 51 I/O Servo DMEA
Priority selection Function dir
sft_cfg2[11:10]=2'b01,2'b10 AT_DMACK O
sft_cfg4[4]=1'b1 DMEA_OUT (default) O
Sft_cfg8[9]=1'b1 DAC_PDB I
sft_cfg8[8]=1'b1 OTP_TEST_ADDR[4] I
(other) GPIO[4] I/O
FGIN/GPIO 52 I/O Servo FGIN
Priority selection Function dir
sft_cfg2[11:10]=2'b01,2'b10 AT_DMARQ I
sft_cfg4[5]=1'b1 FGIN (default) I
Sft_cfg8[9]=1'b1 DAC_PDA I
sft_cfg8[8]=1'b1 OTP_TEST_PGM I
(other) GPIO[5] I/O
HOMESW/GPIO 53 IO Servo HOMESW
Priority selection Function dir
sft_cfg2[3:2]=2'b10 UA0_RXD I
sft_cfg1[8:6]=3'b010 R_CSALL_B O
sft_cfg7[7:6]=2'b11 PCMCIA_IOW_B O
Sft_cfg8[1]=1'b1 DSP_FL0 O
Sft_cfg8[9]=1'b1 DAC_DATA_F[9] I
sft_cfg9[14:13]=2'b01 EXT_CLK48 I
sft_cfg6[4]=1'b1 DELAY_CHAIN1 O
sft_cfg8[8]=1'b1 OTP_TEST_DATA O
(other) GPIO[6] (default) I/O
LDSW/GPIO 54 IO Servo LDSW
Priority selection Function dir
sft_cfg2[3:2]=2'b10 UA0_TXD O
sft_cfg2[5:4]=2'b10 UA1_RXD I
sft_cfg7[7:6]=2'b11 PCMCIA_IOR_B O
Sft_cfg8[2]=1'b1 DSP_FL1 O
Sft_cfg8[9]=1'b1 DAC_DATA_F[8] I
sft_cfg7[15:14]=2'b11 CLK27_OUT O
sft_cfg9[14:13]=2'b10 EXT_CLK48 I
sft_cfg6[4]=1'b1 DELAY_CHAIN2 O
(other) GPIO[7] (default) I/O
© Sunplus Confidential 11 MAY. 19, 2005
Contents are subject to change without Notice Preliminary Version: 0.1
Preliminary
SPHE8281D/Dx
Symbol Pin No. I/O Description
DFCT/GPIO 55 IO Servo DFCT
Priority selection Function dir
sft_cfg2[11:10]=2'b01,2'b10 AT_INTRQ I
sft_cfg4[6]=1'b1 DFCT (default) O
Sft_cfg8[9]=1'b1 DAC_DATA_F[7] I
(other) GPIO[8] I/O
VDD_K1 56 S Kernel logic power supply #1
GPIO/TRAY_IS_IN 57 IO GPIO
Priority selection Function dir
sft_cfg2[11:10]=2'b01,2'b10 AT_ADR[1] O
Sft_cfg8[3]=1'b1 DSP_FL2 O
fm_gpio_len[3:0] > 0 FM_GPIOB[0] I/O
Sft_cfg8[9]=1'b1 DAC_DATA_F[6] I
(other) GPIO[9] (default) I/O
GPIO/TRAY_IS_OUT 58 IO GPIO
Priority selection Function dir
sft_cfg2[11:10]=2'b01,2'b10 AT_ADR[2] O
Sft_cfg8[4]=1'b1 DSP_FLAG_OUT O
fm_gpio_len[3:0] > 0 FM_GPIOB[1] I/O
Sft_cfg8[9]=1'b1 DAC_DATA_F[5] I
(other) GPIO[10] (default) I/O
GPIO/ttio0_4 59 IO GPIO
Priority selection Function dir
sft_cfg2[11:10]=2'b01,2'b10 AT_ADR[0] O
sft_cfg4[9]=1'b1 ttio4/ttio0 I/O
Sft_cfg1[11:9]=3'b001 RISC_INT1_11 I
Sft_cfg3[11:10]=2'b01 ADC_BCK, digital audio I/O
input interface bit clock
fm_gpio_len[3:0] > 0 FM_GPIOB[2] I/O
Sft_cfg8[9]=1'b1 DAC_DATA_F[4] I
(other) GPIO[11] (default) I/O
VSS_O1/ VSS_K1 60 S Kernel logic / I/O power shared ground supply #1
GPIO/ttio1_5 61 IO GPIO
Priority selection Function dir
sft_cfg2[11:10]=2'b01,2'b10 AT_CS1 O
sft_cfg4[9]=1'b1 Ttio5/ttio1 I/O
sft_cfg4[15:13]=3'b001 HSYNC_PC O
Sft_cfg1[11:9]=3'b001 RISC_INT1_12 I