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APPLICATION NOTE IC
Micronas
SDA 55xx TVText Pro Design Guide
Edition March 20, 2003 6251-556-2-2AN
MICRONAS
SDA 55xx
Contents Page 1 1 1 2 2 3 4 4 4 5 5 6 6 6 7 8 8 8 8 9 9 9 12 Section 1. 2. 2.1. 2.2. 2.3. 2.3.1. 2.4. 2.5. 2.6. 2.7. 2.8. 2.9. 2.10. 2.11. 3. 4. 4.1. 4.2. 4.3. 5. 5.1. 5.2. 6. Title Introduction Hardware Items Filtering of Power Supply Oscillator Slicer Performance Group Delay Filter How to Adjust the Correct CVBS Amplitude RGB Output Contrast Reduction I2C Bus Application with 124 and 252 Pages Teletext Application Circuit OSD-only Version (SDA 552x) Sync Master Mode How to Order 128 kByte ROM Mask Development Tools Flash Programming Tools for SDA 555xFL OSD and Character Editor TEDI PRO Emulation and Compiler Important Changes Pin Configuration Memory Access Time Application Note History
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APPLICATION NOTE IC
SDA 55xx
2. Hardware Items 2.1. Filtering of Power Supply
TVText Pro Design Guide
1. Introduction The purpose of this application note is to give a brief overview of the most important hardware aspects of the TVText Pro, e.g. slicer performance, oscillator, and hardware design. The TVText Pro requires two different power supply voltages. The 3.3-V supply is used to drive all port pins and address/data lines. The 2.5 V is used for the CPU core and the analog units of the TVText Pro. It is important for the hardware designer to take special note of the stability and noise on the 2.5-V domain. To avoid interference on the power supply lines and improve the analog performance (e.g. slicer, ADC) of the TVText Pro, it is recommended to divide the power supply into different sections, which are separated from each other by LC-filters. The number of power supply pins assigned to the different power supply sections depends on the package type of the TVText Pro. The tables below show pin assignments for the voltage domains in each of the four available package types. Table 21: Power sections (1) Power Section Supplied Module VDD 2.5 V CORE 2.5 V ANALOG1 2.5 V ANALOG2 3.3 V DIGITAL1 3.3 V DIGITAL2 CPU, pad input stage ADC, slicer, SC-Decoder DAC (RGB), PLL, oscillator Port 0, Port 1, COR/BLANK VSYNC, Port 3, Port 4.2..3 9, 42 13 37 11, 44 30 PSDIP52-1 VSS 10, 43 14 36 10, 43 29 VDD 3, 44 9 37 5, 46 29 PMQFP64-1 VSS 4, 45 10 36 4, 45 28
Table 22: Power sections (2) Power Section Supplied Module PMQFP100-1 VDD 2.5 V CORE 2.5 V ANALOG1 2.5 V ANALOG2 3.3 V DIGITAL1 3.3 V DIGITAL2 CPU, pad input stage ADC, slicer, SC-Decoder DAC (RGB), PLL, oscillator Port 0, Address/Data, COR/BLANK, Port 1.7 VSYNC, Port 3, Port 4.2..3, Port 1 6, 73 22 56 8, 92, 75 40 VSS 7, 74 23 55 7, 91, 74 39 VDD 14, 68 26 57 1, 16, 70 43 PLCC84-1 VSS 15, 69 27 56 84, 15, 69 42
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2.2. Oscillator In order to gain maximum slicer performance, a 6.000 MHz quartz crystal with a frequency tolerance of ±100 ppm (over-all) should be used. This crystal is used to generate the CPU clock, screen pixel clock for OSD, sync. clock, and the clock frequency for the teletext slicer. Resonator components (e.g. ceramic resonators) with higher tolerance may be used if the teletext slicer is not used (e.g. in OSD-only application). The recommended quartz crystal circuit is shown in Fig. 21. For quartz crystal applications, 33 pF capacitors should be used. 2.3. Slicer Performance
APPLICATION NOTE IC
The performance of the teletext slicer depends on several parameters. The performance of the slicer may be significantly improved if attention is paid to these parameters. The digital slicer on the TVText Pro uses a fast analogto-digital converter to digitize the CVBS signal. Noise and interference on the power supply to the slicer should be minimized by using filters and a large ground plane. In addition, analog signal lines should be shielded, for example by power lines. Place a ground plane under the TVText Pro device. Note recommendations for filtering of power supply lines. In particular, the 2.5 V power supply voltage should be designed to be as stable and noise-free as possible. Place a 100 nF capacitor (SMD) at each power supply pin pair, as close as possible to the device pins. Note recommendations for the crystal oscillator design.
Note: The connection to the analog GND (VSSA) should be as short as possible.
VSSA 33 pF
Keep fast switching signals (e.g. altering levels of port pins, address/data lines) away from CVBS signal and Port 2. The optimal CVBS amplitude is about 950 mV. The amplitude must be measured with a norm signal from H-Sync bottom to the maximum peak of the Clock-Run-In signal (CRI: first incoming pulses of a TEXTEXT signal).
XTAL1 6 MHz
XTAL2
33 pF
The maximum voltage level of the H-Sync or Sandcastle signal must not exceed 2.5 V. To improve the slicer performance on signals which have a negative group delay component, an additional external group delay filter is recommended as described in the section "Group Delay Filter".
Fig. 21: Oscillator circuit
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APPLICATION NOTE IC
SDA 55xx
The output of the filter must be connected by a serial 100 nF decoupling capacitor to the CVBS pin of the TVText Pro. The input of the filter must be from a CVBS source with an impedance less than 500 . For fine adjustment of the filter output voltage, the resistor R1 may vary between 2.2 k and 4.7 k. This will also effect the group delay behavior slightly. A stable power supply voltage between 8 V and 9 V is recommended. The group delay response of the filter is shown in Fig. 23.
2.3.1. Group Delay Filter The acquisition performance of the full data service slicer for CVBS signals with group delay ranging from 150 ns to 170 ns can be further improved by the addition of a filter in the CVBS signal path. This additional filter should add positive group delay compensation of approximately 60-80 ns; this will move the signal into a more optimal area for acquisition. Although the above is application dependent (tuner & IF performance), the below circuit can be used to delay the CVBS signal by 60-80 ns in range from1 to 3.5 MHz.
Fig. 22: Circuit diagram of a group delay compensation filter
100ns
80ns
60ns
40ns
20ns 0Hz 0.4MHz VG(C3:2 )
0.8MHz
1.2 MHz
1.6MHz
2.0 MHz
2.4MHz
2. 8MHz
3.2MHz
3.6MHz
Frequency
Fig. 23: Group delay response of the filter
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2.4. How to Adjust the Correct CVBS Amplitude
APPLICATION NOTE IC
After the TVText Pro is reset, the BLANK/COR pin is configured as BLANK output by default. The COR function is switched off. The COR-BLANK function must be switched on by software. If the application requires a separate BLANK and COR signal, an external decoder circuit is needed to separate the COR and the BLANK signal out of the three-level signal as shown in Fig. 26. An appropriate COR-BLANK decoder circuit is shown in Fig. 27.
Fig. 24: Track 1: filter input signal / Track 2: filter output signal (950 mV)
Fig. 24 shows a CVBS signal at the input of the group delay filter [1] and the signal at the output of the filter [2] resp. at the CVBS pin of the TVText Pro. The rear part of the H-sync, eight Clock-Run-In pulses, and the front part of the framing code of a TELETEXT line are visible. The signal amplitude at the filter input must be high enough (about 1.5 V) to enable an output voltage of 950 mV (as shown in Fig. 25) measured with CVBS signal from H-Sync bottom to the maximum peak of the Clock-Run-In signal (CRI: first incoming pulses of a TEXTEXT signal).
Fig. 25: Voltage level definition of COR-BLANK signal
2.5. RGB Output Fig. 26: COR-BLANK decoder The RGB output of the TVText Pro can display 4096 color combinations. The maximum peak-to-peak amplitude (black-to-white level) can be set to 0.5 V, 0.7 V, 1.0 V, and 1.2 V. Because of a small non-linearity at the black level, 0.5 V and 0.7 V should not be used in high-end applications. For designs that require peak-to-peak amplitude of 0.5 V or 0.7 V, the output should be set to 1 V and a resistor voltage divider used. The load at each output must be greater than 5 k.
COR/BLANK 10.0
3.3 V 4.7 * = Philips 74LV32N
>=1
COR 3.3 18 pF a*
>=1
2.6. Contrast Reduction The TVText Pro has a three-level output pin for a combined BLANK and contrast reduction signal similar to the sandcastle signal, which also combines H-sync and V-sync together into one signal. This three-level COR-BLANK signal can be easily connected directly to Micronas' Deflection Controller with RGB Processor SDA 9380 (EDDC) to realize fast blanking and contrast reduction by using only one line.
BLANK b*
Fig. 27: Application circuit for COR-BLANK decoder
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APPLICATION NOTE IC
SDA 55xx
To connect the I2C bus lines to I2C bus devices with 5 V interface, a voltage level shifter is needed. An example circuit for a level shifter using an SN7000/ SN7002 (Infineon Technologies) is shown in Fig. 28.
2.7. I2C Bus The TVText Pro has no hardware I2C bus interface. The I2C bus protocol must be generated by software. The I2C bus output stages of the TVText Pro connected to the SCL and SDA lines must have an opendrain structure in order to perform the wired-AND function. Therefore, any pins of Port 0 of the TVText Pro may be used as I2C bus pins. TVText Pro does not support I2C-specific I/O voltages, so care must be taken to ensure that the I2C bus voltage levels conform to the TVText Pro specification. Note especially that the input low voltage must be below 0.8 V.
2.8. Application with 124 and 252 Pages Teletext Fig. 28 and Fig. 29 are circuit diagrams for a 124 and 252 Teletext page application implemented using a ROMless TVText Pro in either a PLCC84-1 or a PMQFP100-1 package. Firmware for 1, 10, or 252 page Teletext acquisition can be obtained from Micronas. The 252-page Teletext acquisition firmware is scalable from 28 to 252 pages.
+3.3 V
+5 V
R1 SDA or SCL S
G
T1 SN7000 R2 SDA or SCL D
3.3 V device
5 V device
Fig. 28: I2C bus level shifter
A0-A19
A0-A19
A15
CS1
SDA 5550
LCC-84 MQFP-100
RD (P4.2) WR (P4.3)
OE WE D0-D7
1 Mbit SRAM 128k x 8 Bit (< 230 ns)
A0-A14 A15 A16
A0-A14 A16 A17
D0-D7
D0-D7
PSEN
OE CE
8 Mbit EPROM A0-A19 FLASH 1M x 8 Bit (< 115 ns)
A0-A19
Fig. 29: 124-page teletext application
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SDA 55xx
APPLICATION NOTE IC
A0-A19
A0-A19
A15
CS1
SDA 5550
LCC-84 MQFP-100
RD (P4.2) WR (P4.3)
OE WE D0-D7
2 Mbit SRAM 256k x 8 Bit (< 230 ns)
A0-A14 A15 A16 A17
A0-A14 A16 A17 A18
D0-D7
D0-D7
PSEN
OE CE
8 Mbit EPROM A0-A19 FLASH 1M x 8 Bit (< 115 ns)
A0-A19
Fig. 210: 252-page teletext application
2.9. Application Circuit
2.10. OSD-only Version (SDA 552x) The OSD-only version of the TVText Pro provides the same features as the non OSD-only version with the below documented differences. The OSD-only has no Slicer and acquisition functionality Acquisition H-sync interrupt
PSEN
SDA 5550 only
Up to 1 Mbyte Program Memory (< 115 ns)
8 bit Data Bus
Address Bus
Acquisition V-sync interrupt Line23 interrupt
2 x 33 pF
XTAL1
6 MHz
R G
R (0.5 Vpp ...1.2
Vpp)
Channel change interrupt. The functionality of your OSD-only software can be tested with a TVText Pro FLASH (SDA 555xFL) version by leaving the CVBS pin open. Of course, the test has to be done with the correct memory configuration, because the SDA 555xFL provides more memory than the OSD-only version.
G (0.5 Vpp ...1.2 Vpp) B (0.5 Vpp ...1.2 Vpp) BLANK
8 (3.3V)
XTAL2 Sandcastle
(max. 2.5 V)
B BLANK/ COR
HS/SC
Port 0 +3.3 V RST#
8
TVTEXT PRO SDA 55xx
Port 1
4
Port 2
8 3...6 V)
(max. 2.5
Port 3 +3.3 V VDD3.3 Port4
2.11. Sync Master Mode TVText Pro provides a sync master mode, where the H/V-sync signals are delivered by TVText Pro. These sync signals are not synchronized to any other signals like CVBS. The H/V sync master mode is enabled if the bit MAST in register SCR0 is set to "1". The V-sync signal is delivered at the V-sync pin and the H-sync signal can be seen at P3.5 (instead of the H-sync pin). To enable the V-sync signal, the bits P4_7#_Alt and VS_OE# in register CSCR0 must also be set to "1".
+2,5 V
VDD2.5
(DAC, oscillator)
+2,5 V
VDD2.5
(ADC, slicer)
CVBS
100n F
CVBS
(1.2 Vpp)
Fig. 211: Typical application
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APPLICATION NOTE IC
SDA 55xx
Example of a none-code banking program (the code size is within 64 kByte): Linking: L51 @lk.dat (the linker output file is e.g. P073V180) Object-Hex Converter: OH51 p073V180 The ROM mask file is now: P073V180.hex
3. How to Order 128 kByte ROM Mask The BL51 code banking linker/locator takes the userspecified object files and library files and generates either an absolute object file or a banked object file. An absolute object file is generated for a none-code banking program. A banked object file is generated for a code banking program. The BL51 code banking linker/ locator also generates a listing or map file. Absolute object files may be converted into Intel HEX files by the OH51 Object-Hex Converter. Banked object files must be converted by the OC51 Banked Object File Converter into absolute object files (one for each bank) before they can be converted into Intel HEX files by the OH51 Object-Hex Converter (part of the KEIL Software Manual: 8051 Utilities).
Example of a code banking program (code size is within 128 kByte or 2 banks): Linking: bl51 @blk.dat (the linker output file is e.g. P090V003) Banked Object File Converter: OC51 P090V003 The result is 2 files with the name P090V003.B00 and P090V003.B01 Object-Hex Converter Bank 0: OH51 P090V003.B00 RENAME P090V003.hex P090V003.H00 Object-Hex Converter Bank 1: OH51 P090V003.B01 RENAME P090V003.hex P090V003.H01 The ROM mask file0 for bank 0 (0-64kByte) is now: P090V003.H00 The ROM mask file1 for bank 1 (64-128kByte) is now: P090V003.H01
Note: The KEIL converters OH51 and OC51 from the compiler package 5 are DOS tools. Use Windows 3.11 directory and file naming conventions.
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4. Development Tools 4.1. Flash Programming Tools for SDA 555xFL There are two different programming systems for the flash version of TVText Pro: a single programming system and a gang programming system. The single programmer can be used for development purposes and pre-series with low quantities. The gang programmer is a modular programming system for production sites. For further questions please contact "ertec" or refer to their internet home page: ertec GmbH Am Pestalozziring 24 D-91058 Erlangen Phone: ++49 (9131) 7700-0 Fax: ++49 (9131) 7700-10 E-mail: [email protected] Internet: http://www.ertec.com
APPLICATION NOTE IC
The current version of TEDI PRO is V1.02.1 (May 2000). Required equipment for the Dual Monitor system together with SDA 55xx Evaluation Board: TEDI PRO software running on a PC under Microsoft Windows 95/98/NT LPT port of PC connected to target system e.g. TVText Pro Evaluation Board B010-V002 via parallel printer cable I2CSLAVE software running on TVText Pro
4.3. Emulation and Compiler The same software tools (C51-Compiler, Linker/Locator and Assembler) used for TVText, TVText-2 or TVText Plus designs may be used for TVText Pro applications. The Teletext firmware object files provided by Micronas are compiled with tools from KEIL. Other compilers are not supported. The Kleinhenz emulator requires a KSC configurator (probe card) with TVText Pro, which can be used with a KSC X52 emulator. Suitable emulators are also available from HITEX (MX51-BH or AX51-H). The adapter probe is the modified type PVMUXCON. Both emulators have been tested with up to two memory banks using the KEIL Compiler/Linker.
4.2. OSD and Character Editor TEDI PRO TEDI PRO is a software application for simulating the SDA 55xx display features and for editing SDA 55xx displays files on a PC running Microsoft Windows 95/ 98/NT. TEDI PRO is a powerful tool used to generate OSD-characters and OSD-menus, to export them, and to integrate them into the target application. Using the dual monitor feature, you can explore the features of the TVText Pro on a target system and evaluate the visual appearance of your OSD. Main focus is the easy handling of display objects such as fonts, colors, and register settings.
Table 41: Flash programming tools System Single Programming System PGS53 No. of Devices 1 What is needed? PGS53A: Base Set for DIP packages AD555: Adapter for SDA 555xFL in PSDIP52-1 package AD555E: Adapter for SDA 555xFL in PSDIP52-1 package
Gang Programming System PGS67
4-16
PGS67001: Base Set PGS67673: Module for 4 devices SDA 555xFL in PSDIP52-1 package
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SDA 55xx
5.2. Memory Access Time The access times for code and data memory have been changed from those shown in the SDA 55xx User's Manual Version 1.3 or older. The new timing values can be found in Table 51. Table 51: Change of timing values
5. Important Changes 5.1. Pin Configuration The pin configuration of the PMQFP64-1 package has been modified from that shown in the SDA 55xx User's Manual Version 1.3 or older. The new pin configuration is shown in Fig. 51.
P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2
P0.6
P1.1
Page 226
P1.0 VDD 3.3 VSS VDD 2.5 BLANK / COR
Parameter tAVIV tAVDV
Old Value 120 ns 240 ns
New Value 115 ns 230 ns
1
48
P0.7 VDD 2.5 VSS VDD 3.3 CVBS VDDA 2.5 VSSA P2.0 P2.1 P2.2 P2.3 HS / SSC
227
16
33
B G R VDDA 2.5 VSSA XTAL1 XTAL2
This means, that the access times of the memory devices for the code memory (EPROM/Flash) must be less than 115 ns instead of 120 ns and for the data memory (SRAM) must be less than 230 ns instead of 240 ns.
Fig. 51: Pin configuration of TVText Pro in PMQFP64-1
Micronas
P3.6 P3.7 VSS VDD 3.3 P4.2 P4.3 RST_N
VS P3.0 P3.1 P3.2 P3.3 P3.4 P3.5
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6. Application Note History 1. Application Note "SDA 55xx TVText Pro Design Guide Version 1.0", Edition June 7, 2000. First release of the application note. 2. Application Note IC: "SDA 55xx TVText Pro Design Guide", Oct. 9, 2001, 6251-556-1AN. Second release of the application note IC. Major changes: In Table 21: OSD-only version added Section 2.3.: definition of "optimal CVBS amplitude" has been changed Section 2.3.1. Group Delay Filter added Section 2.10. OSD-only Version added Section 2.11. Sync Master Mode added 3. Application Note IC: "SDA 55xx TVText Pro Design Guide", March 20, 2003 , 6251-556-2-2AN. Third release of the application note IC. Major changes: Section 2. Device Overview omitted. Flash version only in PSDIP52-1 package available. PMQFP64 package is no longer available for SDA 555xFL.
APPLICATION NOTE IC
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: [email protected] Internet: www.micronas.com Printed in Germany Order No. 6251-556-2-2AN
All information and data contained in this document are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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