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l GY tia O n L e O C id N IN f n H E o C SPCE8200A IS SPH E sVD SinTle Chip DPEG AYV luD C g N M L / p ProIcessor A N n N H u N C O S U R SE S E U r M o & F
Preliminary
OCT. 07, 2003 Version 0.2
SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice.
is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus. No responsibility is assumed by In addition, SUNPLUS products
are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may
DATA SHEET
Information provided by SUNPLUS TECHNOLOGY CO.
Preliminary
SPHE8200A
Table of Contents
PAGE
1. GENERAL DESCRIPTION...................................................................................................................................................................... 4 2. FEATURE ............................................................................................................................................................................................... 5 3. BLOCK DIAGRAM.................................................................................................................................................................................. 6 4. SIGNAL DESCRIPTION.......................................................................................................................................................................... 7 4.1. PIN MAP ........................................................................................................................................................................................... 7 4.2. GROUP MAP ..................................................................................................................................................................................... 8 4.3. PIN DESCRIPTION .............................................................................................................................................................................. 9
5. FUNCTIONAL DESCRIPTIONS............................................................................................................................................................ 18 5.1. PLL AND CLOCKGEN ....................................................................................................................................................................... 18 5.2. POWER CONTROL ........................................................................................................................................................................... 18 5.3. EMBEDDED 32-BIT RISC CONTROLLER ............................................................................................................................................. 18 5.4. RISC INTERFACE ............................................................................................................................................................................ 19 5.5. ROM/FLASH/SRAM CONTROLLER.................................................................................................................................................... 20 5.6. RISC MEMORY INTERFACE .............................................................................................................................................................. 20 5.7. PERIPHERAL CONTROL INTERFACE ................................................................................................................................................... 20 5.8. CSS/CPPM SUPPORT ..................................................................................................................................................................... 20 5.9. MPEG VIDEO DECODER .................................................................................................................................................................. 20 5.10.GRAPHICS ENGINE BONDYPRO®...................................................................................................................................................... 21 5.11. VIDEO POST PROCESSING ............................................................................................................................................................... 21 5.12.AUDIO DSP .................................................................................................................................................................................... 21 5.13.AUDIO INTERFACE ........................................................................................................................................................................... 22 5.14.INTEGRATED AUDIO QUALITY ADC .................................................................................................................................................... 22 5.15.I/O PROCESSOR.............................................................................................................................................................................. 22 5.16.SDRAM CONTROLLER .................................................................................................................................................................... 22 5.17.SUB-PICTURE DECODER .................................................................................................................................................................. 22 5.18.ON SCREEN DISPLAY ....................................................................................................................................................................... 22 5.19.DISPLAY INTERFACE ......................................................................................................................................................................... 22 5.20.VIDEO DAC .................................................................................................................................................................................... 23 5.21.ATAPI INTERFACE ........................................................................................................................................................................... 23 5.22.GPIO ............................................................................................................................................................................................. 23 5.23.UART ............................................................................................................................................................................................ 23 6. ELECTRICAL SPECIFICATIONS ......................................................................................................................................................... 24 6.1. ABSOLUTE MAXIMUM RATINGS ......................................................................................................................................................... 24 6.2. DC OPERATING CONDITIONS............................................................................................................................................................ 24 6.3. CAPACITANCE.................................................................................................................................................................................. 24 6.4. AC CHARACTERISTICS..................................................................................................................................................................... 25 6.4.1. SDRAM interface timing diagrams ...................................................................................................................................... 25 6.4.2. ROM / flash interface timing diagrams................................................................................................................................. 26 6.4.3. Audio interface timing diagrams .......................................................................................................................................... 27 6.4.4. Video timing diagrams......................................................................................................................................................... 28 7. REGISTER LIST ................................................................................................................................................................................... 30 8. PACKAGE/PAD LOCATION ................................................................................................................................................................. 38 © Sunplus Technology Co., Ltd. Proprietary & Confidential 2 OCT. 07, 2003 Preliminary Version: 0.2
l GY tia O n L e O C id N IN f n H E o C C E IS s T D Y lu C N L p I n N HA N u N C O S U R SE S E U r M o & F
Preliminary
SPHE8200A
8.1. OUTLINE DIMENSIONS ...................................................................................................................................................................... 38 9. DISCLAIMER........................................................................................................................................................................................ 39 10. REVISION HISTORY............................................................................................................................................................................. 40
l GY tia O n L e O C id N IN f n H E o C C E IS s T D Y lu C N L p I n N HA N u N C O S U R SE S E U r M o & F
© Sunplus Technology Co., Ltd. Proprietary & Confidential
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Preliminary
SPHE8200A
DVD SINGLE CHIP MPEG A/V PROCESSOR
1.GENERAL DESCRIPTION
SPHE8200A A/V decoder is a single-chip integrated DVD A/V decoder. sources. 11172 MPEG1 and 13818 MPEG2 stream for multiple bitstream
SPHE8200A supports DVD-Video, DVD-Audio, Super Video CD, Video CD, CD-DA, HDCD, OKO, CD-ROM different disc formats.
SPHE8200A is designed to maximize system performance with
minimum cost. For typical DVD application it integrates DVD/CD quality ADC, with high quality 5.1ch Audio, or low cost 2-ch AC3 system.
servo controller, multi-channel multi-format TV-encoder and audio
Application utilizing the SPHE8200A is presented below:
l GY tia O n L e O C id N IN f n H E o C C E IS s T D Y lu C N L p I n N HA N u N C O S U R SE S E U r M o & F
It performs real-time decoding and playback of ISO/IEC PCM, LPCM, WMA audio playback. high-performance progressive-scan DVD audio sound effects for Karaoke. programming guide and system application libraries.
IR
SPHE8200A supports Dolby Digital, DTS, MPEGI/II Layer1/2 ,
SPHE8200A also combines all the functions required for a system. Built-in de-interlacing hardware allows high quality DVD playback. The embedded digital audio decoder is able to support key control and
In additional to that SPHE8200A includes a flexible 2D graphics engine for high quality user interface and other applications. Complex application could be built using this platform easily. Development tools of SPHE8200A include complete compiler tools,
VFD front panel
6-ch video output
SPHE8200A
DVD-loader
RF
2~10 ch
Audio DAC
Audio amplifier
SDRAM
ROM
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SPHE8200A
2.FEATURE
Single Chip Integrated DVD Servo and A/V Decoder Integrated DVD/CD Servo Controller -- Support 1x ~ 2x DVD format reading -- Support 1x ~ 16x CD format reading -- Support up to 4 SDRAM devices -- Support 16M/64M/128M/256M SDRAM devices Graphics -- Embedded 2D Graphics Accelerator -- BitBlt, line, triangle drawing support
Embedded 32-bit RISC Processor without external host controller Embedded Audio Processor supports multiple audio standards control
Embedded I/O processor supports programmable interface
Embedded TV encoder with multi-channel built-in high-speed video DAC supports various display standards Embedded audio ADC supports stereo analog audio input required from single 27MHz input -- DVD Navigation 1.0 -- DVD audio -- OKO disc
Built-in system PLL and audio PLL generate all clock sources Support following disc format:
CSS/CPPM hardware
Video Decoder
Sub-picture Decoder
Audio Decoder
l GY tia O n L e O C id N IN f n H E o C C E IS s T D Y lu C N L p I n N HA N u N C O S U R SE S E U r M o & F
Display -- De-interlacing of interlaced video source -- Flexible vertical interpolation -- Powerful cropping and panning effect format OSD -- Multiple OSD regions with different formats -- Support 4/16/256 indexed color -- Support 16/24-bit direct color -- Support x2/x3/x4 horizontal scaling -- SVCD (Chaoji VCD) -- VCD 2.0/1.1/1.0 -- CDDA / HDCD Embedded TV encoder -- Simultaneous multi-channel output -- Support 480i/480p/576i/576p format -- Support CVBS output -- Support 640x480 VGA / 800x600 SVGA format -- CDROM (game, WMA and JPEG disc) -- Built-in CSS hardware -- Built-in CPPM C2_DCBC and C2_D/C2_D function protection Interface -- Real time MPEG2 MP@ML decoding -- 27MHz crystal driver -- Real time MPEG1 D1 (720x480x30 /720x576x25) decoding -- Hardware accelerated JPEG decoding -- Advanced decoding and display control -- 16/32-bit SDRAM interface -- UART ports -- 8/16-bit ROM/FLASH/SRAM interface -- IR and VFD support -- Advanced Sub-Picture Decoder for DVD SVCD and OKO -- Support hardware vertical scaling -- Video DAC analog output -- Simultaneous 10-channel audio DAC output -- IEC958/SPDIF digital input / output -- Analog audio input -- External ADC digital input interface (optional) -- Optional ATAPI and I2S interface support -- Optional Parallel Port interface support Low power -- Advanced low power design -- Selective standby mode -- Programmable low speed operation Technology -- Advanced CMOS technology -- 216pin LQFP package -- 3v (I/O) and 1.8v (kernel) power supplies -- 5v I/O tolerance 5 -- Flexible Programmable DSP Architecture -- Embedded high resolution audio quality ADC -- Support CDDA, HDCD, and DVD-Audio -- Support LPCM, PCM, and WMA playback -- Support MPEGI/II layer 1/2 and MPEG 2.5 playback (with optional down-mixing) -- Support Dolby Digital AC3 5.1ch / DTS 5.1ch playback (with optional down-mixing) -- Support Key Shift of 2 channels -- Support equalization, reverb and special sound field
-- Flexible horizontal interpolation with optional CIF filter -- Support YUV422, 8-bit indexed color or 16-bit direct color
-- Support SVideo, Component (YUV / YPbPr) or RGB output -- Macrovision 7.01 and Macrovision AGC v1.03 copy
SDRAM controller -- High Performance SDRAM controller -- Support 16 or 32 bit operation © Sunplus Technology Co., Ltd. Proprietary & Confidential
OCT. 07, 2003 Preliminary Version: 0.2
Preliminary
SPHE8200A
3.BLOCK DIAGRAM
l GY tia O n L e O C id N IN f n H E o C C E IS s T D Y lu C N L p I n N HA N u N C O S U R SE S E U r M o & F
EPROM/SRAM
EPROM/ SRAM interface
RISC
PLLv PLLa
Power control
icache dcache
Servo ECC
loader inf.
Graphics Engine DMA Engine
Intr. control Timer
loader RF input
SDRAM /16 or /32
SDRAM controller
OSD decoder
I/O processor GPIO
IR/VFD/(I2C)
Video postprocessing Video encoder
Audio DSP
Sub-picture decoder
UART ADC
UART / smartcard
icache
mem
Audio Analog In DAC digital out IEC 958 I/O
Video output
Video DAC
CSS/ CPPM
MPEG video decoder
Audio Interface
ADC digital in
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SPHE8200A
4.SIGNAL DESCRIPTION
4.1. Pin Map
© Sunplus Technology Co., Ltd. Proprietary & Confidential
DSRSET CNIN SLVL SVDD RFO SVSS RFRP RFRPLP TEXOLP TEXO ADVDD TEI FEI CSI SBAD VREF VRGD ADVSS SRV_SCLK SRV_SDATA SRV_SDEN SRV_DFCT T_PLCK VDD_K0 T_SLRF GPIO/TDM_DX/ttin0_4 GPIO/TDM_CLK/ttio1_4 GPIO/TDM_FSXR/ttio2_6 R_CS4_B/GPIO/TDM_DR/ttio3_7 VSS_K0 GPIO VDD_O0 RST_B R_A8 R_A9 VSS_O0 R_A10 R_A11 R_A12 R_A13 R_A14 VDD_K1 R_A15 R_D7 R_D6 R_D5 VSS_K1 R_D4 R_D3 R_D2 R_D1 R_D0 R_A0 R_A1
l GY tia O n L e O C id N IN f n H E o C C E I SPHE8200AS s T D Y lu C N L p I n N HA N u N C O S U R SE S E U r M o & F
A_DATA4/GPIO A_IEC_RX/GPIO A_IEC_TX/GPIO A_DATA0/GPIO VDD_O7 A_DATA1/GPIO A_DATA2/GPIO A_DATA3/GPIO A_LRCK/GPIO VSS_K6/VSS_O7 A_BCK/GPIO A_XCK/GPIO UA0_RX/GPIO UA0_TX/GPIO VDD_K6 V_COMP V_BIAS V_FSADJ V_REFOUT TV_DAC0 VDD_TVA0 VSS_TVA0 TV_DAC1 TV_DAC2 VDD_TVA1 VSS_TVA1 TV_DAC3 TV_DAC4 VDD_TVA2 VSS_TVA2 TV_DAC5 PWM_VDD TRAY_OUT SC1_OUT SPDC_OUT SC_OUT DMEA FGIN PWM_VSS DAVSS TEO FEO DAVDD HGIN LGIN2 LGIN1 LPFNIN PDFLT1 FDFLT VREFO PLLVDD PDRSET FDRSET PLLVSS 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VSS_ADA VDD_ADA VM AIN_R/AI_DATA ATO/AI_LRCK AIN/AIN_L/AI_BCK VFD_DATA/TDM_CLK VFD_STB/TDM_FSX VFD_CLK/TDM_DX IR_IN/TDM_DR VSS_O6 M_A12/GPIO GPIO GPIO GPIO VDD_O6 GPIO GPIO GPIO GPIO VSS_K5 GPIO M_DQM2/GPIO M_DQM3/GPIO GPIO VDD_K5 R_A26/GPIO R_A25/GPIO R_A24/GPIO R_A23/GPIO VSS_O5 R_A22/GPIO R_A21/GPIO R_A20/GPIO VDD_O5 M_A3 M_A2 M_A1 VSS_K4 M_A0 M_A10 M_BA1/GPIO VDD_K4 M_DQM0 M_DQM1 M_A4 VSS_O4 M_A5 M_A6 M_A7 VDD_O4 M_A8 M_A9 M_A11/GPIO
216 PIN LQFP 24x24mm2
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
M_CKE VSS_K3 M_CLKO VDD_O3 M_D8 M_D9 M_D10 M_D11 VSS_K3 M_D12 M_D13 M_D14 M_D15 VDD_K3 M_BA0 M_CS_B M_RAS_B M_CAS_B VSS_O2 M_WE_B M_D0 M_D1 M_D2 VDD_O2 M_D3 M_D4 M_D5 M_D6 M_D7 VSS_K2 CLKIN CLKOUT VDD_K2 VSS_PLLA VDD_PLLA VSS_PLLV VDD_PLLV R_CS3_B/GPIO R_CS2_B/GPIO R_CS1_B/GPIO R_WE_B/GPIO R_OE_B/GPIO R_A19/GPIO R_A18 R_A17 VSS_O1 R_A16 R_A7 R_A6 R_A5 R_A4 R_A3 R_A2 VDD_O1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
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4.2. Group Map
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System Interface
VSS_* VDD_* CLKIN RSTB TESTMODE
ADC analog interface
AIN_L/MIC AIN_R ATO VM
ADC digital input
AUI_BCK AUI_LRCK AUI_DATA
Audio digita l output interface
AU_XCK AU_BCK AU_LRCK AU_DATA[3:0] AU_IEC_TXRV
SPHE8200A (216pin)
ROM Flash interface
R_A[21:0] R_D[7:0] R_CS_B[3:0] R_WE_B R_OE_B R_WP_B IO_CHRDY
TEO FEO HGIN LGIN1 LGIN2 LPFNIN PDFLT1 FDFLT VREFO PDRSET FDRSET DRESET CNIN SLVL RFO RFRP RFRPLP TEXOLP TEXO TEI FEI CSI SBAO VREF VRGO
SERVO
SDRAM interface
M_CLKO M_RAS_B M_CAS_B M_WE_B M_CS_B M_BA[1:0] M_A[11:0] M_D[31:0] M_DQ M[3:0]
TRAY_OUT SC1_OUT SPDC_OUT SC_OUT DMEA FGIN SRV_SCLK SRV_SDATA SRV_SDEN SRV_FDCT T_PLCK T_SLRF
SERVO
IR VFD UART GPIOs
IR_IN VFD_CLK VFD_STB VFD_DATA U0_DI U0_DO Other GPIOs
TDM_DX TDM_DR TDM_FSX TDM_CLK
TDM
V_FSAD J V_COMP V_REFOUT V_REFIN V_DACO[5:0]
Video output interface
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OCT. 07, 2003 Preliminary Version: 0.2
Preliminary
SPHE8200A
4.3. Pin Description
Signal Pin State Supply Pins (51) Description
VSS_K*
VSS_O*
VSS_K6/O7 VDD_K*
VDD_O*
VSS_PLLV
VDD_PLLV VSS_PLLA
VDD_PLLA VDD_TVA* VSS_TVA* VSS_ADA
VDD_ADA
PWM_VSS
PWM_VDD DA_VSS
DA_VDD PLLVDD PLLVSS SVSS
SVDD
ADVSS
ADVDD
RST_B
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30, 47, 79, 100, 124, 142 36, 63, 90, 107, 116, 132, 152 172 S S Ground pins for chip kernel logic Ground pins for chip output S Shared ground pin 24, 42, 76, 95, 120, 137, 177 S 1.8V power supply pins for chip kernel logic and input pre-driver 3.3V power supply pins for output pins 32, 55, 85, 105, 112, 128, 147, 167, 73 72 S S Ground pin for system PLL S 1.8V power supply pin for system PLL Ground pin for audio PLL 75 S 74 S 3.3V power supply pin for audio PLL 183, 187, 191 S 3.3V power supply pin for TV DAC Ground pin for TV DAC 184. 188. 192 162 S S Ground pin for on-chip audio ADC 161 S 3.3V power supply pin for on-chip audio ADC 201 S Servo PWM ground (digital) 194 S Servo PWM 3.3V power (digital) 202 S Servo DAC ground 205 S Servo DAC 3.3V power 213 S Servo PLL 3.3V power 216 6 S Servo PLL ground S Servo analog ground 4 S Servo analog 3.3V power 18 11 S Servo ADC ground S Servo ADC 3.3V power System Control Pin 33 I System reset (active low reset) ROM / SRAM / Flash Interface (33) 34 35 37 38 39 40 41 43 44 45 O O O O O O O O I/O I/O ROM / SRAM / flash address bus bit [8] ROM / SRAM / flash address bus bit [9] ROM / SRAM / flash address bus bit [10] ROM / SRAM / flash address bus bit [11] ROM / SRAM / flash address bus bit [12] ROM / SRAM / flash address bus bit [13] ROM / SRAM / flash address bus bit [14] ROM / SRAM / flash address bus bit [15] ROM / SRAM / flash data bus [7] ROM / SRAM / flash data bus [6] 9 OCT. 07, 2003 Preliminary Version: 0.2
R_A[8] R_A[9] R_A[10] R_A[11] R_A[12] R_A[13] R_A[14] R_A[15] R_D[7] R_D[6] © Sunplus Technology Co., Ltd. Proprietary & Confidential
Preliminary
SPHE8200A
Signal R_D[5] R_D[4] R_D[3] R_D[2] R_D[1] R_D[0] R_A[0] R_A[1] R_A[2] R_A[3] R_A[4] R_A[5] R_A[6] R_A[7] Pin 46 48 49 50 51 52 State I/O I/O I/O I/O I/O I/O O O O O O O O O ROM / SRAM / flash data bus [5] ROM / SRAM / flash data bus [4] ROM / SRAM / flash data bus [3] ROM / SRAM / flash data bus [2] ROM / SRAM / flash data bus [1] ROM / SRAM / flash data bus [0] Description
R_A[16] R_A[17] R_A[18]
R_A19/GPIO
R_OE_B/GPIO
R_WE_B/GPIO
l GY tia O n L e O C id N IN f n H E o C C E IS s T D Y lu C N L p I n N HA N u N C O S U R SE S E U r M o & F
53 54 56 57 58 59 60 61 ROM / SRAM / flash address bus bit [0] ROM / SRAM / flash address bus bit [1] ROM / SRAM / flash address bus bit [2] ROM / SRAM / flash address bus bit [3] ROM / SRAM / flash address bus bit [4] ROM / SRAM / flash address bus bit [5] ROM / SRAM / flash address bus bit [6] ROM / SRAM / flash address bus bit [7] 62 64 65 O O O ROM / SRAM / flash address bus bit [16] ROM / SRAM / flash address bus bit [17] ROM / SRAM / flash address bus bit [18] 66 I/O ROM / SRAM / flash address bus bit 19 or GPIO Priority selection Function sft_cfg0[0]=1'b1 (other) R_A19 (default) UART0 TX GPIO[32] sft_cfg2[4:2]=3'b010 67 I/O ROM / SRAM / flash output enable or GPIO Priority selection Function sft_cfg1[4]=1'b1 (other) R_OE_B (default) DSP FL0 GPIO[33] sft_cfg4[2:0]=3'b100 68 I/O ROM / SRAM / flash write strobe or GPIO Priority selection sft_cfg1[5]=1'b1 sft_cfg4[5:3]=3'b100 (other) Function R_WE_B (default) DSP FL1 GPIO[34]
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Preliminary
SPHE8200A
Signal R_CS1_B/GPIO Pin 69 State I/O Description ROM / SRAM / flash chip select #1 (first device) or GPIO Priority selection Function
R_CS2_B/GPIO
R_CS3_B/GPIO
CLKIN
CLKOUT
M_DD[7] M_DD[6] M_DD[5] M_DD[4] M_DD[3] M_DD[2] M_DD[1] M_DD[0]
l GY tia O n L e O C id N IN f n H E o C C E IS s T D Y lu C N L p I n N HA N u N C O S U R SE S E U r M o & F
sft_cfg1[0]=1'b1 (other) R_CS1_B (default) GPIO[13] 70 I/O ROM / SRAM / flash chip select #2 or GPIO Priority selection Function sft_cfg1[1]=1'b1 (other) R_CS2_B (default) DSP FL2 GPIO[35] sft_cfg4[8:6]=3'b100 71 I/O ROM / SRAM / flash chip select #3 or GPIO Priority selection Function sft_cfg1[2]=1'b1 (other) R_CS3_B (default) DSP FLAGOUT GPIO[36] sft_cfg4[11:9]=3'b100 Crystal / Clock Pins (2) 78 I Clock input / crystal in (XTALI) 77 O Clock output / crystal out (XTALO) SDRAM Interface Pins (57) SDRAM data bus [7] SDRAM data bus [6] SDRAM data bus [5] SDRAM data bus [4] SDRAM data bus [3] SDRAM data bus [2] SDRAM data bus [1] SDRAM data bus [0] 80 81 82 83 84 86 87 88 I/O I/O I/O I/O I/O I/O I/O I/O O O O O O I/O I/O I/O I/O I/O 89 91 92 93 94 96 97 98 99 101 SDRAM write enable / row precharge SDRAM column address strobe SDRAM row address strobe / precharge SDRAM chip select SDRAM bank select address [0] SDRAM data bus [15] SDRAM data bus [14] SDRAM data bus [13] SDRAM data bus [12] SDRAM data bus [11] 11 OCT. 07, 2003 Preliminary Version: 0.2
M_WE_B M_CAS_B M_RAS_B M_CS_B M_BA0 M_DD[15] M_DD[14] M_DD[13] M_DD[12] M_DD[11] © Sunplus Technology Co., Ltd. Proprietary & Confidential
Preliminary
SPHE8200A
Signal M_DD[10] M_DD[9] M_DD[8] Pin 102 103 104 State I/O I/O I/O O SDRAM data bus [10] SDRAM data bus [9] SDRAM data bus [8] Description
M_CLKO M_CKE
M_A[11]/GPIO
M_A[9] M_A[8]
M_A[7] M_A[6] M_A[5] M_A[4]
M_DQM1
M_DQM0 M_BA1
M_A[10] M_A[0] M_A[1] M_A[2] M_A[3]
M_DD[31] M_DD[30] M_DD[29] M_DD[28] M_DD[27] M_DD[26] M_DD[25] M_DD[24]
l GY tia O n L e O C id N IN f n H E o C C E IS s T D Y lu C N L p I n N HA N u N C O S U R SE S E U r M o & F
106 SDRAM clock output 108 O SDRAM clock enable 109 I/O SDRAM address bus [11] or GPIO Priority selection Function sft_cfg6[4]=1'b1 (other) M_A[11] (default) GPIO[14] 110 111 O SDRAM address bus [9] SDRAM address bus [8] O 113 114 115 117 O O O O SDRAM address bus [7] SDRAM address bus [6] SDRAM address bus [5] SDRAM address bus [4] 118 O SDRAM data input/output mask for M_DD[15:8] SDRAM data input/output mask for M_DD[7:0] 119 O 121 O SDRAM bank select address [1] Priority selection Function sft_cfg6[6]=1'b1 (other) M_BA1 GPIO[15] 122 O SDRAM address bus [10] SDRAM address bus [0] SDRAM address bus [1] SDRAM address bus [2] SDRAM address bus [3] SDRAM data bus bit 31 SDRAM data bus bit 30 SDRAM data bus bit 29 SDRAM data bus bit 28 SDRAM data bus bit 27 SDRAM data bus bit 26 SDRAM data bus bit 25 SDRAM data bus bit 24 SDRAM data input/output mask for M_DD[31:24] SDRAM data input/output mask for M_DD[23:16] SDRAM data bus bit 23 SDRAM data bus bit 22 12 OCT. 07, 2003 Preliminary Version: 0.2 123 125 126 127 O O O O 129 130 131 133 134 135 136 138 139 140 141 143 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
M_DQM3/GPIO M_DQM2/GPIO M_DD[23] M_DD[22] © Sunplus Technology Co., Ltd. Proprietary & Confidential
Preliminary
SPHE8200A
Signal M_DD[21] M_DD[20] M_DD[19] M_DD[18] M_DD[17] M_DD[16] Pin 144 145 146 148 149 150 State I/O I/O I/O I/O I/O I/O SDRAM data bus bit 21 SDRAM data bus bit 20 SDRAM data bus bit 19 SDRAM data bus bit 18 SDRAM data bus bit 17 SDRAM data bus bit 16 Description
M_A[12]/GPIO
A_DATA[4] / GPIO
A_IEC_RX/GPIO
A_IEC_TX/GPIO
A_DATA[0] / GPIO
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151 I/O SDRAM address bus [12] or GPIO Priority selection Function sft_cfg6[5]=1'b1 (other) M_A[12] (default) GPIO[18] Audio Interface (10) 163 I/O Serial audio data output for channel 9/8 or GPIO Priority selection Function sft_cfg3[5]=1'b1 (other) A_DATA[4] (default) GPIO[57] 164 I/O IEC-958 receive data Priority selection Function sft_cfg3[7]=1'b1 (other) A_IEC_RX (default) GPIO[58] 165 I/O IEC-958 transmit data Priority selection Function sft_cfg3[7]=1'b1 (other) A_IEC_TX (default) GPIO[19] 166 I/O Serial audio data output for channel 1/0 or GPIO Priority selection sft_cfg3[7]=1'b1 (other) Function A_DATA[0] (default) GPIO[20] 168 I/O Serial audio data output for channel 3/2 or GPIO Priority selection sft_cfg3[7]=1'b1 (other) Function A_DATA[1] (default) GPIO[21]
A_DATA[1] / GPIO
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Signal A_DATA[2] / GPIO Pin 169 State I/O Description Serial audio data output for channel 5/4 or GPIO Priority selection Function
A_DATA[3] / GPIO
A_LRCK/GPIO
A_BCK/GPIO
A_XCK/GPIO
GPIO
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sft_cfg3[3]=1'b1 (other) A_DATA[2] (default) GPIO[59] 170 I/O Serial audio data output for channel 7/6 or GPIO Priority selection Function sft_cfg3[4]=1'b1 (other) A_DATA[3] (default) GPIO[60] 171 I/O PCM data output L/R strobe Priority selection Function sft_cfg3[6]=1'b1 (other) A_LRCK (default) GPIO[61] 173 I/O PCM bit clock Priority selection Function sft_cfg3[7]=1'b1 (other) A_BCK (default) GPIO[22] 174 I/O Audio over-sampling clock Priority selection Function sft_cfg3[7]=1'b1 (other) A_XCK (default) GPIO[23] GPIO (7) 31 I/O GPIO pin Priority selection sft_cfg2[8:5]=4'b1110 sft_cfg1[6]=1'b1 sft_cfg5[2:0]=3'b011 sft_cfg5[8:6]=3'b011 sft_cfg5[11:9]=3'b011 sft_cfg5[14:12]=3'b011 (other) Function UART1_TX ISA_CH_RDY DSP_IRQE RI_INT[12] RISC_INT[3] RISC_INTE[1] GPIO[4] (default)
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Signal IR_IN/TDM_DR Pin 153 State I/O Description GPIO (for IR) or TDM data receive Priority selection Function
VFD_CLK/TDM_D X
VFD_STB/TDM_FS X
VFD_DATA/TDM_C LK
UA0_RX/GPIO
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sft_cfg4[14:13]=2'b10 (other) TDM_DR GPIO[53] (default) 154 I/O GPIO (for VFD clock) or TDM data transmit This pin must be pull-high to 3.3v. Priority selection Function sft_cfg4[14:13]=2'b10 (other) TDM_DX GPIO[54] (default) 155 I/O GPIO (for VFD strobe) or TDM frame sync This pin must be pull-high to 3.3v. Priority selection Function sft_cfg4[14:13]=2'b10 (other) TDM_FSXR GPIO[55] (default) 156 I/O GPIO (for VFD data) or TDM clock This pin must be pull-high to 3.3v. Priority selection Function sft_cfg4[14:13]=2'b10 (other) TDM_CLK GPIO[56] (default) 175 I/O UART #0 data receive or GPIO Priority selection Function sft_cfg2[4:2]=3'b101 (other) UART0_RX (default) GPIO[62] 176 I/O UART #0 data transmit or GPIO Priority selection sft_cfg2[4:2]=3'b101 (other) Function UART0_TX (default) GPIO[63] Audio ADC pins (4) 157 A ADC input (left channel, with OP) (bonding option) Digital audio input interface bit clock
UA0_TX/GPIO
AIN/AIN_L AI_BCK
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Signal ATO AI_LRCK AIN_R VM 159 A AI_DATA Pin 158 State A Description ADC OP output. When not used, connect a 0.1uF to ground. (bonding option) Digital audio input interface L/R strobe ADC input (right channel) (bonding option) Digital audio input interface data
V_COMP V_BIAS
V_FSADJ
V_REFOUT V_DAC[0] V_DAC[1] V_DAC[2] V_DAC[3] V_DAC[4] V_DAC[5]
TRAY_OUT SC1_OUT
SPDC_OUT SC_OUT DMEA FGIN
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160 A TV DAC (10) 178 A 179 180 A adjusted by connecting a resistor (RSET) between this pin and ground. used to drive V_REFIN pin directly. 181 A 182 185 186 189 190 193 A A A A A A outputs can drive a 37.5 load directly. outputs can drive a 37.5 load directly. outputs can drive a 37.5 load directly. outputs can drive a 37.5 load directly. outputs can drive a 37.5 load directly. outputs can drive a 37.5 load directly. Servo Digital Interface (16) (Servo digital pins) 195 196 (Servo digital pins) 197 (Servo digital pins) 198 (Servo digital pins) 199 (Servo digital pins) 200 19 20 21 22 23 25 26 27 I/O I/O (Servo digital pins) (Servo digital pins) (Servo digital pins) (Servo digital pins) (Servo digital pins) (Servo digital pins) (Servo digital pins) TDM output data or GPIO TDM master clock or GPIO
ADC input voltage reference. When not used, connect a 0.1uF to ground.
Compensation pin. A 0.1pF ceramic capacitor must be used to bypass this pin to VSSA. The lead length must be kept as short as possible to avoid noise.
Full-Scale adjustment control pin. The full-scale current of D/A converters can be
Voltage reference output. It generates typical 1.2V voltage reference and may be Video DAC output #0. This is a high-impedance current source output. These Video DAC output #1. This is a high-impedance current source output. These Video DAC output #2. This is a high-impedance current source output. These Video DAC output #3. This is a high-impedance current source output. These Video DAC output #4. This is a high-impedance current source output. These Video DAC output #5. This is a high-impedance current source output. These
SRV_SCLK SRV_SDATA SRV_SDEN SRV_DFCT T_PLCK T_SLRF TDM_DX/ttin0_4/G PIO TDM_CLK/ttin1_5/ GPIO
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Signal TDM_FSXR/ttin2_6 /GPIO TDM_DR/ttin3_7/G PIO/R_CS4_B Pin 28 29 State I/O I/O Description TDM input/output frame signal or GPIO TDM input data or GPIO
TEO FEO
HGIN
LGIN2 LGIN1
LPFNIN
PDFLT1 FDFLT
VREFO
PDRSET FDRSET
DRESET CNIN SLVL RFO
RFRP
RFRPLP TEXOLP TEXO TEI FEI
CSI
SBAD VREF
VRGD
Note: Please reference SPHE8200 servo datasheet for servo related information.
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Servo Analog Interface (25) (Servo analog pins) (Servo analog pins) (Servo analog pins) 203 204 A A 206 A 207 208 A A (Servo analog pins) (Servo analog pins) 209 A (Servo analog pins) 210 211 A (Servo analog pins) A (Servo analog pins) 212 A (Servo analog pins) (Servo analog pins) 214 A 215 1 A (Servo analog pins) A (Servo analog pins) 2 A (Servo analog pins) 3 A (Servo analog pins) 5 A (Servo analog pins) (Servo analog pins) 7 A 8 A (Servo analog pins) 9 A A (Servo analog pins) (Servo analog pins) 10 12 13 A A (Servo analog pins) (Servo analog pins) (Servo analog pins) 14 A 15 A (Servo analog pins) 16 A (Servo analog pins) 17 A (Servo analog pins)
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5.FUNCTIONAL DESCRIPTIONS
SPHE8200 is a highly integrated system-on-chip design. It includes DVD/CD servo controller, RISC processor, MPEG1/2 video decoder, programmable audio decoder, programmable single chip. peripheral controller, audio ADC and multi-format TV-encoder on a
CLKI 27MHz PLLa
147.456MHz 135.4752MHz
CLK_PLLA
AUDCLK_GEN
5.1. PLL and ClockGen
SPHE8200 contains two PLLs to generate system clock (PLLv) and audio reference clocks (PLLa). clocks. single external 27MHz clock or crystal to generate all the required System clock is then derived from division of the PLLv output.
Some pre-defined PLLv/SYSCLK frequencies are listed below: SYSCLK Frequency 101.25MHz 108MHz PLLV Frequency 405MHz 216MHz
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5.2. Power Control
order to achieve minimum power consumption. Automatic power-save: not operating.
XCK ADCLK IECCLK
SPHE8200 provides various levels of power-control mechanism in
Both the PLLs reference a
Most hardware modules are automatically power-saved when
Module-level stop-operation:
SPHE8200 provides a function to turn off specific module from operating. Without explicit wake-up, the hardware module will remain static and consume very little power.
CLKI 27MHz
PLLv
Fractional multiples of CLKI
CLK_PLL
SYSCLK_GEN
/2, /4 ~ /65536
SYSCLK
System-level doze:
For maximum power-saving, firmware could fine-tune system performance according to system task.
Option Video Clock In
VIDCLK_GEN
VIDCLK
5.3. Embedded 32-bit RISC Controller
SPHE8200 includes a powerful 32-bit RISC processor. This RISC processor is utilized to manage decoding tasks as well as UI tasks. It can access to all the memory and devices, cooperate between processor systems. Audio decoder and I/O processor handshake with RISC processor through the mailbox registers.
114.75MHz 121.5MHz
459MHz
486MHz
128.25MHz 135MHz
256.5MHz
270MHz
mailbo (16x16
Audio decoder
141.75MHz 148.5MHz
283.5MHz
297MHz
RISC subsyste
155.25MHz 162MHz 168.75MHz 175.5MHz 182.25MHz 189MHz
310.5MHz
324MHz 337.5MHz 351MHz 364.5MHz 378MHz
mailbo (16x8)
I/O processo
Figure 5-1: Communication between processors
The RISC processor is equipped with instruction and data caches. These caches can accelerate accesses to the SDRAM or ROM cacheable regions.
PLLa supports two center frequencies (for 48kHz family or 44.1kHz family) and generates required audio clocks from the audio system clock.
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edge-trigger and level-sensitive mode.
I-CACHE Peripheral Control bus BIU
Processor Local Bus
Other modules
Watchdog: Watchdog keeps monitoring RISC behavior and whenever firmware is in a deadlock, it can try to reset the system and keep the application functioning continuously.
RISC32 core
SMMU
Table: RISC processor configuration
D-Cache
4kbyte (direct-mapped) 1kbyte scratch buffer
to RISC interrupt
peripheral control bus
I-Cache
D-RAM/DMA
The RISC sub-system is able to bootstrap from multiple sources.
In typical application the RISC processor boots from external ROM without pre-loaded firmware.
device #1. Besides that, it also supports standalone booting
5.4. RISC interface
RISC controllers interface to system via various interface control
modules. These interface modules are mapped to the processor memory map and firmware could operate on them via typical memory accesses. These controllers include: ROM/FLASH/SRAM (RFS) controller Peripheral control interface
RISC Memory Interface controller (SDRAM)
The RISC memory mapping of these controllers is shown in following table: Table: RISC memory mapping Memory range
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D-CACHE
System Bus
ROM/Flash interface
ROM FLASH SRAM
D-RAM DMA
System Bus Interface
Timers
DRAM
There are 4-channel timers and 2 cascade counters for timed tasks. During A/V decoding, counters are utilized to synchronize audio and video.
Figure 5-2: RISC subsystem
Specification
RISC subsystem
8kbyte (2-way set associated)
RISC monitor
monitor interrupt
Watchdog
Device interrupt controller
watchdog reset
Timers
timer interrupt
Figure 5-3: RISC dedicated hardware
Table: Device interrupt controller sources Symbol
Description
INT_WDOG
Watchdog interrupt (if reset disabled) Interrupt when horizontal resync
INT_HSYNC INT_VSYNC
Interrupt when enter vertical resync
INT_FLD_ACT
Interrupt when enter active region
INT_FLD_SYNC INT_HOST
Interrupt when leave active region Host device interrupt Timer 0 interrupt Timer 1 interrupt
INT_TIMER0 INT_TIMER1
INT_TIMER2A INT_TIMER2B
Timer 2 scale interrupt
Timer 2 count interrupt Timer 3 scale interrupt
Description
INT_TIMER3A INT_TIMER3B INT_TIMERW INT_UART0 INT_UART1 INT_VDP0 INT_DSP INT_EXT0
8000_0000-87ff_ffff a000_0000-a7ff_ffff 8800_0000-8fbf_ffff a800_0000-afbf_ffff affe_8000-affe_ffff afff_0000-afff_03ff
SDRAM (cached) SDRAM (uncached) ROM/FLASH/SRAM (cached) ROM/FLASH/SRAM (uncached) Peripheral control registers DMA buffer
Timer 3 count interrupt Watchdog timer interrupt UART0 interrupt UART1 interrupt Video decoder interrupt DSP interrupt External interrupt #0 External interrupt #1 External interrupt #2 External interrupt #3 IOP interrupt Audio hardware interrupt
In additional to that, SPHE8200 includes dedicated RISC peripherals to assist the system tasks: Device interrupt controller: Device interrupt controller takes care of interrupt sources from on-chip devices and off chip sources. For each interrupt source the firmware is able to configure the interrupt behavior between
INT_EXT1 INT_EXT2 INT_EXT3 INT_IOP INT_AUD
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5.5. ROM/Flash/SRAM controller
The SPHE8200 provides flexible connections to external ROM, Flash or SRAM (RFS). It can support up to 4 external RFS devices by using different chip-selects (R_CS_B[3:0]). The firmware can configure RFS memory anchor registers and map these devices into locations of memory space. For each memory space it can be in flash mode or in ISA mode. In FLASH mode the access timing is decided by wait-state setting, while in ISA mode the controller will reference external IO_CHRDY input.
5.7. Peripheral Control Interface
RISC firmware controls on-chip devices (such as video decoder, audio decoder..) by a dedicated peripheral control interface. Firmware controls the hardware behavior by writing to specific hardware registers with this interface.
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5.8. CSS/CPPM support
system supports C2_D/C2_E and C2_DCBC functions.
Prefetch buffer
SPHE8200 have built-in CSS and CPPM hardware support. For CSS the system supports accelerated DMA. For CPPM the
5.9. MPEG Video Decoder
The system incorporates a powerful MPEG video decoding datapath and provides real-time video decoding of MPEGI/II bitstream. The bitstream can come from Servo hardware, ATAPI, TDM or UART. This enables various applications to be built over SPHE8200 such as real-time broadcasting over Ethernet. The video decoder is a hardwired MPEG1/2 datapath. The system architecture is as in the figure. RISC subsystem is in charge of de-multiplexing the data and buffering formatted video data into video bitstream buffer resided in external SDRAM. Upon correct timing video decoder will decode the bitstream and write back reconstructed video frame for playback.
Processor local bus
Address translator
Address sequencer
External ROM interface
Wait state generation
Figure 5-4: ROM/FLASH/SRAM controller
ROM/Flash mode
CSB
wait
wait
ADDR[] OEB
Address (read)
Address (write)
oe_setup
oe_hold
WEB
we_setup
we_hold
DATA[]
Data (read)
DATA (for write)
data is sampled at this point
RISC subsystem
bitstream
control bus
Video decoder
reference
ISA MODE
CSB
memory bus all data
wait
iochrdy_hold
wait
iochrdy_hold
ADDR[] OEB WEB
Address (read)
Address (write)
oe_setup
oe_hold we_setup we_hold
External SDRAM
IO_RDY DATA[] Data (read)
data is sampled at this point
DATA (for write)
Figure 5-7: Interface between RISC and Video decoder
Figure 5-6: ISA mode timing
Advanced video decoding and display control mechanism is included to prevent tearing effect.
5.6. RISC Memory Interface
RISC memory interface provides a fast-path between processor local bus and system memory bus. Local bus transactions are mapped to system memory bus tasks.
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bitstream
Figure 5-5: ROM/FLASH/SRAM mode timing
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Video contrast/bright/color enhancement
Picture control Variable length decoder Q matrix
During runtime video post-processing hardware will fetch video sources from framebuffer and process the data as in the following figure.
5.10. Graphics Engine BondyPro®
For thin-client or set-top box applications, 2D graphics capabilities
are key to system performance. This graphics engine is able to
perform fast BitBlt and 2D drawing functions. The graphics engine is combined with 2 parts: graphics command interpreter and graphics datapath. Upon receiving command from RISC, interpreter will send micro-commands to graphics datapath, where raster operations are executed.
5.11. Video Post Processing
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input FIFO Inverse quantization
Memory Interface
input buffer
line buffer
Inverse DCT
output buffer
Motion compensation
de-interlac
from memory interface
input buffer
Vertical filtering d chroma resampl
CIF and horizonta expansio
to display interface
DCT buffer
display information
Decoding control
de-interlac buffer
Figure 5-8: architecture of video decoding pipeline
5.12. Audio DSP
The SPHE8200 contains a high-performance 24-bit audio DSP optimized for embedded systems. The DSP processor can fetch operands from memories and perform During multiplication-and-accumulation (MAC) in one cycle.
execution the DSP fetches instruction from main-memory or IROM, at the same time the ICACHE will store the LRU instructions. Data are loaded from and to main-memory by using the cycle-stealing DMA channels. There are 3 independent cycle-stealing DMA channels that allow DSP run without stalled by memory access.
The DSP works closely with RISC processors by using mailbox registers or shared-memory protocol. When downloaded with different codec firmware the DSP could support multi-standard audio and act as an accelerator for RISC in some case.
Grap comma interpret
Grap data
RISC subsyste
Graph work
Memo Interfa
IROM
Figure 5-9: BondyPro® architecture
ICACHE
SPHE8200 includes powerful video-post-processing facilities to provide high video quality. It perform following functions: YUV411, YUV420, YUV422 and 8-bit indexed color SIF to CCIR601 interpolation MPEG1 CIF filter MPEG1/2 chroma vertical interpolation Up to 1/2x horizontal decimation Up to 1/512x vertical decimation Up to 1024x horizontal expansion Up to 1024x vertical expansion Powerful de-interlacing hardware Pan and scan function De-flicker during interlaced display
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DSP
data ROM
data RAM
BIU
Memory interface
data RAM
data ROM
audio interface controller
Figure 5-10: Audio DSP architecture
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5.13. Audio Interface
The audio interface is in charge of servicing DSP and maintaining all audio-related tasks. It will buffer the DSP processed audio playback data and format them to audio DAC required format.
For power-constrained applications SPHE8200 also implements SDRAM power-down modes to save dynamic operating power.
SPHE8200 support following audio DAC format combinations: 32k ok ok 44.1k ok ok 48k ok ok 64k ok ok 88.2k ok ok 96k ok ok
256fs 384fs
LRCK frame width Data bits
Data sign extension
5.14. Integrated Audio Quality ADC
The embedded ADC is a 2-channel 64fs over-sampling ADC of12-bit quality. If required it could operate under 128fs over-sampling.
5.15. I/O Processor
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Buffer control
5.17. Sub-picture Decoder
For DVD and SVCD sub-picture content SPHE8200 includes an advanced multi-format sub-picture decoder. It could support real-time decode and display from raw sub-picture bitstream. Vertical interpolation is supported for PAL/NTSC translation or special effect.
IEC958
IEC-958 input
Memory Interface
digital input interface
ADC ctrl
digital audio input
Audio work buffer
ADC
analog in
5.18. On Screen Display
PCM playback
IEC958
The on screen display (OSD) function of the SPHE8200 provides an overlay bitmap graphics on the final TV display. Applications can use this function to display specific information over the video display plane without operating on the video source. The SPHE8200 can display multiple OSD regions on a single display frame, where every OSD regions can be in different size, location and color format. The OSD hardware supports 4, 16, 256 indexed color or 16-bit direct color. OSD regions are stored in main memory before display. During display, OSD decoder would read these header and data and interpret to be a graphic data that overlay with video to be output to the display interface.
digital audio output
IEC-958 output
Figure 5-11: Audio Interface architecture
192k ok ok
Data alignment
Left adjust, I2S, normal format 16b, 24b, 32b, 64b
5.19. Display Interface
The display interface of SPHE8200 integrates the video content generated from video-post-processing, sub-picture-decoder and on-screen-display modules. It also performs content cropping, underflow and overflow detection, and overall bright/contrast adjustment.
16b, 18b, 20b, 24b
zero-extended, sign-extended
Video active
Sub-picture active
OSD active
(1.0 - sup_blend_factor)
blank (black)
Video processed source data
TV data output sub-picture source data
(sup_blend_factor) (1.0 - osd_blend_factor)
The SPHE8200 includes an 8-bit micro-controller to handle most I/O jobs. IR, VFD and other slow devices can be interfaced using this I/O processor.
OSD source
(osd_blend_factor)
5.16. SDRAM Controller
SDRAM controller in SPHE8200 is very flexible and powerful. It was designed to meet different SDRAM timing requirement while achieving maximum performance. SDRAM tasks are optimized for maximum system performance. DRAM refreshing is issued automatically whenever required or SDRAM interface is idle for a given time.
Figure 5-12: Display pipeline
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The video enhancement process is show in following figure: ATA/ATAPI compliant devices directly. The ATAPI/IDE interface is a standard ATA-5 host interface capable of PIO mode 2 to PIO
OSD sub-picture
mode 4 to external devices. By implementing this interface system could support IDE hard-disk drives, compact flash cards, ATAPI based DVDROM loaders or other ATA compliant devices.
5.20. Video DAC
SPHE8200 contains 6-channel 10-bit high-speed current-source display). The DAC outputs can drive a 37.5Ohm load directly.
DACs operating from 27MHz to 60MHz (for 480p/576p or SVGA
5.21. ATAPI interface
SPHE8200 also supports ATAPI interface directly without glue logic. Although the SPHE8200 has integrated DVD/CD servo logics, with this interface the application could support other
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Video post processing Display interface vid[] TV-encoder dac[] DAC analog video video source enhancement and bright/ contrast/color control DAC gain, linearity adjustment
5.22. GPIO
In SPHE8200 almost every pin that related to selectable features can serve as general-purpose input-output control function. When a pin is programmed to this mode, the RISC can take full control over the direction and output level.
Figure 5-13: Display pipeline
5.23. UART
Two UART
channels
are
provided
for
debugging
or
communication purpose. The UART can support standard serial port baud-rate and formats. It also supports auto baud-rate detection and hardware flow-control (CTS/RTS pair).
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6.ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Parameter Voltage on any pin relative to Vss Symbol VIN Value -0.3 to 5.5 -0.3 to 3.6 Unit V V
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied and exposure to absolute maximum rating conditions for extended periods may affect device reliability.
6.2. DC Operating Conditions
Recommended Operating Conditions (Voltage referenced to VSS=0V, TA=-0 to 70°C) Parameter Symbol VDDK Min. 1.62 3.0 2.0
6.3. Capacitance
(VDDIO=3.3V, TA=24°C, f=108MHz, VREF=1.4V+-200mV) Parameter
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Voltage on VDDIO supply relative to VSS Voltage on VDDK supply relative to VSS Storage Temperature VDDIO VDDK TSTG -0.3 to 1.98 -55 to 150 V °C Soldering Temp. (Max. Time) TSOLDER IOS 240 (for 5 Sec. Max.) 50 °C Short circuit current mA Typ. 1.8 Max. 1.98 3.6 Voltage on VDDK supply relative to VSS Voltage on VDDIO supply relative to VSS VDDIO VIH VIL 3.30 Input logic high voltage Input logic low voltage 5.5 0.8 -0.3 2.4 Output logic high voltage VOH VOL IL Output logic low voltage Input leakage current 0.4 10 -10 Symbol CIN Min. Typ. 3.5 Max. Input pin capacitance Input pin capacitance COUT 3.5 Bidirectional pin capacitance CBIDIR 3.5 -
Units V V V V V V uA
Units pF pF pF
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6.4. AC Characteristics 6.4.1. SDRAM interface timing diagrams
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tCH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
tCL
CKE
tCC
tRAS
CS
tRC
tSH
tRP
RAS
tSS
tRCD
tCCD
CAS
ADDR
RAa
CAa
RBb
CBb
RAc
CAc
BA
A10/AP
RAa
RBb
RAc
tRRD
*Note 1
tCDL
DQ CL=2
CAa0
CAa1
CAa2
CAa3
DBb0
DBb1
DBb2
DBb3
CAc0
CAc1
CAc2
tSAC
CL=3
CAa0
CAa1
CAa2
CAa3
DBb0
DBb1
DBb2
DBb3
CAc0
CAc1
tSLZ
DH
WE
DQM
Row Active (A-Bank)
Read (A-Bank)
Row Active (B-Bank)
Precharge (A-Bank)
Write (B-Bank)
Row Active (A-Bank)
Read (A-Bank)
: Don't care
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE CS
HIGH
RAS
CAS
ADDR
RAa
CAa
CAb
BA
A10/AP
RAa tBDL tRDL DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
DQ
DAa0
DAa1
DAa2
DAa3
DAa4
WE
DQM
Row Active (A-Bank)
Write (A-Bank)
Burat Stop
Write (A-Bank)
Precharge (A-Bank)
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OCT. 07, 2003 Preliminary Version: 0.2
Preliminary
SPHE8200A
(Recommended condition for DVD playback is listed in typical condition with f=121.5MHz) Parameter Row active to row active delay RAS to CAS delay Symbol tRRD tRCD tRP Min 1 1 Typ 2 2 2 Max 4 *1 4 *1 Units System clock cycle System clock cycle System clock cycle System clock cycle
*1 Using maximum values may limit system performance. *3 Width of clock pulse depends on system clock cycle.
*2 Width of data window can be estimated from (tCC-tSAC+tOH).
6.4.2. ROM / flash interface timing diagrams
ROM Compatible Mode
l GY tia O n L e O C id N IN f n H E o C C E IS s T D Y lu C N L p I n N HA N u N C O S U R SE S E U r M o & F
Row precharge time Row active time Row cycle time 1 4 *1 8 *1 tRAS tRC 1 5 1 1 8 32 *1 4 *1 1 Last data in to new column address delay tCDL 1 Column address to column address delay CLK cycle time *2 tCCD tCC 1 1 6 8.2 1000 6.5 ns CLK to valid SDRAM output delay *2 SDRAM output data hold time *2 CLK high pulse width *3 CLK low pulse width *3 tSAC tOH tCH tCL 6.0 2 ns 1 ns 3 ns 3 ns CLK to SDRAM output Low-Z tSLZ 1.0 (tCC) ns CLK to SDRAM output High-Z tSHZ 6.0 (tSAC) ns
System clock cycle System clock cycle System clock cycle
CSB
tACCESS
tACCESS
ADDR[]
Address (read)
Address (write)
OEB
tWES
tWEH
WEB
tDS
tDH
DATA[]
Data (read)
DATA (for write)
Figure 6-1: ROM / flash interface ROM mode access timing
Parameter ROM / SRAM / flash access time Data setup time for read Data hold time for read Address/data setup time before write strobe Address/data setup time after write strobe *1 Recommended value when f=121.5MHz
Symbol tACCESS tDS tDH tWS tWH
Min 2 5 0 0 0
Typ 8 *1 1 1
Max 31 31 31
Units System clock cycle ns ns System clock cycle System clock cycle
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OCT. 07, 2003 Preliminary Version: 0.2
Preliminary
SPHE8200A
ISA Compatible Mode
ISA access time *1 IO_RDY wait time Output hold time Input hold time
Address/data setup time before write strobe Address/data setup time after write strobe
*1 After this period of time IO_RDY_B must be stable and indicates correct status of target device.
6.4.3. Audio interface timing diagrams
Some audio interface configuration timing diagrams are shown below.
l GY tia O n L e O C id N IN f n H E o C C E IS s T D Y lu C N L p I n N HA N u N C O S U R SE S E U r M o & F
ADDR[] OEB
CSB
tACCESS
tACCESS
Address (read)
Address (write)
tWES
tWEH
WEB
tWAIT
tOH
tIH
tWAIT
tOH
tIH
IO_RDY DATA[]
Data (read)
Data (write)
Figure 6-2: ROM / flash interface ISA mode access timing
Parameter
Symbol tACCESS tWAIT tOH tIH
Min 2
Typ -
Max 31
Units
System clock cycle
0 1 0
-
1000 -
ns
-
System clock cycle ns
-
-
tWS
0
1
31
System clock cycle System clock cycle
tWH
0
1
31
0
1
22
23
0
1
2
22
23
BCK
LRCK
left channel 21 2
right channel 21 2
AUDATA[]
23
22
1
0
23
22
1
0
MSB
LSB MSB
LSB
Figure 6-3: Normal mode / 24bit data / 24bit frame / MSB first
0
1
8
9
30
31
0
1
30
31
0
BCK LRCK AUDATA[]
left channel 23 MSB 22 21 2 1 0 LSB right channel 2 1 0
Figure 6-4: Right justified (normal) mode / 24bit data / 32bit frame / MSB first
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OCT. 07, 2003 Preliminary Version: 0.2
Preliminary
SPHE8200A
0 1 2 22 23 24 31 0 1 2 31 0
BCK
6.4.4. Video timing diagrams
Interlaced Modes
SP active period
active line period
l GY tia O n L e O C id N IN f n H E o C C E IS s T D Y lu C N L p I n N HA N u N C O S U R SE S E U r M o & F
LRCK
left channel 1 right channel 21
AUDATA[]
23
22
21
0
23
22
MSB
LSB
Figure 6-5: Left justified mode / 24bit data / 32bit frame / MSB first
0
1
2
3
23
24
25
31
0
1
2
3
31
0
BCK
LRCK
D
left channel 21 2
D
right channel 22
AUDATA[]
23
22
1
0
23
MSB
LSB
Figure 6-6: I2S mode / 24bit data / 32bit frame
0
1
2
22
23
0
1
2
22
23
0
1
BCK
LRCK
D
left channel 22 21
D 0
right channel 22 21
AUDATA[]
23
2
1
23
2
1
0
MSB
LSB MSB
LSB
Figure 6-7: I S mode / 24bit data / 24bit frame
2
Parameter
Symbol tS
Min -
Typ 0.5
Max -
Units
BCK rising to LRCK / AUDATA transition
System clock cycle
SP active period
V blanking period (21)
active line period
Video line number
522 523 524 525
SP line number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23 0
24 2
25 4
26 6
27 8
28 10
29 12
473 475 477 479
Video line number
260
261 262 263 264 265 266 267 268 269
270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287
1 3
288
5
289 290 291 7 9 11
SP line number
474
476 478
V blanking period (21)
active line period
active line period
SP active period
SP active period
Figure 6-8: NTSC (480i) timing diagram
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OCT. 07, 2003 Preliminary Version: 0.2
Preliminary
SPHE8200A
SP active period active line period V blanking period (23.5) SP active period active line period
Progressive Modes
l GY tia O n L e O C id N IN f n H E o C C E IS s T D Y lu C N L p I n N HA N u N C O S U R SE S E U r M o & F
Video line number SP line number
619 620 567 569
621 622 623 624 625 571 573
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23 0
24 2
25 4
26 6
27 8
Video line number SP line number
307 474
308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 476 478
326 327 328 329 330 331 332 333 334
335 336 337 338 339 340 1 3 5 7 9
active line period SP active period
V blanking period (24)
active line period
SP active period
Figure 6-9: PAL (576i) timing diagram
SP active period
SP active period
active line period
active line period
521 522
523 524 525
1
2
3
4
5
6
7
8
9
10
11
12
13
14
44
45
0
46
1
47
2
48
3
49
4
50
5
51
6
476 477
478 479
Figure 6-10: NTSC (480p) timing diagram
SP active period
SP active period
active line period
active line period
617 618 619 620 621 622 623 624 625 572 573 574 575
1
2
3
4
5
6
7
8
9
43
44
45 0
46 1
47 2
48 3
49 4
50 5
51 6
Figure 6-11: PAL (576p) timing diagram
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OCT. 07, 2003 Preliminary Version: 0.2
Preliminary
SPHE8200A
7.REGISTER LIST
Name GROUP 0 sft_cfg0 sft_cfg1 sft_cfg2 sft_cfg3 sft_cfg5 sft_cfg6 0xbffe8044 0xbffe8048 0xbffe804c Address System Control Registers Configure pin-mux 0 Configure pin-mux 1 Description
0xbffe8044 Description
Pin MUX control register #0 (General) Attribute: RW
Reset_2 Reset_3 Reset_*
Reset_2: reset default when hardware-configuration is set to 2 Reset_3: reset default when hardware-configuration is set to 3 Reset_*: reset default for other hardware-configuration
RA19
RA20
l GY tia O n L e O C id N IN f n H E o C C E IS s T D Y lu C N L p I n N HA N u N C O S U R SE S E U r M o & F
Configure pin-mux 2 0xbffe8050 0xbffe8058 0xbffe805c Configure pin-mux 3 Configure pin-mux 5 Configure pin-mux 6 sft_cfg0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit-field RA26 RA25 RA24 RA23 RA22 RA21 RA20 1 0 1 0 1 1 1 0 1 0 1 1 1 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0
0 RA19 1 1 1
ROM address bus bit 19 (R_A19) select 0: R_A19 is not available and ignored 1: Enable (default)
ROM address bus bit 20 (R_A20) select 00: R_A20 is not available and ignored 01: R_A20 is available at pin 19
10: R_A20 is available at pin 129 11: Reserved
RA21
ROM address bus bit 21 (R_A21) select 00: R_A21 is not available and ignored 01: R_A21 is available at pin 20 10: R_A21 is available at pin 130 11: Reserved
RA22
ROM address bus bit 22 (R_A22) select 00: R_A22 is not available and ignored 01: R_A22 is available at pin 21 10: R_A22 is available at pin 131 11: reserved
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OCT. 07, 2003 Preliminary Version: 0.2
Preliminary
SPHE8200A
RA23 ROM address bus bit 23 (R_A23) select 00: R_A23 is not available and ignored 01: R_A23 is available only at 256 pin package
RA24
RA25
RA26
0xbffe8048 Description
Pin MUX control register #1 (General) Attribute: RW
l GY tia O n L e O C id N IN f n H E o C C E IS s T D Y lu C N L p I n N HA N u N C O S U R SE S E U r M o & F
10: R_A23 is available at pin 133 11: reserved ROM address bus bit 24 (R_A24) select 00: R_A24 is not available and ignored 01: R_A24 is available only at 256 pin package 10: R_A24 is available at pin 134 11: reserved ROM address bus bit 25 (R_A25) select 00: R_A25 is not available and ignored 01: R_A25 is available only at 256 pin package 10: R_A25 is available at pin 135 11: reserved ROM address bus bit 26 (R_A26) select 00: R_A26 is not available and ignored 01: R_A26 is available only at 256 pin package 10: R_A26 is available at pin 136 11: reserved
sft_cfg1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit-field Reset LPT BOOT 0 pcmcia_WAIT 0 pcmcia_IORW 0 CHRDY 0 WE 1 OE 1 CS4 1 CS3 1 0 0 0 0 0 0
0 CS1 1
CS2 1
CS1
CS1 (ROM/FLASH chip select 1) function control 1: Enable Chip Select 1 (default) 0: Disable (CS1 becomes GPIO)
CS2
CS2 (ROM/FLASH chip select 2) function control 1: Enable Chip Select 2 (default) 0: Disabled (CS2 becomes GPIO)
CS3
CS3 (ROM/FLASH chip select 3) function control 1: Enable Chip Select 3 (default) 0: Disabled (CS3 becomes GPIO)
CS4
CS4 (ROM/FLASH chip select 4) function control
31 OCT. 07, 2003 Preliminary Version: 0.2
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SPHE8200A
1: Enable Chip Select 4 (default) 0: Disabled (CS4 becomes GPIO) OE OEB (ROM/FLASH output enable) function control 1: Enable OE function (default)
WE
CHRDY
pcmcia_IORW PCMCIA IOR/IOW select 000: Disabled (default)
pcmcia_WAIT
BOOT
l GY tia O n L e O C id N IN f n H E o C C E IS s T D Y lu C N L p I n N HA N u N C O S U R SE S E U r M o & F
0: Disabled (OEB becomes GPIO) WEB (FLASH/SRAM write enable) function control 1: Enable WEB function (default) 0: Disabled (WEB becomes GPIO) IOCHRDY (ISA_IOCHRDY) function control 1: Enable IOCHRDY input (i.e. output always tri-stated) 0: Disabled (default) 001: IOR from pin 19, IOW from pin 20 010: IOR from pin 135, IOW from pin 136 011: IOR from pin 58, IOW from pin 59 100: Available only at 256 pin package 101 to 111: Reserved bit 12-10 : PCMCIA_WAIT_B select 000: Disabled (default) 001: PCMCIA_WAIT_B is from pin 21 010: PCMCIA_WAIT_B is from pin 61 011: PCMCIA_WAIT_B is from pin 129 100: PCMCIA_WAIT_B is from pin 138 101: Available only at 256 pin package 011 to 111: reserved RISC32 reset boot address 0: RISC32 boots from bfc0_0000 (internal ROM) (default) 1: RISC32 boots from 8000_0000 (SDRAM region) LPT handshake signals (STROBE, ACK) select 00: Disabled (default) 01: LPT STROBE is from pin 62, LPT ACK is from pin 64 10: LPT STROBE is from pin 135, LPT ACK is from pin 136 11: Available only at 256 pin package
LPT
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Preliminary
SPHE8200A
0xbffe804c Description Pin MUX control register #2 (General) Attribute: RW sft_cfg2
ATAPI
IOP
UART0
UART1
TV_LCD
l GY tia O n L e O C id N IN f n H E o C C E IS s T D Y lu C N L p I n N HA N u N C O S U R SE S E U r M o & F
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit-field Reset SWAP 0 BRS 0 BRP 0 BRE 0 TV_LCD 0 UART1 UART0 0 0 0 0 0 0 0 1 1 0
0 ATA