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Advance Information Chroma 4 Multistandard Video Processor
The MC44002/7 is a highly advanced circuit which performs most of the basic functions required for a color TV. All of its advanced features are under processor control via an I2C bus, enabling potentiometer controls to be removed completely. In this way the component count may be reduced dramatically, allowing significant cost savings together with the possibility of implementing sophisticated automatic test routines. Using the MC44002/7, TV manufacturers will be able to build a standard chassis for anywhere in the world. Additional features include 4 selectable matrix modes (primarily for NTSC), fast beam current limiting and 16:9 display. · Operation from a Single 5.0 V Supply; Typical Current Consumption Only 120 mA · Full PAL/SECAM/NTSC Capability (4 Matrix Modes)
MC44002 MC44007
CHROMA 4 VIDEO PROCESSOR
SEMICONDUCTOR TECHNICAL DATA
40 1
· · · · · · · · · · · · · ·
Dual Composite Video or S-VHS Inputs All Chroma/Luma Channel Filtering, and Luma Delay Line Are Integrated Using Sampled Data Filters Requiring No External Components Filters Automatically Commutate with Change of Standard Chroma Delay Line is Realized with a 16 Pin Companion Device, the MC44140 RGB Drives Incorporate Contrast and Brightness Controls and Auto Gray Scale Switched RGB Inputs with Separate Saturation Control Auxiliary Y, R-Y, B-Y Inputs Line Timebase Featuring H-Phase Control, Time Constant and Switchable Phase Detector Gain Vertical Timebase Incorporating Vertical Geometry Corrections 16:9 Display Mode Capability E-W Parabola Drive Incorporating Horizontal Geometry Corrections Beam Current Monitor with Breathing Compensation Analog Contrast Control, Allowing Fast Beam Current Limitation MC44007 Decoders PAL/NTSC Only
I2C
P SUFFIX PLASTIC PACKAGE CASE 711
PIN CONNECTIONS
ACC Video 2 Iref Clock Data V-Ramp V-Drive E-W Drive 1 2 3 4 5 6 7 8 40 Video 1 In 39 Osc Loop Filter 38 Ident 37 36 R-Y B-Y Outputs
35 VCC 34 Gnd 33 (17.7 MHz) 32 (14.3 MHz) 31 Sandcastle 30 System Select 29 Y1 Output 28 Y1 Clamp 27 26 25 24 23 22 R-Y B-Y Inputs Y2 R G B Inputs Crystals
IAnode 9 Analog Contrast 10 SECAM Cal Loop 11 H-Drive 12 H-Flyback Input 13 H-Loop Filter 2 1 R Outputs G B 14 15 17 18 19
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Rating Supply Voltage Operating Ambient Temperature Storage Temperature Junction Temperature Drive Output Sink Current Applied Voltage Range: Feedback Anode Current All Other Pins ESD
NOTE: ESD data available upon request.
Pin 35 12 20 9
Symbol VCC TA Tstg TJ I12 V20 V9 Vi
Value 6.0 0 to + 70 65 to +150 +150 2.0 0 to +8.0 2.0 to VCC 0 to VCC
Unit Vdc °C °C °C mA Vdc
Signal Gnd 16
Feedback 20 (Top View)
21 Fast Commutate
ORDERING INFORMATION
Device Operating Temperature Range TA = 0° to +70°C Package Plastic DIP Plastic DIP
Rev 1
V
MC44002P MC44007P
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© Motorola, Inc. 1996
MOTOROLA ANALOG IC DEVICE DATA
1
MC44002 MC44007
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Rating Human Body Model Machine Model
NOTE: ESD data available upon request.
Pin
Symbol
Value ±2000 ±200
Unit
Simplified Block Diagram
R-Y Video 1 (S-VHS) Video 2 2 40 31 1 11 38 System 30 37 36 29 B-Y Y1
Input Select
Chroma TakeOff Filter SandCastle Luma Delay Peaking & Trap
ACC
Sync Sep
PAL/ NTSC/ SECAM Decoder
System Select Ident Sat & Hue
Filter Filter
Luma Select
25 27 26
Y2 R-Y B-Y
17.7 MHz 33 32 14.3 MHz 39 Osc
Vert Sync Sep
Y1 Clamp Matrix Switching & RGB Sat Control
28 21 24 23 22 10 Fast Comm. Red Green Blue Analog Contrast Red Green Blue
Clk Memory/Control Registers VSync Freq Divider Ramp Gen Iref Beam Current Monitor Parab Gen Rx/Tx
15
PLL 1
17 Control Loops RGB Outputs 18 19 16
14
Loop 2 Flyback Sense 35 12 13 7 V Drive 3 6
34
8
9
4
5
20
H Drive H Flyback 5.0 V Pulse
E-W Drive 5.0 V
Clk Data
Fdbck
Anode I2C Bus Current
This device contains 6,245 active transistors.
ELECTRICAL CHARACTERISTICS (VCC = 5.0 Vdc, I3 = 70 µA, TA = 25°C, unless otherwise noted.)
Characteristic Supply Voltage Operating Current Reference Current, Input Voltage Thermal Resistance, JunctiontoAmbient
NOTES: Composite Video Input Signal Level = 1.0 Vpp Black-to-White = 0.Vpp7 , Syn-to-Black = 0.3 Vpp PAL/NTSC = 75% color bars; Burst = 300 mVpp SECAM = 75% color bars
Pin 35 35 3
Min 4.75 90 1.0
Typ 5.0 120 1.3 56
Max 5.25 180 1.6
Unit V mA V °C/W
Horizontal Timebase started (subaddress 00) Vertical Breathing control set to 00; V9 = 0 V All other analog controls set to midrange 32 Video Peaking "P1, P2, P3" bits high
2
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
TEST CONDITIONS (unless otherwise noted.)
VCC = 5.0 V Iref = 70 µA TA = 25°C Video Composite Input = 1.0 Vpp BlacktoWhite = 0.7 Vpp BlacktoSync = 0.3 Vpp Horizontal Timebase Started (Reg. 00) Vertical Breathing Control Set to 00 Pin 9 = 0 V Pin 10 = 5.0 V PAL/NTSC = 75% Color Bars Burst = 300 mVpp SECAM = 75% Color Bars (MC44002 only) All Analog Controls Set to Midpoint (32) Luma Peaking at Min. (P1 P3 = 111)
Control Bits Setup
Name V1/V2 H EN BRI EN HGAIN1 YX EN Y1 EN D EN XS TEST FSI T3 VD1 2xFh NORM HGAIN2 INTSEL Y2 EN SSD CALKIL BAI SVHS Value 1 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 0 1 1 1 Video Input 1 Selected Horizontal Drive Enabled "Bright" Sample "On" Horizontal Phase Detector Gain Reduced by 3 Enabled Luma Matrix Disabled Luma from Filters "On" RGB Inputs Enabled Pin 33 Crystal Enabled Outputs Sampled Once/Field 50 Hz Field Rate Low Pass Filter Enabled 4:3 Display Mode Horizontal Drive at 1xFh Horizontal Reference Divider for 17.7 MHz Horizontal Phase Detector Gain Reduced by 2 Enabled Long Vertical Time Constant External Luma Input "Off" SECAM Mode Select Enabled Horizontal Calibration Loop Enabled Vertical Blanking for 625 Lines Composite Video Input Function Status
MOTOROLA ANALOG IC DEVICE DATA
3
MC44002 MC44007
ELECTRICAL CHARACTERISTICS
Parameter BUS REQUIREMENTS Maximum Output Low Voltage Isink = 1.0 mA, Device in "Read" Mode Maximum Sink Current VOL = 0.7 V, Device in "Read" Mode Minimum Input High Voltage Maximum Input Low Voltage Maximum Rise Time Between VIH and VIL Levels SCL Clock Frequency HORIZONTAL TIMEBASE FreeRunning Frequency (Calibration Mode) 17.734475 MHz Crystal. "NORM" Bit = 0; "H EN" Bit = 1 (Horizontal Drive Disabled) 14.31818 MHz Crystal. "NORM" Bit = 1; "H EN" Bit = 1 (Horizontal Drive Disabled) HLoop 1 (Pin 15 Current Forced to ± 20 µA) Minimum Frequency Maximum Frequency Frequency Range VCO Control Gain Phase Detector Gain "HGAIN1" Bit = 1; "HGAIN2" Bit = 0 Phase Detector Gain Reduction Factor "HGAIN1" Bit Switched from 1 to 0 "HGAIN2" Bit Switched from 0 to 1 Line Drive Output Saturation Voltage I12 = 1.0 mA Horizontal Drive Pulse Low Defined by Internal Counter, Deflection Transistor "Off", Period is 64 µs Horizontal Flyback Input Resistance V13 = 2.0 V Horizontal Flyback Clamping Voltages I13 = 500 µA I13 = 50 µA Horizontal Flyback Threshold Current Should be Externally Limited to 500 µA Peak by an External Resistor Horizontal Phase Control Range Flyback Duration: 12 µs External Delay Compensation From Horizontal Drive to Center of Flyback Pulse. Flyback Duration: 12 µs 31 15.39 15.42 12 13.85 16.05 12, 15 15 15 2.5 1.75 12 12 3.0 2.0 0.25 27 3.5 2.25 0.5 V µs 1.9 18 14.25 16.55 2.3 2.4 27 14.65 17.05 2.9 39 kHz/V µA/µs 15.625 15.75 15.85 15.98 kHz kHz VOL(max) Isink(max) VIH(min) VIL(max) tr(max) fSCL 5 5 5 5 4, 5 4 0.7 1.0 3.0 1.5 1.0 100 V mA V V µs kHz Symbol Pin Min Typ Max Unit
13 13
50
k V
13 30
5.7 0.5
µA
12 12, 13
8.0 6.0
12 18
µs µs
VERTICAL TIMEBASE (All Values are Related to Pin 3 Reference Current) Vertical Drive Amplitude (4:3 Display) (00) (32) (63) C6 = 82 nF, Assuming Zero Tolerance Capacitance, "VDI" Set to "1" Vertical Drive Amplitude Control Range (4:3 Display) C6 = 82 nF, Assuming Zero Tolerance Capacitance, "VDI" Set to "1", Vertical Amplitude Varied from (00) to (63) 7 1.15 1.55 1.95 1.33 1.75 2.18 1.5 1.95 2.4 V
7
0.75
0.85
1.0
V
4
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
ELECTRICAL CHARACTERISTICS (continued)
Parameter Symbol Pin Min Typ Max Unit
VERTICAL TIMEBASE (All Values are Related to Pin 3 Reference Current) Ramp Amplitude Ratio Between 4:3 and 16:9 Display Modes Vertical Amplitude = (32) Maximum Ramp Amplitude Change With 525/625 Mode Change Vertical Ramp Low Voltage (4:3 Display) Pin 6 Voltage Set to 0 V, "VDI" Set to "1", Vertical Position = (00) Vertical Ramp Low Voltage (16:9 Display) Pin 6 Voltage Set to 0 V, "VDI" Set to "0", Vertical Position = (00), Measured After 16:9 Holding Period Vertical Ramp High Voltage Pin 6 Open, "VDI" Set to "0" or "1", Vertical Position = (63) Vertical Ramp Position Control Range Versus Vertical Ramp Voltage at Vertical Position (32), Measured at Vm, "VDI" Set to "0" or "1", Vertical Position Varied from (00) to (63) Vertical Ramp Clamping Duration (tc) Defined by Internal Counter Maximum Output Source Current Maximum Output Sink Current Vertical Linearity (00) (63) Change in Ramp current as Pin 9 Current Varied from 0 to 6.4 µA Vertical Breathing Correction = (63) Vertical Breathing Correction = (00) Gain V7/V6 7 0.7 0.8 0.9
7 7
2.0 0.65
% V
7
0.85
V
7
4.15
V
7
±0.5
±0.75
±1.0
V
7 7 7 7
1.0 200
512 0.8 1.1
µs mA µA
6 0.15 0.75 0 0.95 1.3 1.0
µA
6, 7
0.9
V/V
EW CORRECTION (V6(b) = 0.2 V, V6(m) = 1.1 V, V6(e) = 2.0 V) Horizontal Amplitude (00) (63) Corner Correction = (00), Tilt = (32), Parabola Amplitude = (00), Measured at Tm. Parabola Amplitude (00) (63) Corner Correction = (00), Horizontal Amplitude = (32), Tilt = (32), Measured at Tb, Tm and Te. Corner Correction (00) (63) Horizontal Amplitude = (63), Parabola Amplitude = (00), Tilt = (32), Measured at Tb, Tm and Te. Parabola Tilt (00) (63) Corner Correction = (00), Horizontal Amplitude = (32), Parabola Amplitude = (32), Measured at Tb, Tm and Te. EW Drive Output Voltage 8 0 150 0.2 300 20 µA
8 0 100 0.2 250 10
µA
8 0 0.2 150 10 30
µA
8 1.9 1.9
8
1.0
VCC
V
MOTOROLA ANALOG IC DEVICE DATA
5
MC44002 MC44007
ELECTRICAL CHARACTERISTICS (continued)
Parameter Symbol Pin Min Typ Max Unit
EW CORRECTION (V6(b) = 0.2 V, V6(m) = 1.1 V, V6(e) = 2.0 V) EW DACs Differential NonLinearity Error At Minor Transitions: Steps 01: 12; 34; 78; 1516. At Major Transition: Step 3132 SYNC SEPARATOR Sync Amplitude to Operate the Device From Black to Sync, Black Picture, Standard Timing Specifications on Sync Signal Vertical Sync Separator Delay Time: td "INTSEL" = 0 "INTSEL" = 1 From Vertical Sync Pulse to Vertical Ramp Reset Vertical Sync Window 2, 40 22, 23, 24, 25 2, 40 2, 40, 22, 23, 24, 25 448 36 68 740 Half Lines 100 160 mV 8 1.0 2.0 1.0 1.0 LSB
µs
COMPOSITE VIDEO PROCESSING (All measurements in NORMAL mode, unless otherwise noted.) Composite Video Input Amplitude Load Impedance 75 , Less than 5% Distortion Video 1/Video 2 Input Crosstalk @ f = (2.0 MHz), Measured on Y1 Output Variable Input LPF CutOff Frequency 17.7 MHz Crystal Selected 14.3 MHz Crystal Selected Chroma Subcarrier Rejection PAL 4.43 MHz (17.7 MHz Crystal Selected) NTSC 3.58 MHz (14.3 MHz Crystal Selected) SECAM (FoR and FoB) (17.7 MHz Crystal Selected) Y1 Output Resistance Y1 Bandwidth (3.0 dB) PAL Minimum Peaking, "T3" Set to 1 (Input LPF "On") SECAM Minimum Peaking, "T3" Set to 0 (Input LPF "Off") Luma Peaking Range Measured at 3.0 MHz, 17.7 MHz Crystal Selected Luma Gain (@ 100 kHz) Overshoot Peaking at Step 3 (100) Source Impedance Luma Delay Range PAL/SECAM (17.7 MHz Crystal Selected) NTSC 3.58 (14.3 MHz Crystal Selected) Video In to Luma Out Delay Difference Between PAL and SECAM (MC44002 only) Luma Delay Minimum: (D1 D2 D3) = (0 0 0), Green to Magenta Transition, "T3" Set to 1 in PAL, to 0 in SECAM PAL/NTSC DECODER Chroma Output Variation For a Burst Input Varied from 60 mV to 600 mV Color Kill Attenuation Referred to Standard Color Video Input, Monochrome Mode Selected 36, 37 36, 37 40 3.0 dB dB 2, 40 29 29 29 25 25 18 29 29 2.5 2.5 29 2, 40, 29 29 2, 40 29 29, 40 280 350 260 ns 6.0 0.9 0 3.0 3.0 8.5 1.1 5.0 1.3 1.5 dB V/V % k ns 30 30 20 300 MHz 6.0 4.85 dB 0.7 1.0 1.4 40 Vpp dB MHz
6
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
ELECTRICAL CHARACTERISTICS (continued)
Parameter PAL/NTSC DECODER Color Difference Output Distortion @ 1.5 V Output Signal Residual Chroma Subcarrier Rejection PAL NTSC Referred to Video Input Oscillator PullIn Range PAL NTSC Referred to Nominal Subcarrier Frequency, with Ideal Xtal RY, BY Channel Separation BY/RY Amplitude Ratio At Standard Color Bars Signal BY/RY Amplitude Ratio Spread At Standard Color Bars Signal Minimum Burst Level for "ACC Active" Flag "On" Standard Set to PAL or NTSC, Increasing Burst Level Steps Minimum Burst Level for "PAL Identified" Flag "On" Standard Set to PAL or NTSC, Increasing Burst Level Steps Maximum Burst Level for "ACC Active" Flag "Off" Standard Set to PAL or NTSC, Decreasing Burst Level Steps Maximum Burst Level for "PAL Identified" Flag "Off" Standard Set to PAL or NTSC, Decreasing Burst Level Steps (BY) Color Difference Output Levels Relative to 75% Color Bars Hue DAC Control Range Hue Control Register Varying from (00) to (63) Chroma to Luma Delay PAL NTSC Measured on (BY) Output, Luma Delay Set to Minimum: (D1 D2 D3) = (0 0 0), Green to Magenta Transition, "T3" Set to 1 DELAY LINE CONTROL SIGNALS System Select PAL NTSC SECAM (MC44002 only) EXTERNAL Sandcastle Level 1 Level 2 Level 3 Level 4 See Figure 4 Sandcastle t1 t2 See Figure 4, Values Defined by Internal Counter 30 1.4 2.75 3.7 31 3.7 2.75 1..3 31 5.0 4.0 6.0 5.0 7.0 6.0 4.0 2.95 1.55 75 4.3 3.15 1.8 V V V mV µs 75 1.65 3.0 4.0 400 1.9 3.25 4.3 mV V V V 36, 37 36, 37 40 40 32, 33 ±350 ±400 Hz 5.0 % dB Symbol Pin Min Typ Max Unit
36, 37 36, 37 36, 37 2, 40
30 2.0
1.3 10
2.0 20
dB V/V dB mVpp
2, 40
5.0
20
mVpp
2, 40
5.0
mVpp
2, 40
1.0
mVpp
36 36, 37 29, 36
0.7 ±20
1.1
1.5
V Deg ns
80 100
MOTOROLA ANALOG IC DEVICE DATA
7
MC44002 MC44007
ELECTRICAL CHARACTERISTICS (continued)
Parameter Symbol Pin Min Typ Max Unit
SVHS VIDEO PROCESSING (SVHS Set to 0, "T3" Set to 0) Y1 Bandwidth Luma Peaking Set to Minimum Minimum Burst Level for "ACC Active" Flag "On" Standard Set to PAL or NTSC, Increasing Burst Level Steps Minimum Burst Level for "PAL Identified" Flag "On" Standard Set to PAL or NTSC, Increasing Burst Level Steps Maximum Burst Level for "ACC Active" Flag "Off" Standard Set to PAL or NTSC, Decreasing Burst Level Steps Maximum Burst Level for "PAL Identified" Flag "Off" Standard Set to PAL or NTSC, Decreasing Burst Level Steps Video In to Luma Out Delay Difference Between SVHS and Normal Mode Luma Delay Minimum in Normal Mode, Set to Step 6 in SVHS Mode, Green to Magenta Transition, "T3" Set to 1 in Normal Mode, to 0 in SVHS Mode Chroma to Luma Delay Difference Between SVHS and Normal Mode Measured on (BY) Output, Luma Delay Minimum in Normal Mode, Set to Step 6 in SVHS Mode, Green to Magenta Transition, "T3" Set to 1 in Normal Mode, to 0 in SVHS Mode SECAM DECODER (MC44002 ONLY) Minimum Subcarrier Level for "SECAM Identified" Flag Measured at foR Color Kill Attenuation Monochrome Mode Selected Referred to Color Difference Output Signal with SECAM Selected and Identified Color Difference Zero Level Error Relative to 75% Color Bars, Difference Between Signal Measured at t1 and Active Black Level (Black Bar) Color Difference Output Distortion Subcarrier Level at foR = 20400 mV @ 1.5 V Output Signal Transient Response (BY) (RY) Generator Rise Time 600 ns (BY), Green to Magenta Transition, Measured Between 10% and 90% Levels BY/RY Amplitude Ratio Ratio Spread Relative to 75% Color Bars Residual Carrier and Harmonics (4.0 to 13.5 MHz) At Standard Color Bars Signal (BY) Color Difference Output Levels Relative to 75% Color Bars PAL/SECAM Color Difference Ratio Nominal Input Signals 2, 40 10 20 mVpp 29 2, 40 3.2 3.5 10 20 MHz mVpp
2, 40
5.0
20
mVpp
2, 40
5.0
mVpp
2, 40
1.0
mVpp
2, 40, 29
310
ns
29, 36, 2, 40
60
ns
36, 37
40
50
dB
36, 37
±1.0
±3.0
%
36, 37
5.0
%
36 37 650 750 800 900
ns
36, 37 2.0 1.3 1.1 1.0 2.0 1.0 1.2 V/V dB % V
36, 37 36 36
0.8
8
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
ELECTRICAL CHARACTERISTICS (continued)
Parameter SECAM DECODER (MC44002 ONLY) Chroma to Luma Delay Luma Delay Set to Minimum: (D1 D2 D3) = (0 0 0), Green to Magenta Transition, "T3" Set to 0 Patterning Full Screen 75% Color Frequency, 500 kHz Low Pass Filter, Relative to Black to Color Output Signal Line to Line Luma Levels Difference Full Screen 75% Yellow Color Frequency, Relative to Black to Yellow Output Signal Chroma to Luma Delay Difference Between PAL and SECAM Measured on (BY) Output, Luma Delay Set to Minimum: (D1 D2 D3) = (0 0 0), Green to Magenta Transition, "T3" Set to 0 in SECAM, to 1 in PAL COLOR DIFFERENCE STAGES RGB Input Amplitude Black to Peak (Less than 5% Distortion at RGB Outputs) Fast Commutate Low Level High Level Y2 Input Amplitude (Less than 5% Distortion at RGB Outputs) Color Difference Input Amplitude (Less than 5% Distortion at RGB Outputs) Y2/Y1 Crosstalk Measured at RGB Outputs, Measured at f = (2.0 MHz) RGB to Y Crosstalk Measured at RGB Outputs, Measured at f = (2.0 MHz) RGB Transconductance Bandwidth (@ 1.0 dB) 22, 23, 24 21 1.0 25 26, 27 25, 29 22, 23, 24, 25, 29 24, 17, 23, 18, 22, 19 10, 17, 18, 19 10, 17, 18, 19 0.562 90 0.344 237 0.9 100 0.3 236 0.9 106 0.3 240 0.91 106 0.31 246 0.7 1.0 40 40 0.5 1.4 1.8 30 30 Vpp Vpp dB dB 500 700 1000 mVpp 29, 36 420 ns Symbol Pin Min Typ Max Unit
36
5.0
%
29
1.5
%
29, 36
340
ns
V
6.5
MHz
Gain Reduction in ACL Mode Pin 10 Voltage Varying from 0 to 5.0 v Gain Reduction Sensitivity in ACL Mode Pin 10 Voltage Varying from 2.0 to 2.5 V Demodulation Angles and Amplitudes Mode A Rm Ra Gm Ga Mode B Rm Ra Gm Ga Mode C Rm Ra Gm Ga Mode D Rm Ra Gm Ga Definitions: Rm/Gm = Module, Ra/Ga = Argument
12.5 20
dB dB/V Deg
MOTOROLA ANALOG IC DEVICE DATA
9
MC44002 MC44007
ELECTRICAL CHARACTERISTICS (continued)
Parameter RGB OUTPUT STAGES Low Dark Sample Output Current Red Green Blue Dark Sample Cathode Current 5.0 to 15 µA, DC DAC Set to Full Scale, See Figure 1 High Dark Sample Output Current Red Green Blue Dark Sample Cathode Current 5.0 to 15 µA, DC DAC Set to Zero, See Figure 1 Blanking Output Current Maximum Y to RGB Output Transconductance Gain DAC Set to Full Scale Brightness (00) (63) Wrt Dark Sample Cathode Voltage, High Voltage Output Stage Transimpedance 39 k, Dark Sample Cathode Current 15 µA, Dark Sample Cathode Voltage 140 V RGB Dark Sample Current Intensity Range RGB Intensity DACs Varying from (00) to (63) Bright to Dark Sample Current Ratio Leakage Loop Sink Current Source Current Average Beam Current Detection Level Excess Flag Overload Flag Peak Beam Current Detection Level 17, 18, 19 mA 3.15 3.15 3.15 Symbol Pin Min Typ Max Unit
17, 18, 19
mA 3.95 3.95 3.95
17, 18, 19 17, 18, 19
6.0 6.0
7.0
8.0
mA mA/V V
30 20
20 20 20
15 8.0 20 5.0
20 9.5 1.0 1.2 6.8
11
dB µA/µA µA
9 0.9 1.3 1.1 1.1 7.1
V
20
6.5
V
Figure 1. Example of Output Circuitry
VP RFDBK RP lodk Pins 17, 18, 19 MC44002/7P Vref
Vp, Vref, RFDBK and Rp values will determine the exact operating point. For example, let us take: Vp = 5.0 V RFDBK = 39 k Vref = 3.6 V Rp = 6.8 k The formula giving the Dark Cathode Voltage with above circuit is: Vdk = Vref + RFDBK*(Vref Vp + lodk*Rp) / Rp
Vdk
Picture Tube Cathode
With above application, component values and lodk specifications, all 3 cathodes on all devices will always have a range of at least 120 V to 150 V. By changing the values of Vp, Vref and Rp, the cathode voltage range may be shifted up or down as required.
10
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
Figure 2. Vertical Waveforms
1.6 ms 18.4 ms
Video Signal Tb Tm Te
Vertical Ramp Waveform td tc Vb Vm Ve
Parabola Waveform
Ib
Im
Ie
Figure 3. Vertical Ramp Positions (V7 versus V6)
Pin 7 Voltage (V) 4 V Ramp High Voltage
3
(63)
(32)
(00)
2 (XX) = Values of (80) Register
1 V Ramp Low Voltage Pin 6 Voltage (V) 1 2 3 4
MOTOROLA ANALOG IC DEVICE DATA
11
MC44002 MC44007
Definitions Parabola Amplitude Parabola Tilt
+ (ib ) ie) im 2 + im
Vertical Amplitude Vertical Linearity
+ Ve Vb
b
+
(i ei ) b Parabola Amplitude
+ (VeVm) V mV
Horizontal Amplitude
Corner correction is calculated in the same way as Parabola Amplitude. Figure 4. Sandcastle Output (Pin 31)
1
2
3
4 t1
t2 64 µs
GENERAL DESCRIPTION OF THE CHROMA 4 SYSTEM
Figure 5 shows a simplified block diagram representation of the basic system using the MC44002/7 and its companion device the MC44140 chroma delay line. The MC44002/7 has been designed to carry out all the processing of video signals, display controls and timebase functions. There are two video inputs which can be used for normal composite video or separate Y and C inputs. In either case, the inputs are interchangeable and selection is made via the I2C bus. The video is decoded within the MC44002/7 and involves separation, filtering, delay of the luminance part of the signal and demodulation of the chroma into color difference signals. The luminance (called Y1) together with the demodulated R-Y and B-Y are all then brought out from the IC. The color difference signals then enter the MC44140 which performs color correction in PAL and the delay line function in SECAM. Corrected color difference signals then re-enter the MC44002/7.
12
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
Figure 5. Connection to TV Chassis
5.0 V Line Output Transformer H-Flyback H-Drive Y1 Out R-Y Out B-Y Out MC44140 Ext R-Y Ext B-Y R-Y In B-Y In Line O/P Stage Anode Current Analog Contrast E-W Drive E-W Amplifier V-Scan Coils V-Drive V O/P Stage G1 G2 G3 R-O/P Fast Commutate G-O/P 17.7 MHz B-O/P 14.3 MHz Feedback I2C Bus Clock Data 0V B G B G R R Diode Modulator Beam Current Limitation 12 V Linearity H-Scan Coils H.T. Tripler Comp Video or S-VHS Video 1 Video 2 Focus EHT
26 V
Y2 In R In G In B In
MC44002/7
EHT
The next stage is called the color difference stage where a number of control functions are carried out together with matrixing of the components to derive RGB signals. At this point a number of auxiliary signals may also be switched in, again all under MCU control. External RGB (text) and Fast Commutate enter here; also an external luminance (Y2) may be used instead of Y1. External R-Y and B-Y are switched in via the delay line circuit to save pins on the main device. The Y2 and External R-Y, B-Y will obviously be of considerable benefit from the system point of view for use with external decoders. The final stage of video processing is the RGB outputs which drive the high voltage amplifiers connected to the tube cathodes. These outputs are controlled by a sophisticated digital servo-loop which is maintained and stabilized by a sequentially sampled beam current feedback system. Automatic gray scale control is featured as a part of this system. Both horizontal and vertical timebases are incorporated into the MC44002/7 and control is via the I2C bus. The MOTOROLA ANALOG IC DEVICE DATA
horizontal timebase employs a dual loop system of a PLL and variable phase shifter, and the vertical uses a countdown system. For the vertical, a field rate sawtooth is available which is used to drive an external power amplifier with flyback generator (usually a single IC). The line output consists of a pulse which drives a conventional line output stage in the normal way. The line flyback pulse is sensed and used by the second loop for horizontal phase shift. Where E-W correction is required, a parabola waveform is available for this which, with the addition of a power amplifier, can be used with a diode modulator type line output stage for dynamic width and E-W control. The bottom of the EHT overwinding is returned to the MC44002/7 and is used for anode current monitoring. Fast beam current limitation is also made possible by the use of an analog contrast control. A much more detailed description of each stage of the MC44002/7 will be found in the next section. Information on the delay line is to be found in its own data sheet. 13
MC44002 MC44007
Introduction The following information describes the basic operation of the MC44002/7 IC together with the MC44140 chroma delay line. The MC44002/7 is a highly advanced circuit which performs all the video processing, timebase and display functions needed for a modern color TV. The device employs analog circuitry but with the difference that all its advanced features are under processor control, enabling external filtering and potentiometer adjustments to be removed completely. Sophisticated feedback control techniques have been used throughout the design to ensure stable operating conditions and the absence of drift with age. The IC described herein is one of a new generation of TV circuits, which make use of a serial data bus to carry out control functions. Its revolutionary design concept permits a level of integration and degree of flexibility never achieved before. The MC44002/7 consists of a single bipolar VLSI chip which uses a high density, high frequency, low voltage process called MOSAIC 1.5. Contained within this single 40 pin package is all the circuitry needed for the video signal processing, horizontal and vertical timebases and CRT display control for today's color TV. Furthermore, all the user controls and manufacturer's set-up adjustments are under the control of the processor I2C bus, eliminating the need for potentiometer controls. The MC44002/7 offers an enormous variety of different options configurable in software, to cater to virtually any video standard or circumstance commonly met. The decoder section offers full multistandard capability, able to handle PAL, SECAM (MC44002 only) and NTSC standards with 4 matrix modes available. Practically all the filtering is carried out onboard the IC by means of sampled data filters, and requires no external components or adjustment. I2C Bus It is not within the scope of this data sheet to describe in detail the functioning of the I2C bus. Basically, the I2C bus is a two-wire bidirectional system consisting of a clock and a serial data stream. The write cycle consists of 3 bytes of data and 3 acknowledge bits. The first byte is the Chip Address, the second the Sub-address to identify the location in the memory, and the third byte is the data. When the address' Read/Write bit is high, the second and third bytes are used to transmit status flags back to the MCU. Figure 6 shows a block diagram of the MC44002/7 Bus Interface/Decoder. To begin with, the start bit is recognized by means of the data going low during CLK high. This causes the Counter and all the latches to be reset. For a write operation, the Write address ($88) is read into the Shift Register. If the correct address is identified, the Chip Address Latch is set and at CLK 9 an acknowledge is sent. The second byte is now read into the Shift Register and is used to select the Sub-address. At CLK 18 a Sub-address Enable is sent to the memory to allow the Data in the register to be changed. Also, at CLK 18 another acknowledge is sent. The third byte is now read into the Shift Register and the Data bussed into the memory. The Data in the Sub-address location already selected is then altered. A third acknowledge is sent at CLK 27 to complete the cycle. A Read address ($89) indicates that the MCU wants to read the MC44002/7 status flags. In this instance, the Read/Write Latch is set, causing the Memory Enable and Subaddress Enable to be inhibited, and the flags to be written onto the data line. Two of the status flags are permanently wired one-high and one-low (O.K. and Fault), to provide a check on the communication medium between the MC44002/7 and the MCU. At start-up the Counter is automatically reset and the Data for each Sub-address is read in from the MCU. Only after the entire memory contents have been transmitted, is Data 00 sent to register 00 to start the Horizontal Drive. The MC44002/7 needs the full 27 clock cycles, or a stop condition, to properly release the I2C bus.
Digital Interface One of the most important features of MC44002/7 is the use of processor control to replace external potentiometer and filter adjustments. Great flexibility is possible using processor control, as each user can configure the software to suit their individual application. The circuit operates on a bidirectional serial data bus, based on the well known I2C bus. This system is rapidly becoming a world standard for the control of consumer equipment. Figure 6. I2C Bus Interface and Decoder
Start-Bit Recognition 4 Clock Clock Counter Reset
5 Data 8-Bit Shift Register 8-Bit 8-Bit
Read/Write Latch
Acknowledge
8-Bit Memory & Sub-Address Decoding
Chip-Address Latch
Sub-Address Latches
14
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
Figure 7. MC44002/7 Memory Map
Data 7 MSB Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 LSB Memory Sub-Address 77 Digital Register, Bits 0-7 Bits 6,7 Bits 6,7 Bits 6,7 Memory Sub-Address 7A Analog Register, Bits 0-5 Bits 6,7 Bits 6,7
Memory Sub-Address 78 Analog Register, Bits 0-5
Memory Sub-Address 79 Analog Register, Bits 0-5
Memory Sub-Address 87 Analog Register, Bits 0-5
D A I-78
D A I-79
D A I-7A
D A I-87
D A I-88
Memory Figure 7 shows a diagram of the MC44002/7 Memory Map. It has 18 bytes of memory which are located at hex sub-addresses 77 to 88. Sub-address 77 is used to set up the vertical timebase mode of the IC and for S-VHS switching, and consists of 8 separate data bits. The remaining 17 bytes use the least significant 6-bits as an analog control register. The contents of each are D/A converted, providing an analog control current which is distributed to the appropriate part of the circuit. Bits 6 and 7 are used singularly for switching control functions. Chroma Decoder The main function of this section is to decode the incoming composite video, which may be in any of the PAL, NTSC or SECAM (MC44002 only) Standards, and to retrieve the luminance and color difference signals. In addition, the signal filtering and luma delay line functions are carried out in this section by means of sampled data filters. The entire decoder section operates in sampled data mode using clocks generated by external crystals. The oscillator, which is phase-locked in the usual way for PAL/NTSC modes, provides the clock function for the whole circuit. The crystals are selected by the MCU by means of a control bit (XS). Only crystals appropriate to the standards which are going to be received need to be fitted. A 17.7 MHz crystal (4x PAL subcarrier) is used for PAL and SECAM systems (50 Hz, 625 lines); and 14.3 MHz (4x NTSC subcarrier) for the NTSC system (60 Hz, 525 lines). Nearly all the filters, together with the luma delay line and peaking, have been integrated, requiring no external components or any adjustment. The filter characteristics are entirely determined by the clocks and by capacitor ratios, and are thus completely independent of variations in the manufacturing process. The PAL/NTSC subcarrier PLL and ACC loop filters have not been integrated in order to facilitate testing. These filters consist of fixed external components. Figure 8 is a block diagram of the main features of the chroma decoder. Selection is first made between the Video 1 and Video 2 inputs. These may be either normal composite video or separate luma and chroma which may enter the IC at either pin. Commands from the MCU are used to route the signals through the appropriate delay and filter sections.
In PAL/NTSC, a variable low pass filter, which can be software bypassed (control bit T3), is then used to compensate for IF filtering and the Q of the external sound traps. Filter response is controlled by means of control bits T1 and T2. It is not recommended to use this filter in SECAM or in SVHS, as lumachroma delays will not be optimized. Next, the video enters the luma path. The PAL/NTSC or SECAM chroma signals are separated out by transversal high pass filters. In SECAM mode, the chroma trap frequency is dynamically steered to follow the instantaneous frequency of the chroma. Then, another transversal filter provides luma peaking, which is also active in SVHS mode. The high frequency luma may be peaked (at about 3.0 MHz with the 17.7 MHz crystal, and 2.4 MHz with the 14.3 MHz crystal) in 7 steps up to a maximum of 8.5 dB, by a control word from the MCU. Another control word is used to trim the delay in the luma channel. Five steps of 56 ns (70 ns with the 14.3 MHz crystal) are possible, giving a total programmable delay of 280 ns. Steps 6 and 7 are used in SVHS mode. The resulting processed luma signal then proceeds to the color difference section after being lowpass filtered by an active filter to remove components of the crystal frequency, and twice that frequency. The luma component (Y1) is made available at Pin 29 for use with auxiliary external functions, as well as testing. When in the SVHS mode, the SVHS control bit controls the signal paths. The luma signal bypasses the first section of the luma channel, which contains the chroma trap. The SVHS chroma is passed directly to the PAL/NTSC decoder without further filtering. As all the delay and filter responses are determined by the crystal, they automatically commute to the new standard when the crystal is changed over. Thus, when the 14.3 MHz clock is being used, the chroma trap moves to 3.58 MHz. The filtered PAL/NTSC and SECAM chroma signals are decoded by their respective circuits. The PAL/NTSC decoder employs a conventional design, using ACC action for gain control and the common double balanced multipliers to retrieve the color difference signals. The SECAM decoder is discussed in a separate subsection.
Memory Sub-Address 88 Analog Register, Bits 0-5
MOTOROLA ANALOG IC DEVICE DATA
15
MC44002 MC44007
Figure 8. Chroma Decoder
S-VHS Video 1 Video 2 40 2 Input Select S-VHS PAL/NTSC (MCU) PAL/NTSC Decoder ACC PLL 17.7MHz 33 32 14.3MHz Oscillator C Crystal Select SECAM Decoder AGC Q C 1 39 U V (MCU) System Select Hue Controls R-Y B-Y 37 R-Y 4.4/8.8MHz 11 SECAM Cal Loop
NOTES: SECAM decoding available in the MC44002 only.
Syn Sep t1, t2
LumaChroma Filters t3 Peaking Ident Data (MCU) 38
Luma Delay Line Delay ADJ
29 Y1 Luma To Color Difference Stage
Ident
4.4/8.8MHz 36 B-Y
The actual decision as to a signal's identity is made by the MCU based on data provided by 3 flags returned to it, namely: ACC Active, PAL Identified, and SECAM Identified. Control bits SSASSD must be sent to set the decoder to the correct standard. This allows a maximum of flexibility, since the software may be written to accommodate many different sets of circumstances. For example, channel information could be taken into account if certain channels always carry signals in the same standard. Alternatively, if one standard is never going to be received, the software can be adapted to this circumstance. If none of the flags are on, color killing can be implemented by the MCU. This occurs if the net Ident Signal is too low, or if the ACC circuit is inactive due to too low a signal level. The demodulated color difference signals now enter the Hue control section, where selection is made between PAL/NTSC and SECAM outputs. The Hue control is simply realized by altering the amplitudes of both color difference signals together. Hue control is only a requirement in NTSC mode and would not normally be used for other standards. The function is usually carried out prior to demodulation of the chroma by shifting the phase of the subcarrier reference, causing decoding to take place along different axes. In the MC44002/7, Hue control is performed on the already demodulated color difference signals. A proportion of the R-Y signal is added or subtracted to the B-Y signal and vice-versa. This has the same effect as altering the reference phase. If desired, the MC44002/7 can apply the Hue control to simple PAL signals. After manipulation by the Saturation and Hue controls, the color difference signals are finally filtered to reduce any remaining subcarrier and multiplier products. Before leaving the chip at Pins 36 and 37, the signals are blanked during line
and frame intervals. The 64 µs chroma delay line is carried out by a companion device, the MC44140. SECAM Decoder (MC44002 only) The SECAM signal from the high-pass filter enters tightly controlled AGC amplifiers wrapped around a cloche filter which is a sampled recursive type, with the AGC derived from a signal squarer. Next, the signal is blanked during the calibration gate period and a reference 4.43 MHz is inserted during this time. The SECAM signal is then passed through a limiter. The frequency demodulator function is carried out by a frequency-locked-loop (F.L.L.). This consists of three components: a tracking filter, a phase detector and a loop filter. The center frequency of the tracking filter depends on three factors: internal R-C product, ADJUST voltage, and TUNING voltage. The tracking filter is dynamically tuned by the TUNING feedback from the loop-filter forming the F.L.L. The ADJUST control calibrates the F.L.L. and compensates for variations in the R-C product. After the F.L.L., the color difference signals are passed to another block where several functions are carried out. The signals are de-emphasized and outputs are provided to the Ident section. Another function of this section is to generate the ICOMP signal used for calibrating the F.L.L. This signal is blanked during the H-IG period to ensure that (R-Y) and (B-Y) output signals have a clean dc level for clamping purposes. In addition, components are added to compensate for the R-C product, and tuning offsets are introduced during the active lines for F0R/F0B. Calibration of the F.L.L. takes place during every field blanking interval, starting from field retrace and ending just before the SECAM vertical Ident sequence (bottles). The calibration current ICAL is derived from ICOMP during the
16
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
calibration gate (CAL) and integrated by an external capacitor on Pin 11. The resulting voltage VEXT is then transformed to generate the ADJUST control voltage removing from the loop range most of the variations due to internal RC products and temperature. Color Difference Stages This stage accepts luminance and color difference signals, together with external R,G,B and Fast Commutation inputs and carries out various functions on them, including clamping, blanking, switching and matrixing. The outputs, consisting of processed R,G,B signals, are then passed to the Auto Gray Scale section. A block diagram of this stage is shown in Figure 10. The Y2, R-Y, B-Y together with R, G and B are all external inputs to the chip. The Y1 signal comes from the decoder section. Each of the signals is back-porch clamped and then blanked. The Y2 and R,G,B inputs have their own simple sync separators, the output from which may be used as the primary synchronization for the chip by means of commands from the MCU. The Fast Commutation is an active high input used to drive a high speed switch; for switching between the Y and color difference inputs and the R,G,B (text) inputs. After blanking, the Y1 and Y2 channels go to the Luma Selector which is controlled by means of 2 bits from the MCU. From here the selected luma signal goes to the RGB matrix. The two color difference signals pass through the saturation control. From here they go to a matrix in which G-Y is generated from the R-Y and B-Y, and lastly, to another matrix where Y is added to the three color difference signals to derive R,G,B. Control bits (via the I2C bus) allow the matrix coefficients to be adjusted in order to suit different requirements, particularly in NTSC. Table 1 shows the theoretical demodulation angles and amplitudes and the corresponding matrix coefficient values for each of the 4 selectable modes. (The A mode corresponds to the standard PAL/SECAM/NTSC mode). Although primarily intended for NTSC, this feature can also act on PAL/SECAM or external RGB signals. The R,G,B inputs may take one of two different paths. They may either go straight to the output without further processing, or via a separate matrix and the saturation control. The path taken is controlled in software. When the latter route is selected, the R,G,B signals undergo a matrix operation to derive Y. From this, R-Y and B-Y are easily derived by subtraction from R and B; the derived color difference signals are then subjected to saturation control. This extra circuitry allows another feature to be added to the TV set, namely the ability to adjust the color saturation of the RGB inputs. After the saturation control the derived signals are processed as before.
Table 1. Matrix Modes Coefficients
A RR RB GR GB BB BR Rm Gm Ra Ga 1.0 0 0.513 0.187 1.0 0 0.562 0.344 90 237 B 1.577 0.156 0.443 0.168 1.0 0 0.9 0.3 100 236 C 1.539 0.248 0.462 0.150 1.0 0 0.9 0.3 106 240 C 1.556 0.251 0.504 0.125 1.0 0 0.91 0.31 106 246
NOTE: BB = Gain of (Bout/(BY)in) = 1 (reference). BR = Gain of (Bout/(RY)in) = 0 (theoretically).
Figure 9. SECAM Decoder (MC44002 only)
AGC Squarer X2 SECAM I/P A1 Cloche Filter A2 4.43MHz H Calibration Switch Adjust VTun H Clamp Loop Filter CAL Limiter FLL Tracking Filter FLL Demodulator Phase Detector
VA1 Adjust RC-T Compensation ICAL 11 SECAM Cal Loop ICOMP CAL
Ident Out
PHIG
IRC
Fbk
De-emphasis Tuning Offsets Output Interface
SECAM Out Timing Signals (R-Y/B-Y Sequen.)
MOTOROLA ANALOG IC DEVICE DATA
17
MC44002 MC44007
Figure 10. Color Difference Stages
Inputs
F/C 21 Fast Commutation
R 24
G 23
B 22
Sync Separator
Clamp
Clamp
Clamp YX EN
Blanking B G Burst Gate R Bypass
Y Matrix
Blanking
Blanking/Fast Commutation Logic
B-Y Gen
Gate 17 Saturation Control R
Matrix
R-Y Gen R-Y 27
Gate
18
G
Clamp
19 Outputs
B
Inputs
B-Y 26 BCL Clamp Blanking Gate 10 Y2 25 Sync Separator Y1 Y2 Luma Selector Y1 Analog Contrast
Clamp
Clamp Y1, Y2 Select 28 Y1 Clamp
18
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
In order to implement automatic beam current limiting (BCL), the possibility of fast contrast reduction has been added. For normal operation, the Contrast control is achieved by auto grey scale output loops and is I2C bus controlled (see Section 4). In the case of excess beam current, this control is not fast enough to protect the tube and power supply stages. It is now possible, by acting on the Pin 10 voltage, to reduce the contrast about 12 dB by reducing the luma gain and saturation. In the case of direct RGB mode, the RGB gains are also reduced. Figure 11. Typical Contrast Reduction
1.0 RELATIVE CONTRAST LEVEL (dB) 1.0 3.0 5.0 7.0 9.0 11 13 0 1.0 2.0 3.0 4.0 5.0 PIN 10 VOLTAGE (V)
Auto Gray Scale Control Loops This section supplies current drives to the RGB cathode amplifiers and receives a signal feedback from them, proportional to the combined cathode currents. The current feedback is used to establish a set of feedback loops to control the dc level of the cathode voltage (cutoff), and gain of the signal at the cathode (white balance). There are three loops to control the dark currents dark loops and another three to control the gains bright loops. The system uses 3 lines at the end of the vertical suppression period and just before the beginning of the picture for sampling the cathode current (i.e., one line for red, one for green and one for blue). The first half of reach line is used for adjusting the gain of the channel and is usually called the "bright" adjustment period. The second half of the line is used for adjusting the dc level of the channel and is called the "dark" adjustment. The theoretical circuit diagram for one channel is shown in Figure 13 along with the basic equations. The dc level (ldc) and gain (G) are both controlled by 7 bit DACs which receive data directly from latches in which the required values are stored between sampling periods. Figure 13. Bright/Dark Current Control
Brightness (B) Bright Gain (G) Output Buffer (A) Pins 17, 18 or 19
Figure 11 is showing the typical analog CONTRAST reduction possible as a function of the voltage on Pin 10. Two solutions are possible for obtaining the BCL function: 1st solution: A measure of the average and/or peak beam current is applied to Pin 10, which causes a reduction of the RGB drive levels to the high voltage video amplifiers. In this case, no software control is required, but variations in color balance and saturation may be observed. A typical application is shown in Figure 12. 2nd solution: The beam current flags are read and acted on by the MCU, which reduces the I2C bus CONTRAST control to maintain the average beam current below the desired level. In the case of rapid and extreme beam current changes (black to white picture at high contrast level), the circuit of Figure 12 may be used as a fast aging protection while the MCU is reducing the CONTRAST through I2C bus. The average of this method is to make any color balance/saturation variation only transient. Figure 12. Automatic Beam Current Limiter Application
EHT
ICont
Dark Bright IPict Dark
IO IDC
Picture Output Current: IO(Pict) = A x [ IDC = G x ((B x ICont) + IPict)] Dark Sample Output Current: IO(dk) = A x IDC Bright Sample Output Current: IO(br) = IO(dk) A x G X ICont Black Level Output Current: IO(bk) = IO(dk) B x A x G x ICont Black Level Output Current: IO(bk) = IO(dk) x B x [IO(dk) IO(br)]
10 k R1
10 n R3 33 k R8 270 k C2
4.7 µ C3 D1 1N4148 R9 2.2 M C5
12 V 1.0 M R4
C1
10 n
470 n
9
10
A block diagram of the complete system is illustrated in Figure 16. Data words from the MCU which represent the RGB color temperatures selected at the factory, are stored in Latches 1,2,3 and D/A converted by DAC1,2,3 to reference currents. During the bright adjustment period, a reference current pulse, whose amplitude depends on the Contrast setting, is output to the cathode of the tube. The gain control is adjusted to bring the feedback current to the same value as the bright reference current, which is defined by the color intensity setting of the output considered. The currents must match each other. If not, a current will flow in resistor R producing an error voltage. This is then buffered into comparators Comp1, 2 and is compared with voltage references Vref1 and Vref2. If the error voltage is greater than Vref1, Comp1 causes the counter to count up. If the error voltage is less than Vref2, Comp2 sends a count-down command. In this way, a "deadband" is set up to prevent the outputs from continuously changing. With the color intensity DAC set to about 32d, the bright cathode current is 100 µA (10 times the dark current). During Load the contents of the counter are loaded into Latch 6 (for red dc) and then D/A converted. The resulting dc current is then applied as an offset to the red output amplifier, completing the loop. During the dark adjustment period, the same intensity data is used but divided by a common factor (typically 10). A black level reference pulse is applied and the feedback loop adjusts the dc levels of the cathode to obtain a set of cathode currents equal to the dark reference currents 19
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
(10 µA). Therefore, the image color will always be adjusted to match the dark level color, i.e. grey scale tracking is ensured. The Load/Backload sequencer is used to control which latch is being addressed at any given time by means of the timing signals input to it. The backload command sends the data from the appropriate latch to the Up/Down Counter, ready to be modified if necessary. The Brightness control is affected by simply changing the dc pedestal of all three drives by the same amount, and does not form part of the feedback loop. The Contrast is adjusted to a set of values dependent on the level of the bright pulse applied during the setup period. This level is set by a control word from the MCU. Once the loops have stabilized under normal working conditions, they may be deactivated by means of a control bit from the MCU. When, however, any change is made to either contrast or RGB intensity, the loops must be reactivated. For normal operation, it is not necessary to deactivate the bright loops. Increasing the RGB intensity values will cause the BlacktoWhite cathode voltage amplitude to increase for a given Contrast setting. The White balance can therefore be set by adjusting the relative values of R, G and B intensity. An extra loop has been included via Latch 4 and DAC 4, which operates during the field flyback time to compensate for offsets within the loop. This has the effect of counteracting any input offset from the Buffer/Amp and will also compensate for cathode leakage should this be needed. A second output of the reference currents from the RGB DACs are used to compare with preset limits, to ensure that the loops are working within their range of control. Should the limits be exceeded in either direction, flags are returned to the MCU to request that the G2 control be adjusted up or down as appropriate. Once setup, the servo loops maintain the same conditions throughout the life of the TV. Horizontal Timebase The horizontal timebase consists of a PLL which locks up to the incoming horizontal sync, and a phase detector and shifter whose purpose is to maintain the H-Drive in phase with the line flyback pulse. Because of on-chip component tolerances, the free-running oscillator frequency cannot be set more accurately than ± 40%; this range would be too much for the line output stage to cope with. For this reason the free-running frequency is calibrated periodically by other means. During startup and whenever there is a channel change, the phase detector is disconnected from the VCO for 2 lines during the blanking interval. A block diagram of the line timebase is given in Figure 14. The calibration loop consists of a frequency comparator driving an Up/Down Counter. The count is D/A converted to give a dc bias which is used to correct a 1.0 MHz VCO. The 1.0 MHz is divided by 64 to give line frequency and this is returned to the frequency comparator. This compares Fh from the VCO with a reference derived from dividing down the subcarrier frequency. Any difference in frequency will result in an output from the comparator, causing the counter to count up or down; and thus closing the loop. Since the horizontal oscillator is quite stable, this calibration does not need to be carried out very often. After switchon, the calibration loop need only be enabled when the timebase goes out of lock. A Coincidence Detector looks at the PLL Fh and compares it with the incoming H-sync. If they are not in lock, a flag is returned to the MCU. To allow for use with VCRs, the gain of the phase detector may be switched by means of commands from the MCU (bits HGAIN1 and HGAIN2). The gain of the phase detector is switched to the maximum value at the end of the vertical sync pulse and then reduced to the selected value after about 11 lines. This allows the horizontal timebase to rapidly compensate any horizontal phase jump (e.g. with a VCR) during the vertical blanking period, thus avoiding bending at the top of the picture. Twice line frequency is output from the PLL which may be divided by either 1 or 2 depending on the command of the MCU. The x2 Fh will be used with Feature Boxes. The phase of the Fh and flyback pulses are compared in a phase detector, whose output drives a phase shifter. A 6-bit control word and D/A converter are used to apply an offset to the phase detector giving a horizontal phase shift control. The presence of the horizontal flyback pulse is detected; if it is missing a warning flag is sent back to the MCU which can take appropriate action. Vertical Timebase The vertical timebase consists of two sections; a digital section which includes a vertical sync separator and standard recognition; and an analog section which generates a vertical ramp which may be modified under MCU control to allow for geometrical adjustments. A parabola is also generated and may be used for pin-cushion (E-W) correction and width control (see Figure 15). In the digital section, the MC44002/7 uses a video sync separator which works using feedback, such that the threshold level of a comparator (slice level) is always maintained at the center of the sync pulse. Sync from any of the auxiliary inputs may also be used. The composite sync is fed to a vertical sync separator, where vertical sync is derived. This consists of a comparator, up/down counter and decoder. The counter counts up when sync is high, and down when sync is low. The output of the decoder is compared with a threshold level, the threshold only being reached with a high count during the broad pulses in the field interval. When "Auto Countdown" is selected, the vertical timebase in fact starts off in the "Injection Lock" mode. This means that the timebase locks immediately to the first signal received, in exactly the same way as an old type injection locked timebase. A coincidence detector looks for counts of the right number (525 e.g.), and causes a 4 bit counter to count up. When there are 8 consecutive coincidences, the vertical countdown is engaged, and the MSB of the counter is brought out to set the flag. Similarly, noncoincidence, which will occur if synchronizing pulses are missing or in the wrong place, or if there is noise on the signals, causes the counter to count down. When the count goes back to zero, after 8 noncoincidences, the timebase automatically reverts to "Injection Lock" mode. If it is known that lock will be lost (e.g., channel change), it is possible to jump straight into Injection Lock mode and not have to wait for the 8 consecutive non-coincidences. In this way the new channel will be captured rapidly. Once locked on to the new channel, "auto countdown" is then reselected by the MCU. Under some conditions such as some VCRs in Search mode, it is possible to get signals having an incorrect number of lines, meaning that the countdown flag will go off because of successive non-coincidences. In these circumstances, if "auto countdown" is selected, the timebase will automatically lock to the signal in the Injection Lock mode. The fact that the
20
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
flag is effectively saying that the vertical timebase is out of lock need not be a cause for major concern, since the horizontal timebase will still be locked to the signal, and has its own flag "Horizontal out of lock". The vertical countdown and horizontal lock flags both perform an independent test for the presence of a valid signal. A logical OR function can be performed on the two flags, such that if either are present then by definition a valid signal is present. The vertical oscillator has end-stops set at two line-count decodes as given below: 50 x 625 / 740 = 42.2 Hz (min) 50 x 625 / 448 = 69.8 Hz (max) These figures assume that the horizontal timebase is running at 15,625 Hz. When the vertical timebase is in Injection Lock mode, the line counter reset is inhibited so that it ignores any sync pulses before a count of 448 is reached. This prevents any possible attempted synchronization in the middle of the picture. If the count reaches 740 lines, then there is an automatic reset which effectively sets the lower frequency limit. The choice of these limits is a compromise between a wide window for rapid signal capture and a narrow window for good noise immunity. It is also possible to run the timebase in 2.0 V mode as there are decodes for 100 Hz (2 x 50 Hz) operation with upper and lower limits in proportion. This is, of course, intended to be used in conjunction with field and frame memory stores. The similar decodes which would be necessary to allow 120 Hz (2 x 60 Hz) operation have not, for the present, been implemented. Finally, the timebase can be forced into a count of either 625 or 525 by commands from the MCU; in this mode the input signal, if present, is ignored completely. If there is no signal present save for noise, then this feature can be used to obtain a stable raster. In the analog section, an adjustable current source is used to charge an external capacitor at Pin 6 to generate a vertical ramp. The amplitude of the ramp is varied according to the current source (Height), and is automatically adapted when the 525 standard is recognized by multiplying by 1.2. The Linearity control is achieved by squaring the ramp and either adding or subtracting a portion of it to the main linear current. In addition, a correction current, depending on the level of anode current, is applied in the sense of oppose a change of picture height with EHT (Breathing). The final ramp with corrections added is then passed to a driver/amplifier and is output at Pin 7. The vertical ramp can be used to drive a separate vertical deflection power circuit with local feedback control. Vertical "S" Correction will then be made using fixed components within the feedback loop of the power op amp. The vertical position can be adjusted under MCU control this is achieved by varying the dc output level at Pin 7. The vertical amplitude can be reduced to 75% of its original value (bit VDI) to make possible the display of a 16:9 picture on a 4:3 screen. The reference ramp is squared to provide a pin-cushion correction parabola, developed across an external resistor at Pin 8. The parabola itself is squared, giving an independent fourth order term (Corner Correction) whose level can also be varied; this is then added as a further modifying term to the E-W output. This latter correction is used for obtaining good corner geometry with flat-square tubes. A variable dc current is added to the parabola to effect a width control. Using a suitable power amplifier and a diode-modulator in the line output stage, the parabola may be used for E-W correction and dynamic width control. A further control is provided to shift the center point of the parabola up and down the screen (Parabola Tilt). All of the vertical and horizontal signals are adjustable via 6-bit words from the MCU, and stored in latches. The adjustment controls available are: Vertical Amplitude/Linearity/Breathing Correction/Position Parabola (E-W) Amplitude/Horizontal Amplitude/ Corner Correction, and Parabola Tilt The Anode Current Sense at Pin 9 is also used as a beam current monitor. Two thresholds may be set, by the manufacturer, using external components. The first threshold sets a flag to the processor if beam current becomes excessive. The MCU could, e.g., reduce brightness and/or contrast to alleviate the condition. The second threshold sets a flag warning of an overload condition where the CRT phosphor could be damaged. If such a condition were to arise, the processor would be programmed to shut down the PSU. The vertical blanking lines may be selected by means of a bit from the MCU for either the 525 or 625 standard. The interlace may also be suppressed again under the control of the processor (bits ICI, IFI).
MOTOROLA ANALOG IC DEVICE DATA
21
MC44002 MC44007
Figure 14. Horizontal Timebase
Norm (MPU) 4.43/ 3.58 MHz Frequency Divider Fh Frequency Comparator Up/Down Counter Horizontal Sync CalKill DC Bias VCO 1.0 MHz Divide by 64 2Fh ÷ 2 or 1 x2 Frequency (MPU) Enable/Start (MPU) Phase Shifter Fh Phase Detector HGAIN1 HGAIN2 D A Iref Coincidence Detector
Horizontal Out of Lock (MPU)
15 12 Drive Out 13 Flyback In Phase Detector Offset HPhase (MPU) Flyback Detector Flyback (MPU)Present
14
Figure 15. Vertical Timebase
2Fh Clock Line Counter Vertical Amplitude (MCU) DAC 16Fh Clock Composite Sync Horizontal Amplitude (MCU) DAC Vert Sync Separator Decoder 448 525 576 625 740 Reset Vertical Linearity (MCU) DAC Vertical Breathing Correction (MCU) DAC Vertical Position (MCU) DAC
Coincidence Counter and Control
Vert Modes (MCU) V Countdown Engaged (MCU)
<576 Lines (MCU)
x1.2 x0.75 VDI (MCU)
Overload and Excess Average Beam Current (MCU)
X2 X4 DAC DAC Corner Correction (MCU) DAC Parabola Tilt (MCU) Parabola Amplitude (MCU)
8 EW Drive
6 Vertical Ramp
7 Vertical Drive
9 Anode Current Sense
22
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
Figure 16. Auto Gray Scale Control Loops
EPBC Reset (MCU) Excess Peak Beam Current (MCU) Cathode Current Feedback 20 DAC1 2.5 V To MPU R G2 Up G2 Down Request Request Buffer R DC G DC B DC G2 Up/Down Request Selector x10 Amplifier Latch 1 R Intensity (MCU) G Intensity (MCU) B Intensity (MCU)
Latch
DAC2
Latch 2
DAC3
Latch 3
Vref1 Comp1 Comp2
Vref2
Up Offset Compensation Up/Down Counter Down Clock Debounce Vertical Clock
DAC4 Rout 17 Output R DC DAC G GAIN DAC Output G Signal Bout 19 Output B Signal B DC DAC G DC DAC B GAIN DAC
Latch 4
Vertical RED Line
R GAIN DAC
Latch 5 Latch 6 Load/Backload Sequencer
GREEN Line BLUE Line Timing Signals Backload Load Bright Dark
R Signal Gout 18
Latch 7 Latch 8
Latch 9 Latch 10
PIN FUNCTION AND EXTERNAL CIRCUIT REQUIREMENTS
The following section describes the purpose and function of each of the 40 pins on the MC44002/7. There is also an explanation of the external circuit component requirements for a practical application; a diagram of the small signal circuit will be found in Figure 17. One of the primary design aims for the MC44002/7 was to use the minimum number of external components, and where these are necessary, to employ low cost and easily obtainable standard types. Thus for example, as all the video signal filtering is carried out on the IC, there are no coils required whatsoever. The most common requirement is for ac coupling capacitors which are far too big to be integrated onto the chip. The time constants on certain pins are deliberately determined by external components to facilitate testing and for fine tuning the performance.
MOTOROLA ANALOG IC DEVICE DATA
23
MC44002 MC44007
PIN FUNCTION DESCRIPTION
Pin 1 Equivalent Internal Circuit VCC Description ACC External Filter used by ACC section. A single capacitor, that does not have a critical value, typically 0.01 µF, filters the feedback loop of the chroma automatic gain control amplifier.
0.1
Gnd 2 40 1.0 k 100 nF 20 k Video Input 1 (Pin 40) and 2 (Pin 2) Video inputs (Pin 2 = Video 2; Pin 40 = Video1); Intended for a nominal 1.0 Vpp input level of composite video. Separate luma and chroma components may also be used with these input pins for SVHS. The external circuit requirement is for a coupling capacitor of 0.01 µF and a series resistance not exceeding 1.0 k. The input selection and adaptation for Y and C is carried out in software.
14 k 20 k
Gnd 3 V Supply Set Iref 0.01 2.2 µF Gnd 4 To MCU 70 k Gnd 5 180 k To MCU 70 k Gnd 6 VCC Vertical Ramp A current is used to charge an external capacitor connected to this pin, developing a voltage sawtooth with a field period. The capacitor value determines the ramp amplitude. 82 nF is the more convenient value for symmetrical, linearity and parabola tilt adjustments. I2C Clock I2C bus clock input. This input can be taken straight into the IC, but in a real TV application it may be prudent to fit a series current limiting resistor near the pin in case of flashover. A single pullup resistor to 5.0 V is required. Although its value is associated with the µP, taking into account system capacitance at high data rates, a value of 4.7 k, giving optimal performance, is recommended. I2C Data I2C data input. Comments above for Pin 4 also apply to this pin. 20 k 8.0 k VCC Reference Current Master reference current used throughout the IC. This is programmed by means of an external pullup resistor, as onboard resistors are not sufficiently accurate. The designated current is 70 µA. This pin should be very well decoupled to ground to avoid picking up interference from the nearby I2C bus inputs. Nominal voltage at the pin is 1.3 V.
150 k
0.082 µF
Gnd
24
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
PIN FUNCTION DESCRIPTION (continued)
Pin 7 Equivalent Internal Circuit VCC To Vertical Deflection Amplifier Description Vertical Drive The sawtooth derived on Pin 6 is used to drive an external power amplifier v