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1 This document and the data disclosed herein or herewith is not to be reproduced, used, or disclosed in whole or in part to anyone without the written permission of THAT Corporation.

2

3

4

5 Rev
A

6 Description
PRODUCTION RELEASE PER ECO 5344

Date
6-28-02

Approved

D

D

UNLESS OTHERWISE NOTED: 1.0 All resistor values are expressed in Ohms. 1.1 All resistors are 1/4 Watt types with their tolerance and material coded into their value. VALUE 1%, Metal Film 5%, Carbon Film 0 Ohm to 0.99 Ohms 0R to 0R976 0R to 0R91 1 Ohm to 99 Ohms 1R00 to 97R6 1R0 to 91R 100 Ohms to 999 Ohms 100R0 to 976R0 100R to 910R 1k Ohm to 9k9 Ohms 1k00 to 9k76 1k0 to 9k1 10k Ohms to 99k Ohms 10k0 to 97k6 10k to 91k 100k Ohms to 999k Ohms 100k0 to 976k0 100k to 910k 1M Ohm to 99M Ohms 1M00 to 97M6 1M0 to 91M 2. All resistor networks are 2%, 1/8 Watt types with their values expressed in Ohms. 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8
B 305-0200 305-0200.SCH

C

C 305-0300 305-0300.SCH

All capacitor values are expressed in Farads All 100n bypass capacitors are 20%, 50 Volt, Z5U, Ceramic Monolythic types. All non-electrolytic capacitors are 10%, 50 Volt, X7R, Ceramic Monolythic types. All NPO capacitors are 5%, 50 Volt, Ceramic Monolythic types. All MY capacitors are 5%, 50 Volt, Metalized Polyester types. All PP capacitors are 5%, 50 Volt, Metalized Polypropylene types. All PC capacitors are 5%, 50 Volt, Metalized Polycarbonate types. All electrolytic capacitors are 20%, 16 Volt (or higher), Aluminum Electrolyte types. All TA capacitors are 20%, 16 Volt (or higher), Tantalum Electrolyte types.

305-0400

305-0400.SCH

305-0500

305-0500.SCH

4. For complete information on any component please see the associated bill of materials. 5. All net names preceded by a / are active low signals.

B

A Checked: Proj. Eng.: Chf. Eng.: Production: 1 2 3 4 Date: Date: Date: Date: 5

THAT Corporation
Title:

45 Sumner Street Milford, MA 508-478-9200

A

QSC Digital Cinema Monitor
DCM Front Panel & Power Amp (For 1, 2 & 3)

Size:

B

Drawing Number:

Revision: PC-000092-00 A

Date: 28-Jun-2002 Drawn by: A. ARANDA Sheet 1 of 5 File: F:\DM\SH\SH000092\DEV_WORK\SH0092rA.DDB - Documents\SH0092rA.P 6

1 This document and the data disclosed herein or herewith is not to be reproduced, used, or disclosed in whole or in part to anyone without the written permission of THAT Corporation.

2

3

4

5 Rev Description

6 Date Approved

VCC

VCC 1

D

RN1B RN1A RN1D RN1C RN1F RN1E RN1H RN1I 10k 10k 10k 10k 10k 10k 10k 10k

From LED Logic SERLED
RN2A 470R 14 15 1 2 3 4 5 6 7 11 12 13 10 SDI D0 D1 D2 D3 D4 D5 D6 D7 SCLK RCLK LOAD OE 74HC589B 5 SDO 9 8 U1A

RN1G 10k

D

1

1

1

1

1

1

1

1

From Rear Panel
VCC

MODE SW1 SPST NO LEFT SW2 SPST NO CENT SW3 SPST NO RITE SW4 C SW5 SPST NO SURL SPST NO SURR SW6 SPST NO SUBW SW7 SPST NO DIAG SW8 SPST NO

10

3

2

5

4

7

6

9

2

1

470R 4 RN2B 470R 4 RN3B 470R 6 RN2C 470R 6 RN3C 470R 8 RN2D 470R 8 RN3D 470R 7 7 5 3 3

SCK FP SSKEYA SSKEYB

8

/CLIP

1 3 5 7 9

VCC U1B 74HC589B GND

16

2

RN3A

1

SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7

VCC D33 RED C901 100n R1 470R C7 10u 2 4 6 8 10

SSLED SSKEYB

P1 HDR 5X2 SSKEYA MISO FP SCK FP MOSI FP

C

VCC

From Rear Panel

Bypass Mode Switch Normal
R3 4k7

To Compressor

MONOUT MONMUTE 2 4 6 8 10

STDBY STDBYC

4 5 SW11 6 DPDT-S

1 2 3

VCC B 1 1 1 1 1 1 1 1

VCC

P2 HDR 5X2 1 3 5 7 9

V+

Bypass
/BYPASS

B

RN10B RN10A RN10C RN10D RN10E RN10F RN10G RN10H 10k 10k 10k 10k 10k 10k 10k 10k LCNT SW9 SPST NO RCNT SW10 SPST NO R38 470R R39 470R SW9 SW10 SW11 SW12 SW13 SW14 SW15 SCK FP A SSKEYA SSKEYB 14 15 1 2 3 4 5 6 7 11 12 13 10 SW8 U7A SDI D0 D1 D2 D3 D4 D5 D6 D7 SCLK RCLK LOAD OE 74HC589B SDO 9

1

RN10I 10k

PH1 LINK

PH1 used only in DCM-1

V-

10

3

2

4

5

6

7

8

9

MISO FP VCC 16 VCC U7B 74HC589B GND 8

C15 100n

THAT Corporation
Checked: Proj. Eng.: Chf. Eng.: Production: Date: Date: Date: Date: 5 Size: Title:

45 Sumner Street Milford, MA 508-478-9200

A

Parts in dashed area are used only in the DCM-2 & 3

DCM FRONT PANEL
I/O Interface & Button Logic

B

Drawing Number:

Revision: PC-000092-00 A

Date: 28-Jun-2002 Drawn by: A. ARANDA Sheet 2 of 5 File: F:\DM\SH\SH000092\DEV_WORK\SH0092rA.DDB - Documents\305-0200.SC 6

1

2

3

4

1

2

3

4

5

6

This document and the data disclosed herein or herewith is not to be reproduced, used, or disclosed in whole or in part to anyone without the written permission of THAT Corporation. U2A
14 SDI SDO Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 9 15 1 2 3 4 5 6 7 7 6 3 2 7 5 1 3

Rev

Description

Date

Approved

MOSI FP

D VCC

D VCC 16 VCC 16 VCC 16

SCK FP SSLED

11 12 10 13

SCLK RCLK CLR OE 8

RN4D 470R

RN4C 470R

RN4B 470R

RN4A 470R

RN5D 470R

RN5C 470R

RN5A 470R

RN5B 470R

VCC U2B 74HC595B GND
8

C903 100n

VCC U3B 74HC595B GND
8

C904 100n

VCC U4B 74HC595B GND
8

C905 100n

5

4

1

8

6

2

D19 GRN

D18 RED

D17 YEL

D14 YEL

D4 GRN

D3 GRN

D2 GRN

4

74HC595B

D1 GRN

POWER
U3A
14 C SDI SDO Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 9 15 1 2 3 4 5 6 7 8

FAULT

AMP L2

AMP MODE

PROC MODE

PROC L

PROC C

PROC R

PH2 used only in DCM-1
PH2 LINK SERLED

To Button Logic
C

VCC 11 12 10 13

8

6

6

4

4

2

2

SCLK RCLK CLR OE 7

RN7D 470R

RN6D 470R

RN7C 470R

RN6C 470R

RN7B 470R

RN6B 470R

RN7A 470R

RN6A 470R

U8A
14 SDI SDO Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 9 15 1 2 3 4 5 6 7 8 6 4 2 5 3 2

7

5

5

3

3

1

D5 GRN

D7 GRN

D6 GRN

D13 YEL

D12 YEL

D11 YEL

D10 YEL

1

74HC595B

D9 YEL

VCC

PROC SL
U4A
14 B SDI SDO Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 9 15 1 2 3 4 5 6 7 7

PROC SR

PROC SUB

AMP L1

AMP C1

AMP R1

AMP SL1

AMP SR1

SCK FP SSLED

11 12 10 13

SCLK RCLK CLR OE 7

RN12D 470R

RN12C 470R

RN12B 470R

RN12A 470R

RN11C 470R

RN11B 470R

RN11A 470R

8

RN11D 470R

5

3

1

6

4

1

VCC 16

D28 YEL

D27 YEL

D26 YEL

D25 YEL

D30 GRN

D31 GRN

D32 YEL

7

74HC595B

B

D29 YEL

VCC 11 12 10 13

AMP C2
C17 100n

AMP R2

AMP LC2

AMP RC2

PROC LC

PROC RC

AMP LC1

AMP RC1

SCLK RCLK CLR OE 8

RN9D 470R

RN8D 470R

RN9C 470R

RN8C 470R

RN9B 470R

RN8B 470R

RN9A 470R

RN8A 470R

VCC U8B 74HC595B GND
8

8

6

6

4

4

2

2

7

5

5

3

3

1

D24 YEL

D23 YEL

D22 YEL

D21 YEL

D20 YEL

D8 YEL

D16 YEL

1

74HC595B

Parts in dashed area are used only in the DCM-2 & 3

D15 YEL

AMP SL2
A

AMP SR2

AMP SL3

AMP SR3

AMP SUB1

AMP SUB2

AMP SUB3

AMP SUB4

THAT Corporation
Checked: Proj. Eng.: Chf. Eng.: Production:
1 2 3 4

45 Sumner Street Milford, MA 508-478-9200

A

Date: Date: Date: Date:
5

Title:

DCM FRONT PANEL
LED Driver Logic

Size:

B

Drawing Number:

Revision: PC000092-00 A

Date: 28-Jun-2002 Drawn by: A. ARANDA Sheet 3 of 5 File: F:\DM\SH\SH000092\DEV_WORK\SH0092rA.DDB - Documents\305-0300.SC
6

1 This document and the data disclosed herein or herewith is not to be reproduced, used, or disclosed in whole or in part to anyone without the written permission of THAT Corporation.

2

3

4

5 Rev Description

6 Date Approved

V+ D D34 1N4148 VR2 50k TRIM V+ V+ D

R20 51R C24 100p NPO C29 100p NPO R21 51R

J1 TP

Optional Symmetry Trim Front Panel Test points
V-

D35 1N4148 V-

R6 330k

C11 100n

C28 10u

J2 TP

R5 51R IN3 15 14

C8 100p NPO

R11 3k3 C22 100n MY C19 100n MY 6 8 R18 100k OA2

BUFFOUT

VCAIN C23 560p

R8 20k R19 33k

17

IN EC-

V- V+

C26 10u

GND SYM

C

EC+

13

R7 20k 12

Low Frequency Peak

+7 dBV Max Output

11

C

OUT OA3 U5A 4301P

CMPOUT

9 16

MONOUT

U5C 4301P

Maximum Input level +10 dBV

-50 dB

VR1 10k POT

0 dB

High Frequency Boost

10 C10 100n V-

7

V-

Monitor Volume Control

R26 2k4 VOL R13 330k IN1 C9 100n Z5U R10 R2 10M 4301P OUT RMS CT 4 5 RMS 19 R25 10k R9 3k6 NI1 20 OA1 U5D 4301P 10k Q1 2SC1815 18 R37 10k MONMUTE EC R29 10k R23 47K R22 100k Q2 J174 V+ R32 10k

Attenuation -20 dB

B

AMPIN

1 2 3

P5 B

HDR 3X1 R36 1k0

C25 10u

R24 10k

1 2

U5B IN IT R4 2M0

C27 10u

Compression Ratio = 1.4 : 1

C18 100n Z5U

To Power Amp -18 dBV Max Input

V-

A Checked: Proj. Eng.: Chf. Eng.: Production: 1 2 3 4 Date: Date: Date: Date: 5

THAT Corporation
Title:

45 Sumner Street Milford, MA 508-478-9200

A

DCM FRONT PANEL
Buffer / Compressor

Size:

B

Drawing Number:

Revision: PC-000092-00 A

Date: 28-Jun-2002 Drawn by: A. ARANDA Sheet 4 of 5 File: F:\DM\SH\SH000092\DEV_WORK\SH0092rA.DDB - Documents\305-0400.SC 6

1 This document and the data disclosed herein or herewith is not to be reproduced, used, or disclosed in whole or in part to anyone without the written permission of THAT Corporation.

2

3

4

5 Rev Description

6 Date Approved

D

D

VPA+

From Power Supply

P8

3 2 1

HDR 3X1

C20 100u

C21 100u

C14 100n C6 10u R35 120k

Amp Gain = 34 dB Maximum Power = 10.4 Watts at clipping Maximum Input = -18 dBV (output clips)

C

C

SVRR

BSTR

1 2

HDR 3X1

2

GND

OUT

10

SPKR+

SPKR-

8

OUT U6B TDA2005M IN4

IN6

U6A R17 TDA2005M 1k0 C2 470u 10V

R16 1R0 R15 1k0

R34 1R0

R14 1k0

C1 470u 10V B

B

R12 36R

C13 100n Z5U

C16 100n Z5U

R33 36R

PAGND

BSTR

1u

VCC

From Front Panel

P7

C4 1 2 3 PWRAMP 1 11 C12 3 9 100u

To 4 Ohm Speaker
P3 HDR 2X1

C3 100u 5 C5 1u 7

IN+

IN+

A Checked: Proj. Eng.: Chf. Eng.: Production: 1 2 3 4 Date: Date: Date: Date: 5

THAT Corporation
Title:

45 Sumner Street Milford, MA 508-478-9200

A

DCM FRONT PANEL
Power Amplifier Module

Size:

B

Drawing Number:

Revision: PC-000092-00 A

Date: 28-Jun-2002 Drawn by: A. ARANDA Sheet 5 of 5 File: F:\DM\SH\SH000092\DEV_WORK\SH0092rA.DDB - Documents\305-0500.SC 6

1 This document and the data disclosed herein or herewith is not to be reproduced, used, or disclosed in whole or in part to anyone without the written permission of THAT Corporation.

2

3

4

5 Rev
A

6 Description
PRODUCTION RELEASE PER ECO 5344

Date
6-28-02

Approved

D

D

304-0204

304-0204.SCH

304-1004

304-1004.SCH

304-0304

304-0304.SCH

304-1104

304-1104.SCH

UNLESS OTHERWISE NOTED:
304-0404 304-0404.SCH 304-1204 304-1204.SCH

C

304-0504

304-0504.SCH

304-1304

304-1304.SCH

1.0 All resistor values are expressed in Ohms. 1.1 All resistors are 1/8 Watt SMT types with their tolerance and material coded into their value. VALUE 1%, Metal Film 5%, Carbon Film 0 Ohm to 0.99 Ohms 0R to 0R976 0R to 0R91 1 Ohm to 99 Ohms 1R00 to 97R6 1R0 to 91R 100 Ohms to 999 Ohms 100R0 to 976R0 100R to 910R 1k Ohm to 9k9 Ohms 1k00 to 9k76 1k0 to 9k1 10k Ohms to 99k Ohms 10k0 to 97k6 10k to 91k 100k Ohms to 999k Ohms 100k0 to 976k0 100k to 910k 1M Ohm to 99M Ohms 1M00 to 97M6 1M0 to 91M 2. All resistor networks are 2%, 1/8 Watt types with their values expressed in Ohms. 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 All capacitor values are expressed in Farads All 100n bypass capacitors are 10%, 50 Volt, X7R, Ceramic Monolythic types. All 100p RF capacitors are 5%, 50 Volt, NP0, Ceramic Monolythic types. All NPO capacitors are 5%, 50 Volt, Ceramic Monolythic types. All MY capacitors are 5%, 50 Volt, Metalized Polyester types. All PP capacitors are 5%, 50 Volt, Metalized Polypropylene types. All PC capacitors are 5%, 50 Volt, Metalized Polycarbonate types. All electrolytic capacitors are 20%, 16 Volt (or higher), Aluminum Electrolyte types. All TA capacitors are 20%, 16 Volt (or higher), Tantalum Electrolyte types.

C

304-0604

304-0604.SCH

304-1404

304-1404.SCH

304-0704

304-0704.SCH

304-1504

304-1504.SCH

4. For complete information on any component please see the associated bill of materials. 5. All net names preceded by a / are active low signals.
B

B

6. V+ = +12 Vdc, V- = -12 Vdc, VCC = +5 Vdc

304-0804

304-0804.SCH

304-1604

304-1604.SCH

304-0904

304-0904.SCH

304-1704

304-1704.SCH

A Checked: Proj. Eng.: Chf. Eng.: Production: 1 2 3 4 Date: Date: Date: Date: 5

THAT Corporation
Title:

45 Sumner Street Milford, MA 508-478-9200

A

QSC Digital Cinema Monitor
DCM-1 Rear Panel PCB

Size:

B

Drawing Number:

Revision: PC-000093-00 A

Date: 28-Jun-2002 Drawn by: A. ARANDA Sheet 1 of 17 File: C:\AA\PC0093rA\SH0093rA.DDB - Documents\SH0093rA.PRJ 6

1 This document and the data disclosed herein or herewith is not to be reproduced, used, or disclosed in whole or in part to anyone without the written permission of THAT Corporation.

2

3

4

5 Rev Description

6 Date Approved

LEFT CHANNEL
D M2 15 14 13 12 11 J1 DB15HD 5 10 4 9 3 8 2 7 1 6 M1 C1 100p C2 100p C3 100p C4 100p

SUBS 1 & 2
C317 100p C6 100p C7 100p C8 100p C9 100p A2- OUT A2 VMON A2 IMON A1 IMON A1 VMON A2+ OUT STDa A1+ OUT A1- OUT C5 100p 15 14 13 12 11 J7 DB15HD D M2 5 10 4 9 3 8 2 7 1 6 M1 C209 100p C210 100p C211 100p C212 100p C320 100p C214 100p C215 100p C216 100p C217 100p D2 VMON D2 IMON D1 IMON D1 VMON STDd SW+ OUT SW- OUT

C213 100p

C

C

CENTER CHANNEL

SUBS 3 & 4

M2 15 14 13 12 11 J2 DB15HD 5 10 4 9 3 8 2 7 1 6 M1

C318 100p

C15 100p

C16 100p

C17 100p

C18 100p B2- OUT B2 VMON B2 IMON B1 IMON B1 VMON B2+ OUT STDb B1+ OUT B1- OUT

M2 15 14 13 12 11 J8 DB15HD 5 10 4 9 3 8 2 7 1 6 M1

C321 100p

C96 100p

C119 100p

C136 100p

C139 100p E2 VMON E2 IMON E1 IMON E1 VMON STDe

C10 100p

C11 100p

C12 100p

C13 100p

C14 100p

C28 100p

C39 100p

C91 100p

C92 100p

C95 100p B

B

RIGHT CHANNEL
P1

M2 15 14 13 12 11 A J3 DB15HD 5 10 4 9 3 8 2 7 1 6 M1

C319 100p

C24 100p

C25 100p

C26 100p

C27 100p C2- OUT C2 VMON C2 IMON C1 IMON C1 VMON C2+ OUT STDc C1+ OUT C1- OUT

1 2 3 4 5 6 C328 100p C288 100p C285 100p C283 100p C278 100p

PSW+ PSWHOH+ HOH-

From Remote Powered Subwoofer Output Driver From Hard of Hearing Output Driver

TRM BLK

C19 100p

C20 100p

C21 100p

C22 100p

C23 100p

THAT Corporation
Checked: Proj. Eng.: Chf. Eng.: Production: Date: Date: Date: Date: 5 Size: Title:

45 Sumner Street Milford, MA 508-478-9200

A

Screen & Subwoofer Dataports, Aux Outputs

DCM-1 Rear Panel PCB
Revision: PC-000093-00 A

B

Drawing Number:

Date: 28-Jun-2002 Drawn by: A. ARANDA Sheet 3 of 17 File: C:\AA\PC0093rA\SH0093rA.DDB - Documents\304-0304.SCH 6

1

2

3

4

1 This document and the data disclosed herein or herewith is not to be reproduced, used, or disclosed in whole or in part to anyone without the written permission of THAT Corporation.

2

3

4

5 Rev Description

6 Date Approved

PROCESSOR INPUTS
D M1 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 J9 DB25S M2 C99 100p C100 100p C101 100p C102 100p C103 100p C104 100p 1 2 3 4 C88 100p C90 100p C93 100p C94 100p C98 100p C97 100p LL+ F2 VMON F2 IMON

C181 100p

C182 100p

C323 100p

C322 100p

C175 100p

M2 5 10 4 9 3 8 2 7 1 6 15 14 13 12 11 D

To Input Buffer

F1 IMON F1 VMON STDf

CC+

To Input Buffer & Passive Crossover

C183 100p

C179 100p

C178 100p

C177 100p

C176 100p

M1 J4 DB15HD

SURROUND DATAPORT 1

RR+

To Input Buffer

C

SLSL+ SRSR+ SWSW+

To Processor Monitor To Input Buffer
G2 VMON G2 IMON G1 IMON G1 VMON STDg P16 HDR 4X1 P17 HDR 4X1 1 2 3 4

C199 100p

C200 100p

C324 100p

C325 100p

C193 100p

M2 C 5 10 4 9 3 8 2 7 1 6 15 14 13 12 11

Link With Ribbon Cable

To IMON Select

C201 100p

C197 100p

C196 100p

C195 100p

C194 100p

M1 J6 DB15HD

SURROUND DATPORT 2

Mode Switch Surround
SR12 SW1A 4PDT

B PH5

C190 100p H2 VMON H2 IMON H1 IMON H1 VMON STDh

C191 100p

C326 100p

C327 100p

C184 100p

SL12 SW1B 4PDT

M2 5 10 4 9 3 8 2 7 1 6 15 14 13 12 11

B

SURROUND INSERT
M2 5 9 4 8 3 7 2 6 1 P3 DB9P2 M1

LINK PH4 LINK SR-B SB-R SL-B SB-L

SR3 SW1C 4PDT SL3 SW1D 4PDT

C192 100p

C188 100p

C187 100p

C186 100p

C185 100p

M1 J5 DB15HD

SURROUND DATAPORT 3

C180 100p

C189 100p

C198 100p

C313 100p

C314 100p

C315 100p

C316 100p

SLINSLIN+ SRINSRIN+

A Checked: Proj. Eng.: Chf. Eng.: Production: 1 2 3 4 Date: Date: Date: Date: 5

THAT Corporation
Title:

45 Sumner Street Milford, MA 508-478-9200

A

Surround Dataports & Insert, Processor Input
Size:

DCM-1 Rear Panel PCB
Revision: PC-000093-00 A

B

Drawing Number:

Date: 28-Jun-2002 Drawn by: A. ARANDA Sheet 4 of 17 File: C:\AA\PC0093rA\SH0093rA.DDB - Documents\304-0404.SCH 6

1 This document and the data disclosed herein or herewith is not to be reproduced, used, or disclosed in whole or in part to anyone without the written permission of THAT Corporation. C37 33p NPO D L7 RN5B 22k 2 6 5 6 RN5C 22k 3 4 RN5D 22k C105 33p NPO C106 CIN 33p NPO CC 2 RN6B 22k 7 2 3 C+ 3 RN6C 22k 6 5 RN6D 22k C107 33p NPO C108 RIN 33p NPO R2 RN7B 22k 7 2 3 RN7C 22k 6 5 RN7D 22k C109 33p NPO C110 8 RN7A 22k 1 8 RN6A 22k 1 U2A 4570B 4 C282 10u 1 1 RN5A 22k 7 U2B 4570B 5 C281 10u 8

2

3 VA+

4 R186 2R0 C132 1u TA C127 100n

5 Rev +5VD0 V+ C286 1u TA C128 100n 8 Description

6 Date Approved

C142 100n D C141 100n

LIN

To Processor Monitor Mix
R183 4k99 R182 20k0 2 3 VREF0 U4A 4570B R184 1 3k32 6 5 VREF0 TP12 R185 3k32 7 U4B 4570B R187 150R

From Left Processor Input

U9 3 LIN+ 17 C129 2n2 NPO 16 VA+ AINL+ VD+ MCLK LRCLK SCLK SDATA 6 R6 7 12 8 9 SD0 OVFL PU FRAME 2 11 10 75R R7 75R R196 75R

MCLK LRCK

From System clock

V+ U2C 4570B V4

From Glue
SCLK SDI0 OF0 PKUO FRAME

L+

VV+ 8

C146 100n

R188 150R 1 VREF0 R197 1k0 C284 1u TA

LIN-

AINL-

-12 dB Attenuation (4 Vrms to 1 Vrms)

To DSP
V+ U3C 4570B V4

2.2VDC

To Processor Monitor Mix
R190 4k99 R189 20k0 2 3 VREF0 R191 1 U5A 4570B 3k32 6 5 VREF0

C131 2n2 NPO

15

CMOUT

To/From Glue

C145 100n

13 R192 3k32 7 U5B 4570B R193 150R CIN+ C130 2n2 NPO 14 4

AINR+

DIF0 DIF1 HPDEF RESET DGND

20 19 1 18 5

R5 47k VV+ /RST

From Center Processor Input

From uC
8 V+ U4C 4570B V4

C144 100n

C

AINRAGND CS5360-KS

R194 150R

CINVA+ R202 +5VD1 C292 1u TA C134 100n

C143 100n

VV+ 8

To Processor Monitor Mix

2R0 C138 1u TA C133 100n

C114 100n

Right Processor Input
B R+ 3

R199 1 U3A 4570B C287 10u 4k99 R198 20k0 2 3 VREF1 U6A 4570B R200 1 3k32 6 5 VREF1

R201 3k32 7 U6B 4570B R203 150R RIN+ U10 3 17 C135 2n2 NPO 16 VA+ AINL+ VD+ MCLK LRCLK SCLK SDATA 6 7 12 8 9 SD1 OVFL PU FRAME 2 11 10 R211 75R MCLK LRCK SCLK SDI1 OF1 PKUO

V+ U5C 4570B V4

C113 B 100n

4

From System Clock From Glue To DSP To/From Glue

VV+ 8

R204 150R

RIN-

C116 100n

AINL-

TP13

2.2VDC
33p NPO SW7 RN23B 22k 2 6 5 RN23C 22k 3 4 RN23D 22k C111 33p NPO 1 RN23A 22k 7 U3B 4570B 5 SWIN 8

1 VREF1

R212 1k0 C290 1u TA C137 2n2 NPO

15

CMOUT

V+ U6C 4570B V4

R195 13 C289 2n2 NPO 14 4 AINR+ DIF0 DIF1 HPDEF RESET DGND 20 19 1 18 5 Checked: Proj. Eng.: Chf. Eng.: Production: Date: Date: Date: Date: 5 Size: 4k7

C115 100n

V/RST

From Subwoofer Processor Input
A SW+ 6

To Processor Monitor Mix

From uC

AINRAGND CS5360-KS

THAT Corporation
Title:

45 Sumner Street Milford, MA 508-478-9200

A

Input Buffers & A/D Converters

DCM-1 Rear Panel PCB
Revision: PC-000093-00 A

B

Drawing Number:

Date: 28-Jun-2002 Drawn by: A. ARANDA Sheet 5 of 17 File: C:\AA\PC0093rA\SH0093rA.DDB - Documents\304-0504.SCH 6

1

2

3

4

1 This document and the data disclosed herein or herewith is not to be reproduced, used, or disclosed in whole or in part to anyone without the written permission of THAT Corporation.

2

3

4

5 Rev Description

6 Date Approved

D VA+ +5VD2 C208 1u TA C40 100n U11 VD+ MCLK LRCLK SCLK SDATA DEM0 DEM1 MUTEL MUTER AMUTE DIF0 DIF1 DIF2 AOUTR13 DAC1R64 13k7 AOUTR+ 5 DGND AGND 14 4 DAC1+ C47 1n0 NPO C48 1n0 NPO CS4390-KS VA+ AOUTLR47 2R0 C218 1u TA 6 3 17 DAC0R60 AOUTL+ 18 DAC0+ 13k7 C54 100n R59 13k7 C43 1n0 NPO C44 1n0 NPO

+6 dB gain in low pass filter
R58 13k7 R51 3k32 2 3 C46 220p R61 13k7 220p C45 NPO 1 U13A 4570B LPF0

Output Attenuator

+12 dB (+6 dB overall) +6 dB (0 dB overall) 0 dB (-6 dB overall) -6 dB (-12 dB overall)
C55 U15C L5 L6 U15E L7 L8 NJU7313M2 L-COM2 9 ATN0 2 3 U14A 5532B 1 100p R71 10k0 1 2 U8A NJU201A 3 D21 1N4148 V14 U8B NJU201A D23 1N4148 V+ VD25 1N4148 RN12D 4 51R 11 D26 1N4148 V6 U8D NJU201A D27 1N4148 V+ V+ D24 1N4148 2 RN12B 51R 7 A1- OUT NPO V+ D22 1N4148 1 RN12A 51R 8 A1+ OUT

D

R54 2k49 R53 4k99 R28 10k0 R23 20k0

7 8

From Sys Clock From Glue From DSP
C

10 11

NJU7313M2 L-COM3 12

MCLK DAC LRCK DAC SCLK DAC SDAT0 DAC

8 7 9 10 1 2

R52 3k32

NPO

15

From Glue

/MUTE

16 15 11 20 19 12

R63 13k7 R108 3k32 6 5 C50 220p R66 13k7 7 U13B 4570B LPF1 220p C49 NPO R57 2k49 R56 4k99 R55 10k0 R120 20k0 NPO 21 20 24 23 U15D R5 R6 U15F R7 R8 NJU7313M2 R-COM2 22 ATN1 NJU7313M2 R-COM3 19 6 5 100p

C53 NPO U8C NJU201A 7 U14B 5532B 9 10

16

C

To Left Dataport

R62 10k0

5 A2+ OUT

R65 13k7 Note: In order to maintain noninverting phase throughout the DCM-1, the polarity is reversed for the L C & R lopass filter inputs. Note: all DAC low pass filter capacitors have 1% tolerances.

R109 3k32

7

B

D28 1N4148 RN12C 3 51R

6 A2- OUT

B

From Output Mute Driver
V+ 8 C42 100n V+ 8 C51 100n VM+ 13 C302 100n 5 C303 100n

OUTMUTE

8

V-

V+ U13C 4570B V4

C41 100n

V+ U14C 5532B V4

VDD GND VSS U8E NJU201A 4 VM-

C52 100n

VA

V-

THAT Corporation
Checked: Proj. Eng.: Chf. Eng.: Production: Date: Date: Date: Date: 5 Size: Title:

45 Sumner Street Milford, MA 508-478-9200

A

DCM-1 Rear Panel PCB
Left Channel D/A Converter

B

Drawing Number:

Revision: PC-000093-00 A

Date: 28-Jun-2002 Drawn by: A. ARANDA Sheet 6 of 17 File: C:\AA\PC0093rA\SH0093rA.DDB - Documents\304-0604.SCH 6

1

2

3

4

1 This document and the data disclosed herein or herewith is not to be reproduced, used, or disclosed in whole or in part to anyone without the written permission of THAT Corporation.

2

3

4

5 Rev Description

6 Date Approved

VC+ K2A DPDTFS D 8 V+ U18C 4570B VC57 100n 4 C58 100n C67 100n 3 5 10 8 K2B DPDTFS

Thru-hole for customization
R353 1k00 1/4 W R354 1k00 1/4 W VR1 C140 330n MY 1k Trim D

V+ U19C 5532B VC68 100n 4

From C+ Processor Input C-

4

8

-6 dB -26 dB

9

C247 82n MY

1k Hz Passive Crossover Network

R358 100R

VCVA+ +5VD3 C219 1u TA C56 100n R74 2R0 C220 1u TA C70 100n R75 13k7 R76 13k7 U16 VD+ MCLK LRCLK SCLK SDATA DEM0 DEM1 MUTEL MUTER AMUTE DIF0 DIF1 DIF2 AOUTR13 DAC3R80 13k7 AOUTR+ 5 DGND AGND 14 DAC3+ 4 C63 1n0 NPO C64 1n0 NPO R112 3k32 6 5 C66 220p R82 13k7 A Note: all DAC low pass filter capacitors have 1% tolerances. Checked: Proj. Eng.: Chf. Eng.: Production: 1 2 3 4 Date: Date: Date: Date: 5 Size: 220p CS4390-KS VA+ AOUTLC59 1n0 NPO C60 1n0 NPO R110 3k32 2 3 C62 220p R78 13k7 220p C61 NPO 1 U18A 4570B LPF2 R67 2k49 R68 4k99 R69 10k0 R122 20k0 NPO 2 3 4 5 U15A L1 L2 L3 L4 L-COM1 6 ATN2 2 3 NJU7313M2 100p R98 10k0 1 U19A 5532B 6 RN17C 51R 5 RN17D 51R 4 3 CLO 3 B1+ 5 NPO C71 R356 100R VR2 1k Trim

-6 dB -26 dB

C

C

6

3 DAC217 R77

4

B1+ OUT

From Sys Clock From Glue From DSP
MCLK DAC LRCK DAC SCLK DAC SDAT1 DAC 8 7 9 10 1 2 B

K3A DPDTFS B1- OUT

R111 3k32

AOUTL+

18 DAC2+

13k7

From Glue

/MUTE

16 15 11 20 19 12

R79 13k7 C65 NPO 7 U18B 4570B LPF3 R70 2k49 R72 4k99 R73 10k0 R123 20k0 NPO 29 28 27 26 U15B R1 R2 R3 R4 R-COM1 25 ATN3 6 5 NJU7313M2 100p

C69 NPO

To Center Dataport

B

R89 10k0 7 U19B 5532B 7 RN17B 51R 8 RN17A 51R 1 2 CHI 10 B2+ 8

9 K3B DPDTFS

B2+ OUT

R81 13k7

R113 3k32

B2- OUT

THAT Corporation
Title:

45 Sumner Street Milford, MA 508-478-9200

A

Center D/A Converter With Bypass Xover

DCM-1 Rear Panel PCB
Revision: PC-000093-00 A

B

Drawing Number:

Date: 28-Jun-2002 Drawn by: A. ARANDA Sheet 7 of 17 File: C:\AA\PC0093rA\SH0093rA.DDB - Documents\304-0704.SCH 6

1 This document and the data disclosed herein or herewith is not to be reproduced, used, or disclosed in whole or in part to anyone without the written permission of THAT Corporation.

2

3

4

5 Rev Description

6 Date Approved

D VA+ +5VD4 C221 1u TA C72 100n R101 2R0 C222 1u TA C86 100n R91 13k7 U20 VD+ MCLK LRCLK SCLK SDATA DEM0 DEM1 MUTEL MUTER AMUTE DIF0 DIF1 DIF2 AOUTR13 DAC5R95 13k7 AOUTR+ 5 DGND AGND 14 4 DAC5+ C79 1n0 NPO C80 1n0 NPO R117 3k32 6 5 C82 220p R97 13k7 8 220p CS4390-KS VA+ AOUTLC75 1n0 NPO DAC4R92 AOUTL+ 18 DAC4+ 13k7 C76 1n0 NPO R114 3k32 2 3 C78 220p R93 13k7 16 NPO 220p R90 13k7 C77 NPO 1 U22A 4570B LPF4 R85 2k49 R84 4k99 R83 10k0 R124 20k0 15 2 3 4 5 U24A L1 L2 L3 L4 L-COM1 6 ATN4 2 3 NJU7313M2 100p C87 NPO U12A NJU201A 1 U23A 5532B 1 2 3 D31 1N4148 V14 U12B NJU201A D30 1N4148 V+ VD33 1N4148 RN22D 4 51R 11 D35 1N4148 V6 U12D NJU201A D36 1N4148 VC304 100n 5 C305 100n Checked: Proj. Eng.: Chf. Eng.: Production: 1 2 3 4 Date: Date: Date: Date: 5 Size: V+ V+ V+

D

R125 10k0

6

3 17

D32 1N4148 RN22A 1 51R

8 C1+ OUT

From Sys Clock From Glue
C

From DSP

MCLK DAC LRCK DAC SCLK DAC SDAT2 DAC

8 7 9 10 1 2

R115 3k32

C D29 1N4148 RN22B 2 51R

7 C1- OUT

From Glue

/MUTE

16 15 11 20 19 12

R94 13k7 C81 NPO 7 U22B 4570B LPF5 R88 2k49 R87 4k99 R86 10k0 R126 20k0 NPO 7 29 28 27 26 U24B R1 R2 R3 R4 R-COM1 25 ATN5 6 5 NJU7313M2 100p C85 NPO U12C NJU201A 7 U23B 5532B 9 10

To Right Dataport

R116 10k0

5 C2+ OUT

R96 B Note: all DAC low pass filter capacitors have 1% tolerances. 13k7

R118 3k32

B D34 1N4148 RN22C 3 51R

6 C2- OUT

From Output Mute Driver
V+ 8 C74 100n V+ 8 C83 100n U12E NJU201A C84 100n VM+ 13

OUTMUTE

V+ U22C 4570B V4 A V-

C73 100n

V+ U23C 5532B V4

VDD GND VSS 4

THAT Corporation
Title:

45 Sumner Street Milford, MA 508-478-9200

A

V-

VM-

DCM-1 Rear Panel PCB
Right Channel D/A Converter

B

Drawing Number:

Revision: PC-000093-00 A

Date: 28-Jun-2002 Drawn by: A. ARANDA Sheet 8 of 17 File: C:\AA\PC0093rA\SH0093rA.DDB - Documents\304-0804.SCH 6

1 This document and the data disclosed herein or herewith is not to be reproduced, used, or disclosed in whole or in part to anyone without the written permission of THAT Corporation.

2

3

4

5 Rev Description

6 Date Approved

Frequency Control From Processor Input Buffer
SWIN R100 2k00 R102 2k00 R24 16k9 R103 2k00 R33 35k7 R32 75k0 R31 165k 21 20 24 23

20.0 Hz 22.1 Hz 24.5 Hz 29.5 Hz 40.0 Hz
U28D R5 R6 U28F R7 R8 NJU7313M2 R-COM2 NJU7313M2 R-COM3 R159 19 22 C172 470n MY R25 16k9 R26 35k7 R29 75k0 R30 165k 6 5 16k9 7 INT1 U26B LF353B 10 11 U28C L5 L6 U28E L7 L8 NJU7313M2 L-COM2 NJU7313M2 L-COM3 R160 16k9 12 9 C168 470n MY D

D

7 8

Q = 0.707
U42D 22 R-COM2 NJU7313M2 R5 R6 R38 24 23 15k0 R39 3k32

6 5

7 SWOUT U27B 5532B R104 16k9 C280 22u

2 3

1 INT2 U26A LF353B

Q = 2.000
C 21 20 U42F R7 R8 U42E L7 L8 NJU7313M2 R-COM3 19

Output Attenuator
SUBATT R17 R37 3k48 R34 6k98 2 3 4 5 U28A L1 L2 L3 L4 L-COM1 6 NJU7313M2 C167 1n0 NPO R40 4k99 2 3 NJU7313M2 U17A NJU201A 1 U27A 5532B 25 15 U17B NJU201A 14 D40 1N4148 V11 D42 1N4148 V6 D43 1N4148 VV+ V+ 1 2 3 D37 1N4148 VV+

C

+3 dB

10 11

NJU7313M2 L-COM3 12

0 dB -3 dB -6 dB

V+

4k99 R35 10k0

D38 1N4148

2

RN1B 51R

7

SW+ OUT

-9 dB -12 dB -15 dB -18 dB
B R16 20k0 R22 40k2

R36 14k0 R41 28k0

29 28 27 26

U28B R1 R2 R3 R4

To Subwoofer Dataports
D39 1N4148 RN1A 51R B

R-COM1

1

8

SW- OUT

U17C NJU201A 10 V+ 8 V+ 8 VM+ 9 C124 13 100n C306 100n 5 C307 100n VM7

16

D41 1N4148

4

RN1D 51R

5

PSW+

C238 100n

V+ U26C LF353B V4

C237 100n

V+ U27C 5532B V4

U17E NJU201A

VDD GND VSS 4

U17D NJU201A

To Powered Subwoofer Output
D44 1N4148 3 RN1C 51R 6 PSW-

C123 100n

From Output Mute Driver

OUTMUTE

VA

V-

8

THAT Corporation
Title:

45 Sumner Street Milford, MA 508-478-9200

A

Checked: Proj. Eng.: Chf. Eng.: Production: 1 2 3 4

Date: Date: Date: Date: 5

DCM-1 Rear Panel PCB
Subwoofer Processing

Size:

B

Drawing Number:

Revision: PC-000093-00 A

Date: 28-Jun-2002 Drawn by: A. ARANDA Sheet 9 of 17 File: C:\AA\PC0093rA\SH0093rA.DDB - Documents\304-0904.SCH 6

1 This document and the data disclosed herein or herewith is not to be reproduced, used, or disclosed in whole or in part to anyone without the written permission of THAT Corporation.

2

3

4

5 Rev Description

6 Date Approved

B1 VMON D B2 VMON F1 VMON

C223 C224 C225 C226 C229 C230 C231 C232

1u 1u 1u 1u 1u 1u 1u 1u

1 2 3 4 1 2 3 4

RN28A 1k RN28B 1k RN28C 1k RN28D 1k RN29A 1k RN29B 1k RN29C 1k RN29D 1k B1 MIX B2 MIX F1 MIX F2 MIX G1 MIX G2 MIX H1 MIX H2 MIX

8 7 6 5 8 7 6 5 2 3 4 5

U30A L1 L2 L3 L4 U30C L5 L6 U30E L7 L8

NJU7313M2

V+ D 6 VMON

L-COM1

To Monitor Select

R226 1k0 C299 10u

From Dataport Voltage Inputs

F2 VMON G1 VMON G2 VMON H1 VMON H2 VMON

7 8

NJU7313M2 L-COM2 9

R224 V25k5 R223 2k00 6 5 Voff R225 1M5 C298 10u U33B 4570B 7 VMONAD

4

8

10 11

NJU7313M2 L-COM3 12 R146 1M5

C297 1u

R227 28k0

1

SYM VCC VEE IN RMS OUT BIAS GND CAP 2 3 6

5

7

U36 2252

To uC

C

R228 549k

C150 100n

C

VV+

1

2

3

4

1

2

3

RN30A RN30B RN30C RN30D RN31A RN31B RN31C RN31D 100k 100k 100k 100k 100k 100k 100k 100k

4

8

7

6

5

8

7

6

1

2

3

4

1

2

3

1

RN32A RN32B RN32C RN32D RN33A RN33B RN33C RN33D 100k 100k 100k 100k 100k 100k 100k 100k A1 MIX A2 MIX C1 MIX C2 MIX D1 MIX D2 MIX E1 MIX E2 MIX 8 7 6 5 8 7 C260 C261 1u 1u 6 5 RN26A 1k RN26B 1k RN26C 1k RN26D 1k RN27A 1k RN27B 1k RN27C 1k RN27D 1k 4 3 21 20 2 1 24 23 4 3 2 1 29 28 27 26

4

5

To Amplifier Monitor Mix

0.169 VDC
TP5

R221 75k0

8

7

6

5

8

7

6

B

5

Voff

C296 1u TA

R215 1k00

B

A1 VMON A2 VMON C1 VMON C2 VMON D1 VMON

C233 C234 C256 C257 C258 C259

1u 1u 1u 1u 1u 1u

U30B R1 R2 R3 R4 U30D R5 R6 U30F R7 R8

NJU7313M2

Input (dBV)
R-COM1 25

Output (V) 0.02 20 mV steps 5.0 ...

+10.75 0.25 dB steps ...

NJU7313M2 R-COM2 22

-53.0 time constant = 35mS

D2 VMON A E1 VMON E2 VMON

NJU7313M2 R-COM3 19 Checked: Proj. Eng.: Chf. Eng.: Production: Date: Date: Date: Date: 5

THAT Corporation
Title:

45 Sumner Street Milford, MA 508-478-9200

A

DCM-1 Rear Panel PCB
Amp Voltage Monitor

Size:

B

Drawing Number:

Revision: PC-000093-00 A

Date: 28-Jun-2002 Drawn by: A. ARANDA Sheet 10 of 17 File: C:\AA\PC0093rA\SH0093rA.DDB - Documents\304-1004.SCH 6

1

2

3

4

1 This document and the data disclosed herein or herewith is not to be reproduced, used, or disclosed in whole or in part to anyone without the written permission of THAT Corporation.

2

3

4

5 Rev Description

6 Date Approved

B1 IMON D B2 IMON F1 IMON F2 IMON

C263 C264 C265 C266 C267 C268 C269 C270

1u 1u 1u 1u 1u 1u 1u 1u 1 2 3 4 1 2 3 4

1 2 3 4 1 2 3 4

RN34A 1k RN34B 1k RN34C 1k RN34D 1k RN35A 1k RN35B 1k RN35C 1k RN35D 1k

8 7 6 5 8 7 6 5 2 3 4 5

V+ U34A L1 L2 L3 L4 U34C L5 L6 U34E L7 L8 NJU7313M2 L-COM2 9 C262 NJU7313M2 L-COM3 12 R46 1M5 R219 549k 1u R218 28k0 1 R214 V25k5 R213 2k00 2 3 Voff R216 1M5 C294 10u C 1 U33A 4570B IMONAD 4 8 5 L-COM1 6 IMON NJU7313M2 R217 1k0 C295 10u D

To Monitor Select

From Dataport Current Inputs

G1 IMON G2 IMON H1 IMON H2 IMON

7 8

10 11

SYM VCC VEE IN RMS OUT BIAS GND CAP 2 3 6

7

U32 2252

To uC

C

RN38A RN38B RN38C RN38D RN39A RN39B RN39C RN39D 100k 100k 100k 100k 100k 100k 100k 100k

C148 100n

8

7

6

5

8

7

6

5

V-

4

3

2

1

4

3

2 7

RN40D RN40C RN40B RN40A RN41D RN41C RN41B RN41A 100k 100k 100k 100k 100k 100k 100k 100k C271 C272 C273 C274 C275 B D1 IMON C276 D2 IMON E1 IMON E2 IMON C277 C293 1u 1u 1u 1u 1u 1u 1u 1u

5

6

7

8

5

6

8

1

A1 IMON A2 IMON C1 IMON C2 IMON

8 7 6 5 8 7 6 5

RN36A 1k RN36B 1k RN36C 1k RN36D 1k RN37A 1k RN37B 1k RN37C 1k RN37D 1k

1 2 3 4 1 2 3 4 29 28 27 26

U34B R1 R2 R3 R4 U34D R5 R6 U34F R7 R8

NJU7313M2

V+ 8

C152 100n

R-COM1

25

V+ U33C 4570B V4

C151 100n

24 23

NJU7313M2 R-COM2 22

V-

B

21 20

NJU7313M2 R-COM3 19

SLIN+ SRIN+

1 2 3

RN11A 1k RN11B 1k RN11C 1k RN11D 1k

8 7 6 5

7 8

U24C L5 L6 U24E L7 L8

NJU7313M2 L-COM2 9

10 11

NJU7313M2 L-COM3 12

A

SWIN

4

THAT Corporation
Checked: Proj. Eng.: Chf. Eng.: Production: Date: Date: Date: Date: 5 Size: Title:

45 Sumner Street Milford, MA 508-478-9200

A

DCM-1 Rear Panel PCB
Amp Current Monitor

B

Drawing Number:

Revision: PC-000093-00 A

Date: 28-Jun-2002 Drawn by: A. ARANDA Sheet 11 of 17 File: C:\AA\PC0093rA\SH0093rA.DDB - Documents\304-1104.SCH 6

1

2

3

4

1 This document and the data disclosed herein or herewith is not to be reproduced, used, or disclosed in whole or in part to anyone without the written permission of THAT Corporation.

2

3

4

5 Rev Description

6 Date Approved

G2

R129 470R D B2 MIX 1 2 RN42A 22k RN42B 22k A2 MIX C2 MIX 3 4 RN42C 22k RN42D 22k 19 5 6 8 7 2 3 4 5 U37A L1 L2 L3 L4 L-COM1 6 R18 1M5 C329 10u 6 5 PREF 33p NPO 7 U40B 4570B NJU7313M2 C147

3

4 U41B AD8403

C202 100p R133 21k0 NPO

2

From VMON Inputs (Highs)

1

D

HIBUSS

2

RN46B 10k

7

AMPSUM

C312 10u

6 5 7 U25B 4570B

To Monitor Selector
AMPMON

V+ C334 8 V+ U25C 4570B V4 100n C335 100n

G3

R130 470R B1 MIX 8 7 RN43A 22k RN43B 22k A1 MIX C1 MIX 6 5 RN43C 22k RN43D 22k 4 3 1 29 2 28 27 26 U37B R1 R2 R3 R4 R-COM1 25 R15 1M5 C330 10u 6 5 PREF 33p NPO 7 U39B 4570B NJU7313M2 C149

18 U41C AD8403

V+

PREF

20

17

R144 75k0

+2.5 VDC
2 3 1 U25A 4570B 1 TP16

V-

C

From VMON Inputs (Lows)

V+ 8

LOBUSS 4

RN46D 10k

5

C35 100n

C

R145 20k0

C333 10u

V+ U39C 4570B V4

C36 100n

F1 MIX

1 2 3 4

RN44A 22k RN44B 22k RN44C 22k RN44D 22k R20 22k

8 7 6 5

7 8

U37C L5 L6 U37E L7 L8 U37F R7 R8

NJU7313M2 L-COM2 9 R131 470R C279 12 C331 10u 19 R14 1M5 7 33p NPO 1 U39A 4570B SRBUSS 1 RN46A 10k 8 22 G1 U41A AD8403 MISO AUX 16 13 C38 100n 9 U41E VDD SDO SDI CLK 12 14 10 15 11 MOSI AUX SCK AUX /MUTE /RST SSDPOT V-

From VMON Inputs (Surrounds)

F2 MIX G1 MIX G2 MIX H1 MIX

23

24

10 11

21

NJU7313M2 L-COM3

V+ 8

C204 100n

2 3 PREF

VCC

B H2 MIX

21 20

NJU7313M2 R-COM3

To / From Glue

V+ U40C 4570B V4

R19 22k

SHDN RS DGND CS AD8403

C205 100n

B

From uC

V-

G4

D1 MIX D2 MIX

8 7

RN45A 1k RN45B 1k

1 2

24 23

U24D R5 R6 U24F R7 R8

NJU7313M2 R-COM2 22 C332 10u

R132 470R C120 33p NPO 1 U40A 4570B

8 U41D AD8403

24 23

U37D R5 R6

NJU7313M2 R-COM2 22

6

From VMON Inputs (Subs)

E1 MIX E2 MIX A

6 5

RN45C 1k RN45D 1k

3 4

21 20

NJU7313M2 R-COM3 19 R13 1M5

R135 21k0

2 3 PREF

5

SWBUSS 3

RN46C 10k

6

THAT Corporation
Checked: Proj. Eng.: Chf. Eng.: Production: Date: Date: Date: Date: 5 Size: Title:

45 Sumner Street Milford, MA 508-478-9200

A

DCM-1 Rear Panel PCB
Amp Monitor Select & Submix

B

Drawing Number:

Revision: PC-000093-00 A

Date: 28-Jun-2002 Drawn by: A. ARANDA Sheet 12 of 17 File: C:\AA\PC0093rA\SH0093rA.DDB - Documents\304-1204.SCH 6

1

2

3

4

1 This document and the data disclosed herein or herewith is not to be reproduced, used, or disclosed in whole or in part to anyone without the written permission of THAT Corporation.

2

3

4

5 Rev Description

6 Date Approved

D

Processor Input Select
LIN CIN R42 4k99 R43 4k99 R44 4k99 SWIN SL+ SR+ R45 4k99 R48 4k99 R49 4k99 7 8 U42C L5 L6 NJU7313M2 L-COM2 9 PROCSUM 6 5 R21 1M5 2 3 4 5 U42A L1 L2 L3 L4 100p NPO R181 4k99 7 U43B 5532B PROCMON 29 28 27 AMPMON 26 L-COM1 6 C203 NJU7313M2

D

From Processor Inputs

RIN

Processor / Amp Monitor Select
U42B R1 R2 R3 R4 R-COM1 25 R121 1M5 R180 49R9 MONOUT NJU7313M2

C

To Front Panel Interface

C

From Amp Submixer

From Voltage RMS

VMON

From Current RMS

IMON

R176 4k99 R50 10k0 1 B 2 3 4 RN47A 10k RN47B 10k RN47C 10k RN47D 10k 5 HOHSUM 2 3 U43A 5532B 6 7 100p 8 C117 B NPO

Not Used

R164 3k92 1

Nominal Output Level = -14 dBV
R8 49R9 R9 49R9 HOHHOH+

V+ C122 8 100n

Center -2.1 dB Attenuation L & R -8.1 dB Attenuation

To Hearing Impaired Output

V+ U43C 5532B V4 V-

C121 100n

A Checked: Proj. Eng.: Chf. Eng.: Production: 1 2 3 4 Date: Date: Date: Date: 5

THAT Corporation
Title:

45 Sumner Street Milford, MA 508-478-9200

A

Processor Monitor Select & Hearing Impaired Mixer
Size:

DCM-1 Rear Panel PCB
Revision: PC-000093-00 A

B

Drawing Number:

Date: 28-Jun-2002 Drawn by: A. ARANDA Sheet 13 of 17 File: C:\AA\PC0093rA\SH0093rA.DDB - Documents\304-1304.SCH 6

1 This document and the data disclosed herein or herewith is not to be reproduced, used, or disclosed in whole or in part to anyone without the written permission of THAT Corporation.

2

3

4

5 Rev Description

6 Date Approved

VC+ MOSI AUX SCK AUX SSSW0 SSSW1 SSSW2 R151 470R R99 4k7 17 16 14 U15G DATA VDD CK ST VEE VSS 30 1 15 VCV+ 17 16 R152 470R 14 U24G DATA VDD CK ST VEE VSS 30 1 15 VV+ U28G 17 C 16 R153 470R 14 DATA VDD CK ST VEE VSS 30 1 15 VV+ 17 16 R154 470R 14 U30G DATA VDD CK ST VEE VSS 30 1 15 VV+ 17 B R155 470R 16 14 U34G DATA VDD CK ST VEE VSS 30 1 15 VV+ 17 16 R156 470R 14 U37G DATA VDD CK ST VEE VSS 30 1 15 VV+ 17 A R157 470R 16 14 U42G DATA VDD CK ST VEE VSS 30 1 15 V-

C34 100n C33 100n V+ D11 1N4148 VC+ 1 C291 47u TP4

From Glue
D

11.4VDC

D

NJU7313M2

From uC

SSSW3 SSSW4 SSSW5 SSSW6

C30 100n C29 100n VD12 1N4148 VCC301 47u 1 TP14

Props up Center Channel During Power Down

-11.4VDC

NJU7313M2

C32 100n C31 100n V+ D9 1N4148 VM+ 1 C310 47u TP6

+11.4VDC

C

NJU7313M2

Props Up Output Mutes During Power Down
C311 47u D10 1N4148 VVM1 TP7

C207 100n C206 100n

-11.4VDC

NJU7313M2

C228 100n C227 100n Q1 2SC4116 VM+

0V = Unmute 5.4V = Mute
TP3 B

NJU7313M2

R105 47k

1

OUTMUTE

To Output Mute Switches

C241

From Glue
100n C240 100n

/MUTE

R107 10k R106 4k7 R140 47k

NJU7313M2

C125 100n C126 Checked: 100n Proj. Eng.: Chf. Eng.: Production: Date: Date: Date: Date: 5

THAT Corporation
Title:

45 Sumner Street Milford, MA 508-478-9200

A

NJU7313M2

Analog Switch Control & Supply Prop-ups
Size:

DCM-1 Rear Panel PCB
Revision: PC-000093-00 A

B

Drawing Number:

Date: 28-Jun-2002 Drawn by: A. ARANDA Sheet 14 of 17 File: C:\AA\PC0093rA\SH0093rA.DDB - Documents\304-1404.SCH 6

1

2

3

4

1 This document and the data disclosed herein or herewith is not to be reproduced, used, or disclosed in whole or in part to anyone without the written permission of THAT Corporation.

2

3

4

5 Rev Description

6 Date Approved

VCC D3 1N4148 VMONAD R229 1k0

TP2 VCC 1 VCC

BDM Interface
P5 VCC 2 4 6 /RESET

D

BKGD

1 3 5 R234 4k7

HDR 3X2

From Level Detectors

D4 1N4148

R238 1k07 C163 100n VCC U47 VRH 43 95 85 87 88 89 90 91 92 93 94 R142 1k0 D5 1N4148 VAMON 1 PKUI PT1 105 106 107 108 109 110 111 112 97 98 99 100 101 102 103 104 75 76 77 78 81 82 83 84

L2 EMI FILTER 68HC812A4 VDD VDD VDD VDD A00/PB0 A01/PB1 A02/PB2 A03/PB3 A04/PB4 A05/PB5 A06/PB6 A07/PB7 A08/PA0 A09/PA1 A10/PA2 A11/PA3 A12/PA4 A13/PA5 A14/PA6 A15/PA7 A16/PG0 A17/PG1 A18/PG2 A19/PG3 A20/PG4 A21/PG5 D08/PC0 D09/PC1 D10/PC2 D11/PC3 D12/PC4 D13/PC5 D14/PC6 D15/PC7 D00/PD0 D01/PD1 D02/PD2 D03/PD3 D04/PD4 D05/PD5 D06/PD6 D07/PD7 CS0/PF0 CS1/PF1 CS2/PF2 CS3/PF3 CSD/PF4 CSP0/PF5 CSP1/PF6 XTAL EXTAL VSS VSS VSS VSS 79 42 14 2 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 11 12 13 16 17 18 28 29 30 31 32 33 34 35 20 21 22 23 24 25 26 27 68 69 70 71 72 73 74 47 46 80 41 15 1 CPUCLK A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A0 12 A1 11 A2 10 A3 9 A4 8 A5 7 A6 6 A7 5 A8 27 A9 26 A10 23 A11 25 A12 4 A13 28 A14 29 A15 3 A16 2 /ROM 22 /RD 24 /WR 31 C153 100n C160 100n C161 100n C162 100n D

D1 1N4148 IMONAD R220 1k0 D2 1N4148 HDR 3X1 V+ R239 49k9 R232 4k7 R240 75k0 D6 1N4148 MODB VCC 1

VDDpll VDDa VRH AN0/PAD0 AN1/PAD1 AN2/PAD2 AN3/PAD3 AN4/PAD4 AN5/PAD5 AN6/PAD6 AN7/PAD7 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 RXD0/PS0 TXD0/PS1 RXD1/PS2 TXD1/PS3 MISO/PS4 MOSI/PS5 SCK/PS6 SS/PS7 KWH0/PH0 KWH1/PH1 KWH2/PH2 KWH3/PH3 KWH4/PH4 KWH5/PH5 KWH6/PH6 KWH7/PH7 KWJ0/PJ0 KWJ1/PJ1 KWJ2/PJ2 KWJ3/PJ3 KWJ4/PJ4 KWJ5/PJ5 KWJ6/PJ6 KWJ7/PJ7 BKGD RESET XIRQ/PE0 IRQ/PE1 R/W/PE2 LSTRB/PE3 ECLK/PE4 MODA/PE5 MODB/PE6 ARST/PE7 XFC VRL VSSa VSSpll

U48A A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 CE OE WE

29C257 D0 D1 D2 D3 D4 D5 D6 D7

VCC 1 2 3

P6

TP1

C300 1u TA

13 14 15 17 18 19 20 21

D8 D9 D10 D11 D12 D13 D14 D15

VCC C MODA R233 4k7 1 3 5

P7

VCC 2 4 6

A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 A10 21 A11 23 A12 2 A13 26 A14 1 /RAM 20 /RD 22 /WR 27

U49A A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 CE OE WE

61C256 D0 D1 D2 D3 D4 D5 D6 D7

11 12 13 15 16 17 18 19

D8 D9 D10 D11 D12 D13 D14 D15

C

HDR 3X2

TP8

VCC RXD1 1 3 PT1 5 7 9

P8

V2 4 6 8 10 TXD1 MISO MOSI SCK SSAUX

+2.4VDC

RXD TXD RXD1 TXD1 MISO MOSI SCK SSAUX SSCTL SSSW6 SSCLIP SSLED SSKEY /SSKEY RTS CTS

HDR 5X2

Digital I/O Test Points
2 /RAM 4 /CS0 6 /MR 8 10

D8 D9 D10 D11 D12 D13 D14 D15 SSDSP MONMUTE BPSTAT DSPCTL0 DSPCTL1 SSDPOT /RST /CS0

/WR /RD VCC

B

/ROM /WR /RD R/W ECLK

1 3 5 7 9

P9

VCC

HDR 5X2

R231 4k7

SSSW0 3 SSSW1 4 SSSW2 5 SSSW3 6 SSSW4 7 SSSW5 8 9 SPI FP SPI AUX 10 19 40 36 37 38 39 ECLK 48 MODA 49 MODB 50 51 BKGD /RESET /XIRQ /PFO R/W 44 86 96 45

D8 1N4148 R12 1k0 D7 1N4148

15 14 13 12 11 10 9 7

U46A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C G2A G2B G1

1 2 3 4 5 6

R/W

ECLK

/BYPASS

74VHC138 B

From Front Panel Bypass Switch
VCC 16 VCC 32 VCC 28 C166 100n VCC U49B 61C256 GND 14

V+

VCC

Reset and power fail detect
C159

/RAM /ROM

R237 7 5 8 3 4k7

TP9

1

PFI R11 10k0 /MR

+1.4VDC
A

2 4 6 1

U45

ADM706

/RESET /PFO

VCC RESET PFI PFO WDI WDO MR GND

16

8

R10 75k0

VCC U46B 74VHC138 GND

C164 100n

VCC U48B 29C256 GND

C165 100n

R134 4k7

100n

Manual Reset

THAT Corporation
Checked: Proj. Eng.: Chf. Eng.: Production: Date: Date: Date: Date: 5 Size: Title:

45 Sumner Street Milford, MA 508-478-9200

A

VSSA

L1 EMI FILTER

DCM-1 Rear Panel PCB
Microcontroller & Peripherals

B

Drawing Number:

Revision: PC-000093-00 A

Date: 28-Jun-2002 Drawn by: A. ARANDA Sheet 15 of 17 File: C:\AA\PC0093rA\SH0093rA.DDB - Documents\304-1504.SCH 6

1

2

3

4

1 This document and the data disclosed herein or herewith is not to be reproduced, used, or disclosed in whole or in part to anyone without the written permission of THAT Corporation.

2

3

4

5 Rev Description

6 Date Approved

VCC

C174 100n

U50 D MOSI FP MISO FP SCK FP MOSI AUX MISO AUX SCK AUX P11 VCC 1 2 3 4 5 6 7 8 R243 10k0 R244 10k0 R260 75R R261 75R R245 470R R246 470R SPI FP SPI AUX CPUCLK /PFO SSCLIP SSCTL /RESET ISPSDI ISPSCLK ISPMODE /ISPEN C169 100p MOSI MISO SCK 9 10 11 12 13 14 15 16 19 20 21 22 23 24 25 26 8 5 29 27 40 30 7

ispLSI2032 VCC VCC 6 28 OF0 31 32 OF1 33 SCLK 34 LRCK 35 36 PKUI PKUO 37 /CLIP 38 41 42 43 DSPCK 44 1 LR DAC 2 LR DSP 3 SCK DAC 4 SCK DSP ISPSDO 18

C173 D 100n

To Front Panel Interface

From uC

To Analog Switch & Digipot Control

To/From uC

IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 IO12 IO13 IO14 IO15 SDI/IN0 Y0 RESET/Y1 SCLK/Y2 GOE0 MODE ispEN

IO16 IO17 IO18 IO19 IO20 IO21 IO22 IO23 IO24 IO25 IO26 IO27 IO28 IO29 IO30 IO31 SDO/IN1

To/From A/Ds From uC

TP11

TP10

1

To Front Panel
R252 75R R257 75R R259 75R SCLK DSP LRCK DSP

1

/STDBY /MUTE DSPCLK

To Standby Relay Driver To D/As & Output Mute Driver

To DSP

ISP Download Port
C
(Cut Pin 5)

C GND GND 17 39 R256 75R R258 SCLK DAC 75R

HDR 8X1

LRCK DAC

To D/As

From A/D

FRAME

1 C157 100n B 3 4 C155 100n 5 TXD RTS RXD CTS 11 10 12 9

U51 C1+ VCC

VCC 16 C154 100n VCC 14 Y1 12M288 R2 VCC U7G 74HCU04B GND 7 M1 1 6 2 7 3 8 4 9 5 M2 R3 150R C170 100n 1 1M5 2 3 49 U7B 74HCU04B C235 22p NPO 5 13 12 U7F 74HCU04B 11 10 U7E 74HCU04B 8 U7D 74HCU04B 6 R263 75R MCLK

To A/Ds

C1C2+

V+ V-

2 6 C156 100n

R158 75R

C158 100n

MCLK DAC

To D/As

B

R1 75R

CPUCLK

To uC

C2TD1 TD2 RD1 RD2

GND TX1 TX2 RX1 RX2

15 14 7 13 8

U7A 74HCU04B C171 22p NPO

From uC

Not Used

ADM202E C244 100p C245 100p C246 100p

XTXD XCTS XRXD XRTS C255 100p

J10 DB9S

U7C 74HCU04B

PH3 LINK

A Checked: Proj. Eng.: Chf. Eng.: Production: 1 2 3 4 Date: Date: Date: Date: 5

THAT Corporation
Title:

45 Sumner Street Milford, MA 508-478-9200

A

"Glue" Logic, RS-232 Driver & System Clock Oscillator
Size:

DCM-1 Rear Panel PCB

B

Drawing Number:

Revision: PC-000093-00 A

Date: 28-Jun-2002 Drawn by: A. ARANDA Sheet 16 of 17 File: C:\AA\PC0093rA\SH0093rA.DDB - Documents\304-1604.SCH 6

1 This document and the data disclosed herein or herewith is not to be reproduced, used, or disclosed in whole or in part to anyone without the written permission of THAT Corporation.

2

3

4

5 Rev Description

6 Date Approved

D

DSP Development Test Ports
1 3 5 P4 2 4 6

D

VCC

HDR 3X2 1 3 5 P15 2 4 6 C248 100n C249 100n C250 100n C251 100n

17 28

40 48 VCC VCC

VCC VCC

VCC VCC

HDR 3X2 SCK MISO MOSI SSDSP DSPCTL1 DSPCTL0 SDI0 SDI1 LRCK DSP SCLK DSP SDAT0 DAC SDAT1 DAC SDAT2 DAC DSPCLK /RST VCC 26 35 41 42 43 57 56 55 51 47 46 45 50 49 27 36 37 38 39 C253 22n X7R 1 DSI 3 DSO 5 DSCK 7 /DR 9 R362 10k R363 10k 33 32 30 31 59 58 60 61

VCC VCC

53 70

6 9

From uC
C

SCK/SCL MISO/SDA MOSI/HA0 SS/HA2 HREQ SDI0 SDI1 WSR SCKR

From A/D From Glue

To D/As From uC

GND

C254 100n B 2 4 6 8 10 P10

R361 10k

MA0 MA1 MA2 MA3 SDO0 MA4 SDO1 MA5 U21 SDO2 MA6 DSP56004FJ66 WST MA7 SCKT MA8 MA9 MA10 EXTAL MA11 RESET MA12 MODA/IRQA MA13 MODB/IRQB MA14 MODC/NMI MA15/MCS3 MA16/MCS2/MCAS PVCC MA17/MCS1/MRAS PCAP MCS0 PINIT MRD PGND MWR DSI/OS0 DSO DSCK/OS1 DR GND GND GND GND GND GND GPIO0 GPIO1 GPIO2 GPIO3 GND GND GND GND GND GND

25 24 23 22 20 19 18 16 14 13 12 11 7 5 4 3 80 79 2 77 78

A0 DSP A1 DSP A2 DSP A3 DSP A4 DSP A5 DSP A6 DSP A7 DSP A8 DSP A9 DSP A10 DSP A11 DSP A12 DSP A13 DSP A14 DSP A15 DSP A16 DSP /CS DSP /RD DSP /WR DSP

A14 DSP 12 A13 DSP 11 A12 DSP 10 A11 DSP 9 A10 DSP 8 A8 DSP 7 A6 DSP 6 A4 DSP 5 A3 DSP 27 A5 DSP 26 A9 DSP 23 A7 DSP 25 A2 DSP 4 A1 DSP 28 A0 DSP 3 A15 DSP 31 A16 DSP 2 22 24 29

U55 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 CE OE WE VCC

32

MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7

71 69 68 67 65 64 63 62

D0 DSP D1 DSP D2 DSP D3 DSP D4 DSP D5 DSP D6 DSP D7 DSP

VCC

C252 100n 628128 D0 D1 D2 D3 D4 D5 D6 D7

C

13 14 15 17 18 19 20 21

D0 DSP D1 DSP D2 DSP D3 DSP D4 DSP D5 DSP D6 DSP D7 DSP

Delay SRAM Also optioned for 61C256

VCC CE2 30 B

OnCE Port

76 DSPCTL0 75 74 73 DSPTST 1

HDR 5X2

TP15 1 8 10 15 21 29 34 44 52 54 66 72

16

From uC

A Checked: Proj. Eng.: Chf. Eng.: Production: 1 2 3 4 Date: Date: Date: Date: 5

THAT Corporation
Title:

45 Sumner Street Milford, MA 508-478-9200

A

DCM-1 Rear Panel PCB
Digital Signal Processor

Size:

B

Drawing Number:

Revision: PC-000093-00 A

Date: 28-Jun-2002 Drawn by: A. ARANDA Sheet 17 of 17 File: C:\AA\PC0093rA\SH0093rA.DDB - Documents\304-1704.SCH 6