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COMPAL CONFIDENTIAL
1
MODEL NAME : IBQ00 PCB NO : LA-3301P (DA80000771L) BOM P/N : 45144631L01
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2
M08 (UMA) Briscoe
uFCPGA Mobile Merom Intel Crestline + ICH8M
2
2007-03-07
REV : 1.0 (A00)
3 3
DAZ P/N:DAZZGX0010L
MB PCB Part Number DA80000771L Description PCB ZGX LA-3301P REV1 M/B UMA
BOM NO. 45144631L01 PCB P/N: DA80000771L
PCB1
IBQ 00 LS-3301P REV1 LED/B
LS-3301P REV1 LED/B PCB1
IBQ 00 LS-3302P REV1 IO/B
LS-3302P I/O Board
4 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title
Cover Sheet
Size Date: Document Number
LA-3301P
Wednesday, March 07, 2007
E
Rev 1.0 Sheet 1 of 58
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Block Diagram Compal confidential Model : IBQ00
FAN
1
Thermal
GUARDIAN III EMC4001
+3.3V_SUS page 18
+FAN1_VOUT page 18
+1.05V_VCCP +VCC_CORE H_A#(3..35)
Pentium-M Merom -4MB (Socket P) uFCPGA CPU
478pin
page 7,8,9 H_D#(0..63)
CPU ITP Port
+1.05V_VCCP page 7
Clock Generator CK505
+3.3V_RUN page6
1
System Bus
FSB 800 MHz
RGB
CRT CONN
+5V_RUN page 20
RGB
+1.25V_RUN
LVDS CONN
on M/B Board page 19
LVDS DVO
INTEL Crestline 1299pin BGA
Memory BUS (DDR2) +1.8V_SUS
DDRII-DIMM X2
533 / 667MHz +0.9V_DDR_VTT +1.8V_SUS
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8
page 16,17
+1.5V_RUN +1.8V_SUS +1.05V_VCCP +3.3V_RUN +1.8V_RUN page 10,11,12,13,14,15
DVI TV
DVI Bridge SI1362A page
51
USB[4]
+5V_RUN
Smart Card OZ77CR6
page 31
SLOT
USB2 : Rear Left as viewed from the back, USB3 Rear Right as viewed from the back
2
2
PCI BUS
PCI_PIRQA# REQ#0 GNT#0
+3VRUN 33MHz
DMI
+1.5V_RUN 100MHz 48MHz +1.25V_RUN +RTC_CELL +3.3V_RUN +3.3V_SUS +1.5V_RUN +1.05V_VCCP
USB[2,3]
REAR
USB Ports X2
+5V_SUS page 32
IDSEL:AD17 (PIRQD#,GNT#1,REQ#1)
DOCKING PORT
page 36 DOCK LPC BUS
DOCKING BUFFER
+5V_RUN page 35
CardBus OZ711 LQFP
+3.3V_RUN page 30
USB[0,1]
SIDE
USB Ports X2
+5V_SUS IO/Board
IEEE1394
page 30
USB[8]
USB[6]
INTEL ICH8-M 676pin BGA
page 21,22,23,24 SATA
USB0 : side pair top, USB1 : side pair bottom
Azalia I/F PATA
PCI Express BUS Mini Card2 WLAN
3
(+1.5V_RUN 100MHz) +3VRUN 33MHz
SPI LPC BUS
+3.3V_WLAN +1.5V_RUN page 34
Mini Card 1 WWAN
USB[9]
GIGA Enthernet BCM5755M
+3.3V_LAN +2.5V_LAN +1.2V_LAN page 28,29 DOCK LPC BUS
SC_USB
M DC
+3.3V_SUS page 33 Cable
3
+3.3V_RUN +1.5V_RUN page 34
SMSC SIO ECE5028
+3.3V_ALW page 38
S-HDD
+5V_HDD page 25
D Moudle
+5V_MOD page 25
Azalia Codec STAC9205
+3.3V_RUN +VDDA page 26
RJ45 1.8V / 0.9V/1.25V
page 46
RJ11
IO/B
IO/B
PWR Sequence
page 42
+3.3V_SUS page 37
COM
SPI
MEC5025
ECE1077
+3.3V_ALW page 37 +RTC_CELL +3.3V_ALW page 39
ME & LED
page 43
1.5V / 1.05V
page 47
AMP & INT. Speaker
+5V_RUN page 27 +3.3V_SUS page 39
INT MIC
+VDDA page 27
HeadPhone & MIC Jack +3.3V_RUN
page 27
DC IN
page 44
4
Vccore
page 48
Int.KBD & Stick page Bluetooth
+3.3V_RUN page 40
ST M25P16
40
4
Battery IN
page 44
Charger
page 49
Stick
Touch Pad
+5V_RUN page 40
Biometric
+3.3V_RUN page 40
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
3V / 5V /15V
page 45
A
Battery Select
page 50
B
USB[7]
USB[5]
Trough Cable
Size Date:
C D
Block Diagram
Document Number
LA-3301P
Wednesday, February 14, 2007
E
Rev 1.0 Sheet 2 of 58
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2
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POWER STATES
Signal State S0 (Full ON) / M0 S3 (Suspend to RAM) / M1 S4 (Suspend to DISK) / M1 S5 (SOFT OFF) / M1 S3 (Suspend to RAM) / M-OFF S4 (Suspend to DISK) / M-OFF S5 (SOFT OFF) / M-OFF SLP S3# SLP S4# SLP S5# S4 STATE# SLP M# ALWAYS PLANE M PLANE SUS PLANE RUN PLANE CLOCKS
USB PORT# 0
DESTINATION Side Top
D
D
HIGH LOW LOW LOW LOW LOW LOW
HIGH HIGH HIGH HIGH HIGH LOW LOW
HIGH HIGH HIGH LOW HIGH HIGH LOW
HIGH HIGH LOW LOW HIGH LOW LOW
HIGH HIGH HIGH HIGH LOW LOW LOW
ON ON ON ON ON ON ON
ON ON ON ON OFF OFF OFF
ON ON ON ON ON OFF OFF
ON OFF OFF OFF OFF OFF OFF
ON
1
ON
Side Bottom Rear Left Rear Right Smart Card Biometric Card Bus Bluetooth Docking
C
2
ON
3
ON OFF
ICH8-M
4 5
OFF
6
OFF
7
C
PM TABLE
+15V_ALW +5V_ALW power plane +3.3V_ALW +3.3V_RTC_LDO +5V_SUS +3.3V_SUS +1.8V_SUS +5V_RUN +3.3V_RUN +2.5V_RUN +1.8V_RUN +1.5V_RUN +0.9V_DDR_VTT +VCC_CORE State +1.05V_VCCP +1.25V_RUN
8 9 1
WWAN None None None None
ECE 5028
2 3 4
S0 S3 S5 S4/AC S5 S4/AC don't exist
ON ON ON OFF
ON ON OFF OFF
ON OFF OFF OFF
B
B
PCI EXPRESS Lane 1 Lane 2
DESTINATION MINI CARD-1 WWAN MINI CARD-2 WLAN None None None GIGA LAN
A
PCI TABLE
Lane 3
PCI DEVICE OZ711
A
IDSEL AD17 AD24
REQ#/GNT# REQ#1 / GNT#1 REQ#0 / GNT#0
PIRQ PIRQD PIRQA
Lane 4 Lane 5 Lane 6
Docking
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5 4 3 2
Index and Config.
Size Date: Document Number
LA-3301P
Wednesday, February 14, 2007
1
Rev 1.0 3 of 58
Sheet
5
4
3
2
1
RUN_ON
FDS4435 (Q24)
+INV_PWR_SRC
ADAPTER
D D
+15V_ALW
ALWON
+5V_ALW +PWR_SRC BATTERY
RUNPWROK 1.05V_RUN_ON 1.5V_RUN_ON DDR_ON M_ON
RUN_ON
ISL6260 (PU11)
ISL6236 (PU22)
ISL6236 (PU21)
ISL6236 (PU20)
ALWON
SI4810DY (Q52) +3.3V_ALW
+5V_RUN
ENAB_3VLAN
CHARGER
+VCC_CORE
0.9V_DDR_VTT_ON
+1.8V_SUS
+1.25V_RUN
+1.05V_VCCP
+1.5V_RUN
C
SI3456BDV (Q69)
RUN_ON
RUN_ON
SI4810DY (Q58)
C
SUS_ON
+3.3V_LAN
REGCTL_PNP25
+3.3V_RUN
+5V_SUS
+3.3V_SUS
AUDIO_AVDD_ON
B
HDDC_EN#
SI3456BDV (Q56)
MODC_EN#
BCP69 (Q70) MAX9789A (U37) +0.9V_DDR_VTT +1.8VRUN
REGCTL_PNP12
TPS51100 (PU24)
SI3456BDV (Q54)
MMJT9435T1G (Q71)
B
SI3456 (Q48)
+5V_HDD
+5V_MOD
+VDDA
+2.5V_LAN
+1.2V_LAN
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title
Power Rail
Size Date: Document Number
LA-3301P
Wednesday, February 14, 2007
1
Rev 1.0 Sheet 4 of 58
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1
2.2K 2.2K AJ26
ICH_SMBCLK ICH_SMBDATA 32 30 C7 C8 32 30
2.2K
+3.3V_SUS
MEM_SCLK
2.2K 2N7002 2N7002
MEM_SDATA
+3.3V_RUN
197 195
ICH8-M
D
AD19
DIMMA
SMBUS Address [TBD]
197
WWAN
Intel LAN
2.2K 2.2K
195
DIMMB
SMBUS Address [TBD]
D
+3.3V_WLAN
@ 0 WLAN @ 0 CLK_SCLK CLK_SDATA
SMBUS Address [TBD]
SMBUS Address [TBD] 2N7002 2N7002
WLAN_SMBCLK WLAN_SMBDATA
SMBUS Address [TBD]
8.2K 8.2K
8 7
C
+3.3V_ALW
6
LCD_SMBCLK LCD_SMDATA
INVERTER 4.7K 4.7K
5 10
(JLVDS) Charger
SMBUS Address [TBD]
C
+3.3V_ALW
9 12 11
SMBUS Address [TBD]
100 99
THRM_SMBCLK THRM_SMBDAT
EMC4001
SMBUS Address [TBD]
2.2K 2.2K
10 SBAT_SMBCLK SBAT_SMBDAT
+3.3V_ALW
100 ohm 100 ohm
3 4
SIO
9
2'nd BATTERY
SMBUS Address [TBD]
2.2K 2.2K
111 112 PBAT_SMBCLK PBAT_SMBDAT
+3.3V_ALW
100 ohm 100 ohm
3 4
BATTERY CONN
SMBUS Address [TBD]
B
B
9 10 CHARGER
SMBUS Address [TBD]
8.2K 8.2K
6 DOCK_SMB_CLK DOCK_SMB_DAT
+5V_ALW
6 5
MEC 5025
5
DOCKING
SMBUS Address [TBD]
2.2K 2.2K
12 13 CKG_SMBDAT CKG_SMBCLK
+3.3V_RUN
17 16 CLK GEN
2N7002 2N7002
CLK_SDATA CLK_SCLK
SMBUS Address [TBD]
A
A
Compal Electronics, Inc.
Title
SMBUS TOPOLOGY
Size Date:
5 4 3 2
Document Number
LA-3301P
Wednesday, February 14, 2007
1
Rev 1.0 Sheet 5 of 58
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4
3
2
1
+3.3V_RUN +3.3V_RUN R265 2.2K_0402_5%~D 2 1 R266 2.2K_0402_5%~D 2 1 C471 0.1U_0402_16V4Z~D
Non-iAMT
+CK_VDD_MAIN +CK_VDD_MAIN C473 0.1U_0402_16V4Z~D C474 0.1U_0402_16V4Z~D C475 0.1U_0402_16V4Z~D C476 0.1U_0402_16V4Z~D C477 0.1U_0402_16V4Z~D C472 10U_0805_10V4Z~D 1 1 1 1 1 1 +3.3V_RUN
Non-iAMT
@ R435 1 2 0_0402_5%~D D 39 CKG_SMBDAT 1 S
1
1 2 L28 BLM21PG600SN1D_0805~D
2 1 2
+CK_VDD_MAIN2 L87 BLM21PG600SN1D_0805~D
2
2
2
2
2
2
MINI1CLK_REQ# MINI2CLK_REQ#
C481 0.1U_0402_16V4Z~D
D
+3.3V_RUN 2 G Q35 2N7002W-7-F_SOT323-3~D 3 S +CK_VDD_48 CLK_SCLK 1 1 2 @ R440 0_0402_5%~D 1 1 C189 0.047U_0402_16V7K~D C99 4.7U_0603_6.3V4Z~D C799 0.047U_0402_16V4Z~D +CK_VDD_REF
1
1
1
C482 0.1U_0402_16V4Z~D
C480 10U_0805_10V4Z~D
3 Q34 2N7002W-7-F_SOT323-3~D
CLK_SDATA
1 R315 1 R310 CLK_3GPLLREQ# 1 R297 SATA_CLKREQ# 1 R283 LOM_CLKREQ# 1 R301
2 10K_0402_5%~D 2 10K_0402_5%~D 2 10K_0402_5%~D 2 10K_0402_5%~D 2 10K_0402_5%~D
2 G
D
D
39 CKG_SMBCLK
1
2
2
2
2
2
2
R759 2.2_0603_5%~D U28 C479 0.047U_0402_16V4Z~D C478 4.7U_0603_6.3V4Z~D 1 2 +CK_VDD_A 1 1
FSC
CLKSEL2
FSB
CLKSEL1
FSA
CLKSEL0
CPU MHz
266 133 200 166 333 100 400 200
SRC MHz
100 100 100 100 100 100 100 100
PCI MHz
33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3
23 CLK_ICH_48M 31 CLK_SMC_48M 8,10 CPU_MCH_BSEL0 8,10 CPU_MCH_BSEL1 8,10 CPU_MCH_BSEL2 1
2 VDD_A 7 8 25 24 11 10 14 13 6 5 3 2 72 70 69 71 66 67 38 63 64 62 60 61 29 58 59 57 55 56 28 52 53 26 50 51 46 47 48 DOT96_SSC DOT96_SSC# PCIE_SATA PCIE_SATA# MCH_3GPLL MCH_3GPLL# PCIE_LOM PCIE_LOM# PCIE_ICH PCIE_ICH# PCIE_MINI2 PCIE_MINI2# H_STP_PCI# H_STP_CPU# MCH_BCLK MCH_BCLK# CPU_BCLK CPU_BCLK# CPU_ITP CPU_ITP# PCIE_MINI1 PCIE_MINI1#
2
CLK_ICH_14M 1 C775 3.3P_0402_50V8C~D @ CLK_SIO_14M 1 C776 3.3P_0402_50V8C~D @ CLK_PCI_TPM 1 C777 3.3P_0402_50V8C~D @ CLK_PCI_DOCK 1 C778 3.3P_0402_50V8C~D @ CLK_PCI_PCM 1 C779 3.3P_0402_50V8C~D @ CLK_PCI_5025 1 C780 3.3P_0402_50V8C~D @ CLK_PCI_5018 1 C781 3.3P_0402_50V8C~D @ CLK_PCI_ICH 1 C785 3.3P_0402_50V8C~D @
B C
C708 3.3P_0402_50V8C~D
C774 3.3P_0402_50V8C~D
0 0
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
CLK_ICH_48M
CLK_SMC_48M 1 49 54 65 30 36 R760 1 1 R758 R271 0_0402_5%~D 1 2 2 R273 1 R275 1 R309 R314 1 1 2 15_0402_5%~D 2 15_0402_5%~D 2.2K_0402_5%~D 2 8.2K_0402_5%~D PCI_LOM PCI_DOCK PCI_PCM PCI_SIO CLKREF DOT96 DOT96# PCI_ICH 33_0402_5%~D 2 +CK_VDD_REF 1_0603_5%~D 2 +CK_VDD_48 2.2_0603_5%~D CLK_XTAL_IN 12 18 40 20 19 41 45 FSC 23 34 33 32 27 22 43 44 37 39 PGMODE 9 VDD_SRC VDD_SRC VDD_SRC VDD_SRC VDD_PCI VDD_PCI VDD_CPU CPU_1 VDD_REF CPU_1# VDD_48 CPU_0 XTAL_IN CPU_0# CLK_XTAL_OUT FSA XTAL_OUT CPU_ITP/SRC_10 USB_48MHz/FSLA FSL_B/TEST_MODE SRC_9 REF_0/FSL_C/TEST_SEL SRC_9# PCICLK4/FCT_SEL PCICLK3 PCICLK2/TME PCICLK1 REF_1 SRC_7# DOT_96/27M DOT_96#/27M_SS PCICLK_F0/ITP_EN CLKREQ_6# CKPWRGD/PD# PGMODE CLKREQ_5# CLK_SCLK 16 SRC_4 SMBCLK SRC_4# CLKREQ_4# SMBDAT SRC_3 4 15 VSS_SRC VSS_CPU VSS_REF VSS_PCI VSS_PCI VSS_48 VSS_SRC THRM_PAD THRM_PAD THRM_PAD THRM_PAD SRC_3# CLKREQ_3# SRC_2 SRC_2# CLKREQ_2# SRC_1/SATA SRC_1#/SATA# CLKREQ_1# LCD_CLK/SRC_0 LCD_CLK#/SRC_0# SRC_5 SRC_5# CLKREQ_7# SRC_6 SRC_6# CLKREQ_9# SRC_8 SRC_8# CLKREQ_8# SRC_7 CPU_ITP#/SRC_10#
1
SLG8LP550
VSS_A PCI_STP# CPU_STP#
2 H_STP_PCI# 23
*
0 0 1
2
2
H_STP_CPU# 23 1 R267 1 R268 1 R269 1 R270 1 R272 1 R274 1 R311 1 R313 CLK_MCH_BCLK 2 33_0402_5%~D CLK_MCH_BCLK# 2 33_0402_5%~D CLK_CPU_BCLK 2 33_0402_5%~D CLK_CPU_BCLK# 2 33_0402_5%~D CLK_CPU_ITP 2 33_0402_5%~D CLK_CPU_ITP# 2 33_0402_5%~D CLK_PCIE_MINI1 2 33_0402_5%~D CLK_PCIE_MINI1# 2 33_0402_5%~D CLK_PCIE_MINI2 2 33_0402_5%~D CLK_PCIE_MINI2# 2 33_0402_5%~D CLK_PCIE_ICH 2 33_0402_5%~D CLK_PCIE_ICH# 2 33_0402_5%~D CLK_PCIE_LOM 2 33_0402_5%~D CLK_PCIE_LOM# 2 33_0402_5%~D CLK_MCH_BCLK 10 CLK_MCH_BCLK# 10 CLK_CPU_BCLK 7 CLK_CPU_BCLK# 7
C483 X1 27P_0402_50V8J~D 14.31818MHz_20P_1BX14318CC1A~D 2 1 1
2
C
1 1 1
Place crystal within 500 mils of CK410
C484 33P_0402_50V8J~D 2 1
2
2 CLK_CPU_ITP 7 CLK_CPU_ITP# 7
CLK_ICH_48M CLK_SMC_48M
Table : ICS954305AK
CLK_PCIE_MINI1 34 2 CLK_PCIE_MINI1# 34 MINI1CLK_REQ# 34
CPU_BSEL 133 166
CPU_BSEL2(FSC) CPU_BSEL1(FSB)
28 CLK_PCI_TPM 36 CLK_PCI_DOCK
CLK_PCI_TPM CLK_PCI_DOCK CLK_PCI_PCM CLK_PCI_5025 CLK_PCI_5018 CLK_ICH_14M CLK_SIO_14M MCH_DREFCLK MCH_DREFCLK#
0 0
0 1
30 CLK_PCI_PCM 39 CLK_PCI_5025 38 CLK_PCI_5018 23 CLK_ICH_14M 38 CLK_SIO_14M
+3.3V_RUN 2
10 MCH_DREFCLK 10 MCH_DREFCLK#
2 R277 2 R596 2 R280 2 R282 1 R333 1 R284 1 R285 1 R286 1 R287
1 1 33_0402_5%~D 33_0402_5%~D 1 33_0402_5%~D 1 2 15_0402_5%~D 15_0402_5%~D 2 15_0402_5%~D 2 15_0402_5%~D 2 33_0402_5%~D 2 33_0402_5%~D 1
1 R306 1 R307
CLK_PCIE_MINI2 34 CLK_PCIE_MINI2# 34 MINI2CLK_REQ# 34
2
1 R288 1 R289
CLK_PCIE_ICH 23 CLK_PCIE_ICH# 23
B
R290 10K_0402_5%~D 1 PCI_PCM
21 CLK_PCI_ICH 23 CLK_PWRGD
CLK_PCI_ICH 2 R291 CLK_PWRGD @ +3.3V_RUN
1 R299 1 R168
CLK_PCIE_LOM 28 CLK_PCIE_LOM# 28 LOM_CLKREQ# 28
2
Non-iAMT
R295 10K_0402_5%~D 1 2 @ R298 1 2 10K_0402_5%~D 34 CLK_SCLK
2
+3.3V_RUN
PGMODE 0
PIN 9 VTT_PWRGD#/PD CKPWRGD/PD# PIN 37 Pin 5/6 as SRC_10 Pin 5/6 as CPU_ITP PIN 32 Normal Operation Trusted Mode Enabled
34 CLK_SDATA
2 1 R293 1 R294 1 R419 CLK_MCH_3GPLL 2 33_0402_5%~D CLK_MCH_3GPLL# 2 33_0402_5%~D 2 475_0402_1%~D CLK_MCH_3GPLL 10 CLK_MCH_3GPLL# 10 CLK_3GPLLREQ# 10
CLK_SDATA
17
Non-iAMT
R304 10K_0402_5%~D PCI_ICH
1
1 ITP_EN 0
2
21 31 35 42
+3.3V_RUN 1
+3.3V_RUN 1
*
1 TME 0
2
PCI_LOM R319 10K_0402_5%~D
2
A
R318 10K_0402_5%~D @
@ R329 10K_0402_5%~D FSA @ R391 10K_0402_5%~D 2
68 73 74 75 76
1 R279 1 R281
CLK_PCIE_SATA 2 33_0402_5%~D CLK_PCIE_SATA# 2 33_0402_5%~D
CLK_PCIE_SATA 22 CLK_PCIE_SATA# 22 SATA_CLKREQ# 23
*
1
1 R316 1 R317
2 33_0402_5%~D 2 33_0402_5%~D
DREF_SSCLK 10 DREF_SSCLK# 10
A
1
1
FCTSEL1
PIN43 DOT96T 27M_out
PIN44 DOT96C 27M SSout
PIN47 96/100M_T SRCT0
PIN48 96/100M_C SRCC0
SLG8LP550_QFN72~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
2
0=UMA 1=Disc. GRFX down
5
*
0=UMA 1=DIS
Clock Generator
Size Date: Document Number
LA-3301P
Monday, February 26, 2007
1
Rev 1.0 Sheet 6 of 58
4
3
2
5
4
3
2
1
10
H_A#[3..35] H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1 H_A20M# H_FERR# H_IGNNE# H_STPCLK# H_INTR H_NMI H_SMI# J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 K3 H2 K2 J3 L1 Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A5 C4 D5 C6 B4 A3 M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# A20M# FERR# IGNNE# STPCLK# LINT0 LINT1 SMI# RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10] ADS# BNR# BPRI# H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 C1 F3 F4 G3 G2 G6 E4 H_ADS# H_BNR# H_BPRI# H_DEFER# H_DRD Y# H_DBSY# H_BR0# H_IERR# H_INIT# H_LOCK# H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY# H_HIT# H_HITM# H_ADS# 10 H_BNR# 10 H_BPRI# 10
JITP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
ITP_DBRESET# DEFER# DRDY# DBSY# BR0# IERR# INIT# LOCK# RESET# RS[0]# RS[1]# RS[2]# TRDY# HIT# HITM# H_DEFER# 10 H_DRDY# 10 H_DBSY# 10 H_BR0# 10 2 H_INIT# H_LOCK# H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY# 22 10 10 10 10 10 10 H_RESET# R320 1 +1.05V_VCCP 56_0402_5%~D R321 22.6_0402_1%~D 1 2 CLK_CPU_ITP CLK_CPU_ITP#
D
10 10 10 10 10 10
H_ADSTB#0 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
6 6
CLK_CPU_ITP CLK_CPU_ITP#
H_HIT# 10 H_HITM# 10 T47 T48 T49 T50 T51 T52 PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D
BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
XDP/ITP SIGNALS
EC_CPU_PROCHOT#
2
ITP_BPM#0 AD4 ITP_BPM#1 AD3 ITP_BPM#2 AD1 ITP_BPM#3 AC4 ITP_BPM#4 AC2 ITP_BPM#5 AC1 ITP_TCK AC5 ITP_TDI AA6 ITP_TDO AB3 ITP_TMS AB5 ITP_TRST# AB6 C20 ITP_DBRESET#
+1.05V_VCCP 1
GND7
VTT1 VTT0 VTAP DBR# DBA# BPM0# GND5 BPM1# GND4 BPM2# GND3 BPM3# GND2 BPM4# GND1 BPM5# RESET# FBO GND0 BCLKP BCLKN TDO NC2 TCK NC1 TRST# TMS TDI
GND6
29
JCPUA
+1.05V_VCCP
JCPUD A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
CONTROL
R323 56_0402_5%~D ITP_DBRESET# 23,38
C
THERMAL
PROCHOT# THERMDA THERMDC D21 A24 B25 C7 H_THERMDA 1 C417 2200P_0402_50V7K~D
EC_CPU_PROCHOT# 39 H_THERMDA 18 +1.05V_VCCP H_THERMDC 18 H_THERMTRIP# 18
30
ADDR GROUP 0 ADDR GROUP 1
D
@ MOLEX_52435-2891_28P~D
C
10
H_ADSTB#1 22 H_A20M# 22 H_FERR# 22 H_IGNNE# 22 22 22 22 H_STPCLK# H_INTR H_NMI H_SMI#
H_THERMTRIP#
H CLK
BCLK[0] BCLK[1] A22 A21 CLK_CPU_BCLK CLK_CPU_BCLK#
CLK_CPU_BCLK 6 CLK_CPU_BCLK# 6
H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil
1 C485
1 C486
2
2
RESERVED
Place near JITP
+3.3V_SUS R324 150_0402_5%~D ITP_DBRESET# 1 2 +1.05V_VCCP R325 51_0402_5%~D
TYCO_1-1674770-2_Merom~D
B
R326 51_0402_1%~D R327 56_0402_5%~D 1 2 H_THERMTRIP# H_RESET# R328 39_0402_1%~D ITP_TMS R330 150_0402_5%~D ITP_TDI
+1.05V_VCCP
This shall place near CPU
R331 649_0402_1%~D 1 2 R332 27_0402_1%~D ITP_TCK
A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5 4 3 2
@ 0.1U_0402_16V4Z~D ITP_TDO ITP_TRST# Title Size Date:
@ 0.1U_0402_16V4Z~D
ICH
THERMTRIP#
H_THERMDC
2
B
TYCO_1-1674770-2_Merom~D
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc. Merom Processor(1/2)
Document Number Rev 1.0 Sheet
1
LA-3301P
Monday, February 26, 2007 7 of 58
5
4
3
2
1
+VCC_CORE JCPUC A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] VCCA[1] VCCA[2] VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] VCCSENSE VSSSENSE AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 B26 C26 AD6 AF5 AE5 AF4 AE3 AF3 AE2 AF7 AE7
+VCC_CORE
D
D
10
H_D#[0..63] JCPUB H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1 E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 AD26 TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 6,10 CPU_MCH_BSEL0 6,10 CPU_MCH_BSEL1 6,10 CPU_MCH_BSEL2 C23 D25 C24 AF26 AF1 A26 D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# GTLREF TSET1 TEST2 TEST3 TEST4 TEST5 TEST6 BSEL[0] BSEL[1] BSEL[2] D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# COMP[0] COMP[1] COMP[2] COMP[3] DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 R26 U26 AA1 Y1 E5 B5 D24 D6 D7 AE6 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3 COMP0 COMP1 COMP2 COMP3 54.9_0402_1%~D 27.4_0402_1%~D 54.9_0402_1%~D 27.4_0402_1%~D H_DPRSTP# H_DPSLP# H_DPWR# H_PW RGOOD H_CPUSLP# H_PSI# H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# H_PSI# 10,22,48 22 10 22 10 48 1 1 1 1
10 10 10
H_DSTBN#0 H_DSTBP#0 H_DINV#0
DATA GRP 2
DATA GRP 0 DATA GRP 1
H_DSTBN#2 10 H_DSTBP#2 10 H_DINV#2 10
+1.05V_VCCP 220U_D2_4VY_R15M~D 1 C487 + 2
C
10 10 10
H_DSTBN#1 H_DSTBP#1 H_DINV#1 V_CPU_GTLREF
DATA GRP 3
CRB was 270uF
C
H_DSTBN#3 10 H_DSTBP#3 10 H_DINV#3 10
+1.5V_RUN
0.01U_0402_16V7K~D
10U_0805_10V4Z~D C488
MISC
VID0 VID1 VID2 VID3 VID4 VID5 VID6 VCCSENSE VSSSENSE
VID0 VID1 VID2 VID3 VID4 VID5 VID6 VCCSENSE VSSSENSE
48 48 48 48 48 48 48 48 48
1
1
C489
2
2
R337
R338
R339
R340
CPU_MCH_BSEL0 B22 CPU_MCH_BSEL1 B23 CPU_MCH_BSEL2 C21
2
2
2
2
TYCO_1-1674770-2_Merom~D
TYCO_1-1674770-2_Merom~D
B
TEST1 TEST2 TEST4 TEST6 C490 0.1U_0402_16V4Z~D @R335 1K_0402_5%~D 1 2 @ R336 1K_0402_5%~D 1 2 R394 0_0402_5%~D 1 2
PAD~D T30 PAD~D T31
TEST3 TEST5
Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP0, COMP2 trace should be 27.4 ohm. COMP1, COMP3 should be 55 ohm.
Length match within 25 mils Z0=27.4 ohm
B
Place R342 and R343 near CPU
+VCC_CORE R342 1 2 VCCSENSE 100_0402_1%~D R343 1 2 VSSSENSE 100_0402_1%~D
2
@
1
@
For the purpose of testability, route these signals through a ground referenced Z0 = 55ohm trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection.
Place C close to the CPU_TEST4 pin. Make sure CPU_TEST4 routing is reference to GND and away from other noisy signal.
FSB 533 667 800
BCLK 133 166 200
BSEL2 0 0 0
BSEL1 0 1 1
BSEL0 1
+1.05V_VCCP
Route VCCSENSE and VSSSENSE trace at 27.4 ohms, 7 mils spacing and 1 inch (max)
1
1 0
V_CPU_GTLREF 2 R341 1K_0402_1%~D
A
A
1 R344 2K_0402_1%~D 2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3 2
Title
Layout close CPU PIN AD26 55 ohm, 0.5 inch (max)
5 4
Merom Processor(2/2)
Size Date: Document Number
LA-3301P
Monday, February 26, 2007
1
Rev 1.0 Sheet 8 of 58
5
4
3
2
1
+VCC_CORE
Place these inside 1 socket cavity on L8 (North side Secondary) 2
D
1 C329 10U_0805_4VAM~D 2 C330 10U_0805_4VAM~D
1 C331 10U_0805_4VAM~D
1 C332 10U_0805_4VAM~D
1 C333 10U_0805_4VAM~D
1
1 C334 10U_0805_4VAM~D 2 C335 10U_0805_4VAM~D
1 C336 10U_0805_4VAM~D
1 C55 10U_0805_4VAM~D
1 C190 10U_0805_4VAM~D
D
2
2
2
2
2
2
2
+VCC_CORE
Place these inside 1 socket cavity on L8 (Sorth side Secondary) 2
1 C222 10U_0805_4VAM~D 2 C223 10U_0805_4VAM~D
1 C224 10U_0805_4VAM~D
1 C225 10U_0805_4VAM~D
1 C227 10U_0805_4VAM~D
1
1 C226 10U_0805_4VAM~D 2 C228 10U_0805_4VAM~D
1 C229 10U_0805_4VAM~D
1 C69 10U_0805_4VAM~D
1 C185 10U_0805_4VAM~D
2
2
2
2
2
2
2
+VCC_CORE
Place these inside 1 socket cavity on L8 (North side Primary) 2
1 C363 10U_0805_4VAM~D 2 C64 10U_0805_4VAM~D
1 C65 10U_0805_4VAM~D
1 C66 10U_0805_4VAM~D
1 C67 10U_0805_4VAM~D
1 C68 10U_0805_4VAM~D
2
2
2
2
+VCC_CORE
C
Place these inside 1 socket cavity on L8 (Sorth side Primary) 2
1 C364 10U_0805_4VAM~D 2 C50 10U_0805_4VAM~D
1 C51 10U_0805_4VAM~D
1 C52 10U_0805_4VAM~D
1 C53 10U_0805_4VAM~D
1 C54 10U_0805_4VAM~D
10uF 0805 X6S -> 85 degree C
C
2
2
2
2
High Frequence Decoupling
Near VCORE regulator.
+VCC_CORE +VCC_CORE
C177 220U_X_2VM_R7M~D
C179 220U_X_2VM_R7M~D
@ C178 220U_X_2VM_R7M~D
C366 220U_X_2VM_R7M~D
@ C338 220U_X_2VM_R7M~D
C365 220U_X_2VM_R7M~D
1 1 + 2
1 C870 0.1U_0402_10V7K~D @ C871 0.1U_0402_10V7K~D @
1 C872 0.1U_0402_10V7K~D @
1 C873 0.1U_0402_10V7K~D @
South Side Secondary
1 + 2
1 + 2
1 + 2
1 + 2
1 + 2
North Side Secondary
ESR <= 1.5m ohm Capacitor > 1980uF
2
2
2
2
BITs WI97840
B
B
+1.05V_VCCP
1 C312 0.1U_0402_10V7K~D
1 C256 0.1U_0402_10V7K~D
1 C293 0.1U_0402_10V7K~D
1 C250 0.1U_0402_10V7K~D
1 C310 0.1U_0402_10V7K~D
1 C264 0.1U_0402_10V7K~D
2
2
2
2
2
2
Place these inside socket cavity on L8 (North side Secondary)
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title
CPU Bypass
Size Date: Document Number
LA-3301P
Wednesday, February 14, 2007
1
Rev 1.0 Sheet 9 of 58
5
4
3
2
5
4
3
2
1
U29B M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB# M_ODT0 M_ODT1 M_ODT2 M_ODT3 SMRCOMP SMRCOMP# SMRCOMP_VOH SMRCOMP_VOL V_DDR_MCH_REF C491 0.1U_0402_16V4Z~D C492 0.1U_0402_16V4Z~D RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 P36 P37 R35 N35 AR12 AR13 AM12 AN13 J12 AR37 AM36 AL36 AM37 D20
16 16 17 17 16 16 17 17 16 16 17 17 16 16 17 17
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3
AV29 BB23 BA25 AV23 AW30 BA23 AW25 AW23 BE29 AY32 BD39 BG37 BG20 BK16 BG16 BE13 BH18 BJ15 BJ14 BE16 BL15 BK14 BK31 BL31 AR49 AW4
SM_CK_0 SM_CK_1 SM_CK_3 SM_CK_4 SM_CK#_0 SM_CK#_1 SM_CK#_3 SM_CK#_4 SM_CKE_0 SM_CKE_1 SM_CKE_3 SM_CKE_4 SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3 SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3 SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF_0 SM_VREF_1
D
8
H_D#[0..63] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_SWNG H_RCOMP H_SCOMP H_SCOMP# 7 8 1 R350 H_VREF H_RESET# H_CPUSLP# H_RESET# H_CPUSLP# E2 G2 G7 M6 H7 H3 G4 F3 N8 H2 M10 N12 N9 H5 P13 K9 M2 W10 Y8 V4 M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4 W3 N1 AD12 AE3 AD9 AC9 AC7 AC14 AD11 AC11 AB2 AD7 AB1 Y3 AC6 AE2 AC5 AG3 AJ9 AH8 AJ14 AE9 AE11 AH12 AJ5 AH5 AJ6 AE7 AJ7 AJ2 AE5 AJ3 AH2 AH13 B3 C2 W1 W2 B6 E5 B9 A9
U29A H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_SWING H_RCOMP H_SCOMP H_SCOMP# H_CPURST# H_CPUSLP# H_AVREF H_DVREF H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19 G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRD Y# H_HIT# H_HITM# H_LOCK# H_TRDY#
H_A#[3..35]
7
D
DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB# 16 16 17 17 M_ODT0 M_ODT1 M_ODT2 M_ODT3
MUXING
+1.8V_SUS
R345 20_0402_1%~D 1 2 1 2 R346 20_0402_1%~D
V_DDR_MCH_REF 1 1 6 MCH_DREFCLK 6 MCH_DREFCLK# 6 DREF_SSCLK 6 DREF_SSCLK# 6 CLK_MCH_3GPLL 6 CLK_MCH_3GPLL#
C
CLK
2
2
MCH_DREFCLK MCH_DREFCLK# DREF_SSCLK DREF_SSCLK# CLK_MCH_3GPLL CLK_MCH_3GPLL#
B42 C42 H48 H47 K44 K45
DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# PEG_CLK PEG_CLK#
RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 RSVD33 RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 RSVD39 RSVD40 RSVD41 RSVD42 RSVD43
H10 B51 BJ20 BK22 BF19 BH20 BK18 BJ18 BF23 BG23 BC23 BD24 BH39 AW20 BK20 C48 D47 B44 C44 A35 B37 B36 B34 C34
DDR
RSVD
C
H_ADS# 7 H_ADSTB#0 7 H_ADSTB#1 7 H_BNR# 7 H_BPRI# 7 H_BR0# 7 H_DEFER# 7 H_DBSY# 7 CLK_MCH_BCLK 6 CLK_MCH_BCLK# 6 H_DPWR# 8 H_DRDY# 7 H_HIT# 7 H_HITM# 7 H_LOCK# 7 H_TRDY# 7
HOST
23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23
DMI_MRX_ITX_N0 DMI_MRX_ITX_N1 DMI_MRX_ITX_N2 DMI_MRX_ITX_N3 DMI_MRX_ITX_P0 DMI_MRX_ITX_P1 DMI_MRX_ITX_P2 DMI_MRX_ITX_P3 DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3 DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3
DMI_MRX_ITX_N0 DMI_MRX_ITX_N1 DMI_MRX_ITX_N2 DMI_MRX_ITX_N3 DMI_MRX_ITX_P0 DMI_MRX_ITX_P1 DMI_MRX_ITX_P2 DMI_MRX_ITX_P3 DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3 DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3
AN47 AJ38 AN42 AN46 AM47 AJ39 AN41 AN45 AJ46 AJ41 AM40 AM44 AJ47 AJ42 AM39 AM43
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20 P27 N27 N24 C21 C23 F23 N23 G23 J20 C20 R24 L23 J23 E23 E20 K23 M20 M24 L32 N33 L35 CPU_MCH_BSEL0 6,8 CPU_MCH_BSEL1 6,8 CPU_MCH_BSEL2 6,8 T63 PAD~D T64 PAD~D CFG5 12 T65 PAD~D T66 PAD~D T67 PAD~D CFG9 12 T68 PAD~D T69 PAD~D T70 PAD~D T71 PAD~D T72 PAD~D T73 PAD~D CFG16 12 T74 PAD~D T75 PAD~D CFG19 12 CFG20 12
DMI
CFG5
CFG9
CFG
+1.05V_VCCP
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2
K5 L2 AD13 AE13 M7 K3 AD2 AH11 L7 K2 AC2 AJ10 M14 E13 A11 H13 B12 E12 D7 D8
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
8 8 8 8 8 8 8 8 8 8 8 8
GRAPHICS VID
R348 54.9_0402_1%~D 2
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2 7 7 7 7 7 7 7 7
CFG16 CFG19 CFG20
54.9_0402_1%~D
1
1 R347
B
PAD~D PAD~D PAD~D PAD~D
T42 T43 T44 T45
2
E35 A39 C38 B39 E36
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VR_EN
B
PAD~D T46
+1.25V_RUN 1
PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR
G41 L39 L36 J36 AW49 AV20 N20 G36
PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 ICH_PWRGD PLTRST1#_R THERMTRIP_MCH# DPRSLPVR
PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 ICH_PWRGD
23 8,22,48 16 17 23,42
PM
THERMTRIP_MCH# 18 DPRSLPVR 23,48 +3.3V_RUN R352 10K_0402_5%~D 2 1 R354 10K_0402_5%~D 2 1
ME
R349 1K_0402_1%~D 2
24.9_0402_1%~D 2
23 CL_CLK0 23 CL_DATA0 23,39 ICH_CL_PWROK 23 ICH_CL_RST0# 1
CL_CLK0 CL_DATA0 ICH_CL_PWROK ICH_CL_RST0# CL_VREF
+1.8V_SUS R351 392_0402_1~D R353 1K_0402_1%~D 2 SMRCOMP_VOH C494 0.01U_0402_16V7K~D C495 2.2U_0603_6.3V6K~D 1 1 1 1
1
LE88CLGM A0 QM20_FCBGA1299~D
AM49 AK50 AT43 AN49 AM50
CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF
C493 0.1U_0402_16V4Z~D 51 SDVO_CTRLCLK 51 SDVO_CTRLDATA 6 CLK_3GPLLREQ# 23 MCH_ICH_SYNC# SDVO_CTRLCLK SDVO_CTRLDATA CLK_3GPLLREQ# MCH_ICH_SYNC# R774 2 2 H35 K36 G39 G40 SDVO_CTRL_CLK SDVO_CTRL_DATA CLK_REQ# ICH_SYNC# TEST_1 TEST_2
2 2
Layout Note: H_RCOMP trace width and spacing is 10/20
A
R355 1K_0402_1%~D 2 2 H_VREF C496 0.1U_0402_16V4Z~D 1 H_SWNG
R356 221_0402_1%~D
0_0402_5%~D A37 1 R32 1
MISC
+1.05V_VCCP
+1.05V_VCCP
NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16
BJ51 BK51 BK50 BL50 BL49 BL3 BL2 BK1 BJ1 E1 A5 C51 B50 A50 A49 BK2
PM_EXTTS#0
PM_EXTTS#1
NC
R589 @ 0_0402_5%~D 2 1 R583 0_0402_5%~D 2 1PLTRST1#
1
1
SB_NB_PCIE_RST# 21
A
R359 3.01K_0402_1%~D 2 C497 0.1U_0402_16V4Z~D
2
2
R357 20K_0402_5%~D
LE88CLGM A0 QM20_FCBGA1299~D R358
R36 100_0402_5%~D PLTRST1#_R 1 2
PLTRST1#
21,51
1
C498 0.01U_0402_16V7K~D
C499 2.2U_0603_6.3V6K~D
1
R361 2K_0402_1%~D 2
1
1
SMRCOMP_VOL R363 1K_0402_1%~D 2 1 1
THERMTRIP_MCH# 1
2
+1.05V_VCCP
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
R362 100_0402_1%~D
56_0402_5%~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
2 2
2
2
Crestline(1 of 6)
Size Date: Document Number
LA-3301P
Monday, February 26, 2007
1
Rev 1.0 Sheet 10 of 58
5
4
3
2
5
4
3
2
1
D
D
U29D 16 DDR_A_BS0 16 DDR_A_BS1 16 DDR_A_BS2 16 DDR_A_DM[0..7] DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 16 DDR_A_DQS[0..7] DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 16 DDR_A_DQS#[0..7] DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 16 DDR_A_MA[0..14] DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_CAS# DDR_A_RAS# DDR_A_WE# BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16 BJ29 BL17 BE18 BA19 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 SA_CAS# SA_RAS# SA_WE# AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 BB19 BK19 BF29 AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6 SA_BS_0 SA_BS_1 SA_BS_2 SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 AR43 AW44 BA45 AY46 AR41 AR45 AT42 AW47 BB45 BF48 BG47 BJ45 BB47 BG50 BH49 BE45 AW43 BE44 BG42 BE40 BF44 BH45 BG40 BF40 AR40 AW40 AT39 AW36 AW41 AY41 AV38 AT38 AV13 AT13 AW11 AV11 AU15 AT11 BA13 BA11 BE10 BD10 BD8 AY9 BG10 AW9 BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8 AN10 AT9 AN9 AM9 AN11 DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
DDR_A_D[0..63] 16 17 DDR_B_BS0 17 DDR_B_BS1 17 DDR_B_BS2 17 DDR_B_DM[0..7] DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 17 DDR_B_DQS[0..7] DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 17 DDR_B_DQS#[0..7] DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 17 DDR_B_MA[0..14] DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_CAS# DDR_B_RAS# DDR_B_WE# BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13 BE24 BE17 AV16 BC17 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 SB_CAS# SB_RAS# SB_WE# AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 AY17 BG18 BG36 AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2 SB_BS_0 SB_BS_1 SB_BS_2 SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7
U29E SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 AP49 AR51 AW50 AW51 AN51 AN50 AV50 AV49 BA50 BB50 BA49 BE50 BA51 AY49 BF50 BF49 BJ50 BJ44 BJ43 BL43 BK47 BK49 BK43 BK42 BJ41 BL41 BJ37 BJ36 BK41 BJ40 BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12 BJ10 BL9 BK5 BL5 BK9 BK10 BJ8 BJ6 BF4 BH5 BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3 AY2 AY3 AU2 AT2 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
DDR_B_D[0..63] 17
C
A
B
C
MEMORY
SYSTEM
B
16 DDR_A_CAS# 16 DDR_A_RAS# 16 DDR_A_WE#
DDR
17 DDR_B_CAS# 17 DDR_B_RAS# 17 DDR_B_WE#
DDR
SYSTEM
MEMORY
B
T10
SA_RCVEN#
AY20
SA_RCVEN#
SB_RCVEN# T11
AY18
SB_RCVEN#
LE88CLGM A0 QM20_FCBGA1299~D
LE88CLGM A0 QM20_FCBGA1299~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title
Crestline(2 of 6)
Size Date: Document Number
LA-3301P
Monday, February 26, 2007
1
Rev 1.0 Sheet 11 of 58
5
4
3
2
5
4
3
2
1
U29C 19 BIA_PWM 38 PANEL_BKEN
D
Strap Pin Table
PEG_COMPI PEG_COMPO PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15 N43 M43 J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41 J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42 N45 U39 U47 N51 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44 M45 T38 T46 N50 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43 SDVOB_RED-_C SDVOB_GREEN-_C SDVOB_BLUE-_C SDVOB_CLK-_C R366 24.9_0402_1%~D PEGCOMP 1 2 +VCC_PEG
BIA_PWM PANEL_BKEN LCD_DDCCLK LCD_DDCDATA ENVDD 2 L_IBG
19 LCD_DDCCLK 19 LCD_DDCDATA 19 ENVDD 1 R369 3.3K_0402_1%~D
J40 H39 E39 E40 C37 D35 K40 L41 L43 N41 N40 D46 C45 D44 E42 G51 E51 F49 G50 E50 F48 G44 B47 B45 E44 A47 A45
L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2
CFG5 CFG9
DMI X2 Select PCI Express Graphic Lane FSB Dynamic ODT DMI Lane Reversal SDVO/PCIE Concurrent Operation
Low = DMI x 2 High = DMI x 4 (Default) Low = Reverse Lane High = Normal Operation (Default) Low=Dynamic ODT Disable High=Dynamic ODT Enable(default) Low=Normal (default) High=Lane Reversed Low=Only SDVO or PCIEx1 is operational (defaults) High=SDVO and PCIEx1 are operating simultaneously via PEG port Low=No SDVO Device Present
10 CFG5 R365 1 2 @ 4.02K_0402_1%~D
D
SDVOB_INT- 51
CFG16
R369 = 2.4k ohm value is recommended per Intel
LCD_ACLK-_C LCD_ACLK+_C LCD_BCLK-_C LCD_BCLK+_C
CFG19
LVDS
19 LCD_A019 LCD_A119 LCD_A219 LCD_A0+ 19 LCD_A1+ 19 LCD_A2+ 19 LCD_B019 LCD_B119 LCD_B219 LCD_B0+ 19 LCD_B1+ 19 LCD_B2+
CFG20
SDVOB_INT+ 51
10
CFG9
R368 1
2 @ 4.02K_0402_1%~D
GRAPHICS
10
CFG16
R372 1
2 @ 4.02K_0402_1%~D
CFG[3:17] have internal pullup
SDVO_CRTL_DATA High=SDVO Device Present (default)
C
PCI-EXPRESS
C
+3.3V_RUN
R375 2 1 150_0402_1%~D
R376 2 1 150_0402_1%~D
R377 2 1 150_0402_1%~D
36 36 36
TV_CVBS TV_Y TV_C
TV_CVBS TV_Y TV_C
E27 G27 K27 F27 J27 L27 M35 P33
TVA_DAC TVB_DAC TVC_DAC
C500 C501 C502 C503
1 1 1 1
2 2 2 2
0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D
SDVOB_RED- 51 SDVOB_GREEN- 51 SDVOB_BLUE- 51 SDVOB_CLK- 51
10 10
CFG19 CFG20
R373 1 R374 1
2 @ 4.02K_0402_1%~D 2 @ 4.02K_0402_1%~D
TV
TVA_RTN TVB_RTN TVC_RTN TV_DCONSEL_0 TV_DCONSEL_1
CFG[18:19] have internal pulldown
20,36 20,36 20,36
CRT_BLU CRT_GRN CRT_RED
H32 G32 K29 J29 F29 E29 G_CLK_DDC2 G_DAT_DDC2 CRT_HSYNC CRT_VSYNC CRT_IREF 1 1.3K_0402_1%~D K33 G35 F33 E33 C32
CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED# CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_VSYNC CRT_TVO_IREF
SDVOB_RED+_C C504 SDVOB_GREEN+_C C505 SDVOB_BLUE+_C C506 SDVOB_CLK+_C C507
1 1 1 1
2 2 2 2
0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D
SDVOB_RED+ 51 SDVOB_GREEN+ 51 SDVOB_BLUE+ 51 SDVOB_CLK+ 51
VGA
R378 1 2 150_0402_1%~D
R379 1 2 150_0402_1%~D
R380 1 2 150_0402_1%~D
B
20 CRT_HSYNC 20 CRT_VSYNC 2 R382
B
Trace CRT_IREF should be at least 20 miles away from any other toggling signal.
+3.3V_RUN LE88CLGM A0 QM20_FCBGA1299~D R686 0_0402_5%~D 1 2 1 1 @ R667 0_0402_5%~D G_CLK_DDC2 2 1 2 LCD_ACLK+ 19 +3.3V_RUN 2 G Q37 1 DAT_DDC2 D BSS138_SOT23~D
NO CONNECT FOR DISCRETE
1 R383 2.2K_0402_5%~D 2 2 1 R384 2.2K_0402_5%~D Q36 1 CLK_DDC2 BSS138_SOT23~D 2 G S D
LCD_ACLK-_C @ C39 3.3P_0402_50V8C~D LCD_A0+ @ LCD_A1+ @ LCD_A2+ @ LCD_B0+ @ LCD_B1+ @ LCD_B2+ @ LCD_DDCCLK 2 2.2K_0402_5%~D LCD_DDCDATA 2 2.2K_0402_5%~D 1 C181 1 C192 1 C193 1 C196 1 C207 1 C209 LCD_A02 3.3P_0402_50V8C~D LCD_A12 3.3P_0402_50V8C~D LCD_A22 3.3P_0402_50V8C~D LCD_B02 3.3P_0402_50V8C~D LCD_B12 3.3P_0402_50V8C~D LCD_B22 3.3P_0402_50V8C~D LCD_ACLK+_C
LCD_ACLK- 19
2
3
CLK_DDC2 20,36
R685 0_0402_5%~D R689 0_0402_5%~D 1 2 1 1 @ R687 0_0402_5%~D G_DAT_DDC2 LCD_BCLK- 19
3 S
DAT_DDC2 20,36
LCD_BCLK-_C @ C43 3.3P_0402_50V8C~D
+3.3V_RUN
A
LCD_BCLK+_C
2
R41
1
A
1 R110
Keep stub for caps as small as possible
2 1 2 LCD_BCLK+ 19
R688 0_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title
Crestline(3 of 6)
Size Date: Document Number
LA-3301P
Monday, February 26, 2007
1
Rev 1.0 Sheet 12 of 58
5
4
3
2
5
4
3
2
1
+3.3V_RUN +1.05V_VCCP C537 0.47U_0402_10V4Z~D U29H VCCSYNC VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VCC_AXD_1 VCC_AXD_2 VCC_AXD_3 VCC_AXD_4 VCC_AXD_5 VCC_AXD_6 VCCA_CRT_DAC_1 VCCA_CRT_DAC_2 J32 A33 B33 1 C532 0.1U_0402_16V4Z~D +3.3V_RUN L31 +3.3V_CRT_DAC C723 0.022U_0402_16V7K~D 1 3 22n_0805_25V C536 2 0.1U_0402_16V4Z~D 2 1 BLM18PG181SN1_0603~D 1 C541 +3.3V_RUN_DAC_BG +3.3V_RUN L29 BLM18PG181SN1_0603~D 2 1 1 C538 0.1U_0402_16V4Z~D
CRB 270uF
C535 C542 4.7U_0603_6.3V6M~D 220U_D2_4VY_R15M~D 1 + 2 1
2
D
1
1
1
2
2
2
C545 22n_0805_25V
3
+1.25V_RUN L33 2 1 BLM18AG121SN1D_0603~D C551 22U_0805_6.3V6M~D 1U_0603_10V4Z~D
AXD
AT23 AU28 AU24 AT29 AT25 AT30
VSSA_LVDS VCCA_PEG_BG VSSA_PEG_BG VCCA_PEG_PLL
B41 K50 K49 U51
+3.3V_RUN
1
C547 1000P_0402_50V7K~D
VCCA_LVDS
A41
+VCC_TX_LVDS 220U_D2_4VY_R15M~D C548
+VCC_PEG 10U_0805_4VAM~D C549
L32 BLM18PG181SN1_0603~D 2 1
1
+1.05V_VCCP
1 + 2 1
2
2 C550 0.1U_0402_16V4Z~D 1
2
1
1
AR29 +1.25V_RUN B23 B21 A21 AJ50
+1.25V_RUN_PEGPLL
+3.3V_RUN_TVDACC 1 C553 22n_0805_25V 2 3 C555 0.1U_0402_16V4Z~D
2
VCC_AXD_NCTF VCC_AXF_1 VCC_AXF_2 VCC_AXF_3 VCC_DMI +1.25V_RUN_A_SM
2
2
+VCC_RXR_DMI C556 220U_D2_4VY_R15M~D +1.25V_RUN C558 100U_D2E_6.3VM_R18M~D C557 10U_0805_4VAM~D
AXF
+1.25V_RUN
C
+1.8V_SM_CK 1 BK24 BK23 BJ24 BJ23 VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4
2
VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 VCCA_SM_7 VCCA_SM_8 VCCA_SM_9 VCCA_SM_10 VCCA_SM_11 VCCA_SM_NCTF_1 VCCA_SM_NCTF_2 VCCA_SM_CK_1 VCCA_SM_CK_2
AW18 AV19 AU19 AU18 AU17 AT22 AT21 AT19 AT18 AT17 AR17 AR16 BC29 BB29
L34 BLM18PG181SN1_0603~D 2 1
1
+1.05V_VCCP
R406 1 2 1 + 2 4.7U_0603_6.3V6M~D C559 1U_0603_10V4Z~D 22U_0805_6.3V6M~D C560 C562 22U_0805_6.3V6M~D 0_0805_5%~D
1 + 2 1
2
C546 0.1U_0402_16V4Z~D
U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1 +1.25V_RUN_AXD C544 2.2U_0603_6.3V6K~D
2
+3.3V_RUN_TVDACA 1 C534 22n_0805_25V 2 3
+3.3V_RUN_TVDAC 2 1
+3.3V_RUN
1 C533 22n_0805_25V 3
2
1
C539 0.1U_0402_16V4Z~D
L30 BLM18PG181SN1_0603~D 1 C540 10U_0805_10V4Z~D
D
CRT VTT
VCCA_DAC_BG VSSA_DAC_BG
A30 B32
+3.3V_RUN_DAC_BG
1
2
2
2
2 @ VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_MPLL B49 H49 AL2 AM2 +1.25V_RUN_DPLLA +1.25V_RUN_DPLLB +1.25V_RUN_HPLL +1.25V_RUN_MPLL
2
C543 4.7U_0603_6.3V6M~D 1 2
C533,C534,C536,C545,C553,C579 are being replaced by 0-ohm 0805 resistor
+VCC_TX_LVDS
PLL LVDS PEG
+3.3V_RUN_TVDACB 1 2
C552
+3.3V_RUN C597 0.1U_0402_16V4Z~D +VCC_PEG
PEG
C722 0.022U_0402_16V7K~D
VCCD_QDAC VCCD_HPLL
N28 AN2 U48
+1.5V_RUN_QDAC
+1.25V_RUN 1 1 C642 0.1U_0402_16V4Z~D
C570 0.1U_0402_16V4Z~D
C569 1U_0603_10V4Z~D
DMI
B
VTTLF
1
1
1
1
VCCD_LVDS_1 VCCD_LVDS_2
J41 H42
2
C571 0.1U_0402_16V4Z~D
1
1
C572 22U_0805_6.3VAM~D
C720 0.022U_0402_16V7K~D
2
+1.8V_RUN +1.8V_SUS
+1.25V_RUN
1
BLM18AG121SN1D_0603~D
1
1
A
C593 22U_0805_6.3VAM~D
C591 0.1U_0402_16V4Z~D C589 1U_0603_10V4Z~D 1 2
CLK
SM
C
1
1
1 C561
1
2
2
2
2
2
+VCC_TX_LVDS
A43
VCC_TX_LVDS
+1.25V_RUN_SM_CK
POWER
C40 B40 VCC_HV_1 VCC_HV_2
1
1
1
1
1
AD51 W50 W51 V49 V50
VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5
VCCA_TVA_DAC_1 VCCA_TVA_DAC_2 VCCA_TVB_DAC_1 VCCA_TVB_DAC_2 VCCA_TVC_DAC_1 VCCA_TVC_DAC_2
C25 B25 C27 B27 B28 A28
+3.3V_RUN_TVDACA +3.3V_RUN_TVDACB +3.3V_RUN_TVDACC
+1.25V_RUN +1.25V_RUN L35 BLM21PG221SN1D_0805~D 2 R408 1 2 0_0603_5%~D C567 10U_0805_4VAM~D R409 2 1 1_0402_5%~D
+1.25V_RUN_PEGPLL
C563 0.1U_0402_16V4Z~D
C564 22U_0805_6.3V6M~D
C565 1U_0603_10V4Z~D
C566 1U_0603_10V4Z~D
0.1U_0402_16V4Z~D
1
C568
TV TV/CRT
2
2
2
2
2
+1.5V_RUN VCCD_CRT VCCD_TVDAC M32 L29 +1.5V_RUN_QDAC +1.5V_RUN_TVDAC R815 100_0603_5%~D 1 2 +1.25V_RUN_HPLL +1.25V_RUN L37 +1.25V_RUN_MPLL
+VCC_RXR_DMI
AH50 AH51
VCC_RXR_DMI_1 VCC_RXR_DMI_2
1
1
Non-iAMT
45mA Max.
C574 1 1
A7 F2 AH1 C576 0.47U_0402_10V4Z~D C577 0.47U_0402_10V4Z~D 1 1 2 C578 0.47U_0402_10V4Z~D
+1.25V_RUN_PEGPLL C554 0.1U_0402_16V4Z~D
45mA Max.
VTTLF1 VTTLF2 VTTLF3
VCCD_PEG_PLL
2
2
2
2 1 BLM18AG121SN1D_0603~D 1 C573 0.1U_0402_16V4Z~D
+1.25V_RUN L38 2 1 BLM18AG121SN1D_0603~D
B
C575 22U_0805_6.3VAM~D
LVDS
2
+1.5V_RUN_TVDAC 1 1 3 C579 22n_0805_25V 2 0.1U_0402_16V4Z~D
2
2
2
0.1U_0402_16V4Z~D
2
2
2
2
LE88CLGM A0 QM20_FCBGA1299~D
@ R116 0_0603_5%~D 2 1 C581 1U_0603_10V4Z~D 2 1 R152 0_0603_5%~D
1
C584
+1.8V_RUN +1.8V_SUS
2
2 +1.25V_RUN_DPLLA +1.25V_RUN L39 +1.25V_RUN_DPLLB +1.25V_RUN L40 2 1 10U_MLZ2012E100PTAIN_60mA_25%_0805~D 1 C585 470U_D2_2.5VM_R15~D C588 0.1U_0402_16V4Z~D 1 + 2 C586 470U_D2_2.5VM_R15~D
R579 @ 0_0603_5%~D 1 2 2 R578 0_0603_5%~D +VCC_TX_LVDS_R 2
1 +VCC_TX_LVDS L42 1 C596 1000P_0402_50V7K~D C595 220U_D2_4VY_R15M~D 1 1 + 2 BLM18AG121SN1D_0603~D 2
@
40mA Max.
1 C587 +1.8V_SUS L41 2 1 R416 1_0603_5%~D C592 0.1U_0402_16V4Z~D +1.8V_SM_CK 0.1U_0402_16V4Z~D 1 + 2
2 1 10U_MLZ2012E100PTAIN_60mA_25%_0805~D
40mA Max.
2
2
2
Place caps close to VCC_AXF (Pin A21, B21, B23)
C590 10U_0805_4VAM~D
C594 10U_0805_4VAM~D 2 1
A
2
2
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
+1.05V_VCCP
+3.3V_RUN
2 1 1 2 D16 RB751V_SOD323~D R417 10_0603_5%~D
5 4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Crestline(4 of 6)
Size Date: Document Number
LA-3301P
Wednesday, March 07, 2007
1
Rev 1.0 Sheet 13 of 58
3
2
5
4
3
2
1
+1.05V_VCCP +3.3V_RUN R420 10_0603_5%~D 1 2 D17 2 1 3 +1.05V_VCCP U29F
D
+1.05V_VCCP U29G AT35 AT34 AH28 AC32 AC31 AK32 AJ31 AJ28 AH32 AH31 AH29 AF32 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 +1.05V_VCCP
BAT54CW_SOT323~D
1 + 2
1
1
2
2
Layout Note: 370 mils from edge
C
1
1
2
2
Layout Note: Inside GMCH cavity.
AB33 AB36 AB37 AC33 AC35 AC36 AD35 AD36 AF33 AF36 AH33 AH35 AH36 AH37 AJ33 AJ35 AK33 AK35 AK36 AK37 AD33 AJ36 AM35 AL33 AL35 AA33 AA35 AA36 AP35 AP36 AR35 AR36 Y32 Y33 Y35 Y36 Y37 T30 T34 T35 U29 U31 U32 U33 U35 U36 V32 V33 V36 V37
VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44 VCC_NCTF_45 VCC_NCTF_46 VCC_NCTF_47 VCC_NCTF_48 VCC_NCTF_49 VCC_NCTF_50
VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21
T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28
R30
VCC_13
POWER
+1.8V_SUS AU32 AU33 AU35 AV33 AW33 AW35 AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35 BJ32 BJ33 BJ34 BK32 BK33 BK34 BK35 BL33 AU30 VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36 0.1U_0402_10V7K~D 22U_0805_6.3V6M~D 22U_0805_6.3V6M~D C606
2 C608
1 C605 + 2
1
1 C607
1
2
2
VSS_SCB1 VSS_SCB2 VSS_SCB3 VSS_SCB4 VSS_SCB5 VSS_SCB6
A3 B2 C1 BL1 BL51 A51
Layout Note: Place on the edge
VCC GFX NCTF
Layout Note: Place C901 where LVDS and DDR2 taps.
POWER
+1.05V_VCCP
+1.05V_VCCP AL24 AL26 AL28 AM26 AM28 AM29 AM31 AM32 AM33 AP29 AP31 AP32 AP33 AL29 AL31 AL32 AR31 AR32 AR33 VCC_AXM_NCTF_1 VCC_AXM_NCTF_2 VCC_AXM_NCTF_3 VCC_AXM_NCTF_4 VCC_AXM_NCTF_5 VCC_AXM_NCTF_6 VCC_AXM_NCTF_7 VCC_AXM_NCTF_8 VCC_AXM_NCTF_9 VCC_AXM_NCTF_10 VCC_AXM_NCTF_11 VCC_AXM_NCTF_12 VCC_AXM_NCTF_13 VCC_AXM_NCTF_14 VCC_AXM_NCTF_15 VCC_AXM_NCTF_16 VCC_AXM_NCTF_17 VCC_AXM_NCTF_18 VCC_AXM_NCTF_19
1
1
1
VCC_AXM_1 VCC_AXM_2 VCC_AXM_3 VCC_AXM_4 VCC_AXM_6 VCC_AXM_5 VCC_AXM_7
AT33 AT31 AK29 AK24 AK23 AJ26 AJ23
+1.05V_VCCP
2
2
2
B
Layout Note: Place close to GMCH edge.
0.1U_0402_10V7K~D
1
1
1
VCC SM LF
2
2
2
LE88CLGM A0 QM20_FCBGA1299~D
Layout Note: Inside GMCH cavity.
R20 T14 W13 W14 Y12 AA20 AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31 AJ20 AN14
VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34
VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 VCC_AXG_NCTF_61 VCC_AXG_NCTF_62 VCC_AXG_NCTF_63 VCC_AXG_NCTF_64 VCC_AXG_NCTF_65 VCC_AXG_NCTF_66 VCC_AXG_NCTF_67 VCC_AXG_NCTF_68 VCC_AXG_NCTF_69 VCC_AXG_NCTF_70 VCC_AXG_NCTF_71 VCC_AXG_NCTF_72 VCC_AXG_NCTF_73 VCC_AXG_NCTF_74 VCC_AXG_NCTF_75 VCC_AXG_NCTF_76 VCC_AXG_NCTF_77 VCC_AXG_NCTF_78 VCC_AXG_NCTF_79 VCC_AXG_NCTF_80 VCC_AXG_NCTF_81 VCC_AXG_NCTF_82 VCC_AXG_NCTF_83
T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31
VCC CORE
220U_D2_4VY_R15M~D
220U_D2_4VY_R15M~D
1 C598 + 2
1 C599 + 2
Layout Note: 370 mils from edge.
D
C602 220U_D2_4VY_R15M~D
C603 22U_0805_6.3VAM~D
0.22U_0402_10V4Z~D
C604
330U_D2E_2.5VM~D
0.47U_0402_10V4Z~D
1U_0603_10V4Z~D C609
0.1U_0402_10V7K~D C610
0.1U_0402_10V7K~D C611
10U_0805_10V4Z~D C612
22U_0805_6.3VAM~D C600
1
1
1
1
1
1 C601
2
2
2
2
2
2
C613 0.22U_0402_10V4Z~D
VCC SM
C614 0.1U_0402_10V7K~D
Layout Note: Inside GMCH cavity for VCC_AXG.
C
22U_0805_6.3V6M~D
C616 0.22U_0402_10V4Z~D
C617 0.22U_0402_10V4Z~D
C615 C618
B
VCC GFX
C619 0.1U_0402_10V7K~D
C620 0.1U_0402_10V7K~D
VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7
AW45 BC39 BE39 BD17 BD4 AW8 AT6
VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D C621 C623 0.22U_0402_10V4Z~D C622 C624 0.22U_0402_10V4Z~D 0.47U_0402_10V4Z~D 1U_0402_6.3V4Z~D C625 1U_0402_6.3V4Z~D C626
1
1
1
1
1
1
1
C627
2
2
2
2
2
2
2
LE88CLGM A0 QM20_FCBGA1299~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title
Crestline(5 of 6)
Size Date: Document Number
LA-3301P
Wednesday, February 28, 2007
1
Rev 1.0 Sheet 14 of 58
5
4
3
2
5
4
3
2
1
U29I A13 A15 A17 A24 AA21 AA24 AA29 AB20 AB23 AB26 AB28 AB31 AC10 AC13 AC3 AC39 AC43 AC47 AD1 AD21 AD26 AD29 AD3 AD41 AD45 AD49 AD5 AD50 AD8 AE10 AE14 AE6 AF20 AF23 AF24 AF31 AG2 AG38 AG43 AG47 AG50 AH3 AH40 AH41 AH7 AH9 AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28 AK31 AK51 AL1 AM11 AM13 AM3 AM4 AM41 AM45 AN1 AN38 AN39 AN43 AN5 AN7 AP4 AP48 AP50 AR11 AR2 AR39 AR44 AR47 AR7 AT10 AT14 AT41 AT49 AU1 AU23 AU29 AU3 AU36 AU49 AU51 AV39 AV48 AW1 AW12 AW16 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41
U29J C46 C50 C7 D13 D24 D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36 F4 F40 F50 G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48 G8 H24 H28 H4 H45 J11 J16 J2 J24 J28 J33 J35 J39 K12 K47 K8 L1 L17 L20 L24 L28 L3 L33 L49 M28 M42 M46 M49 M5 M50 M9 N11 N14 N17 N29 N32 N36 N39 N44 N49 N7 P19 P2 P23 P3 P50 R49 T39 T43 T47 U41 U45 U50 V2 V3 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239