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Compal Confidential
2 2
P5WS5 Schematics Document
AMD Sabine
APU Llano / Hudson M3 / Vancouver Whistler_Seymour
DIS only / UMA only / PX Muxless with BACO
3 3
2011-04-20
LA-6973P REV: 1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/04 Deciphered Date 2010/08/04 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P5WS5 LA-6973P
Date: Wednesday, April 20, 2011 Sheet 1 of 50
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ZZZ1 ZZZ2
Compal Confidential PCB 46@
Part Number = DAZ0JU00100
PCB P5WS5 LA-6973P LS-6902P/6905P/6973P HDMI+HDCP LOGO
Model Name : P5WS5 RO0000003HM
1
VRAM 512M/1G/2G
64M16/128M16 x 8
page 18, 19
Sabine 1
DDR3
Thermal Sensor ATI Vancuver Whistler/ Seymour GFX x 16 Gen2
ADM1032 Mahattan Granville
page 14
uFCBGA-962 GFX x 4 (Group 1~4)
AMD FS1 APU Memory BUS(DDR3)
Page 13~17 204pin DDRIII-SO-DIMM X2
APU HDMI Dual Channel
VGA VGA VGA
(UMA / Muxless) Llano BANK 0, 1, 2, 3 Page 11,12
1.5V DDRIII 800~1600MHz
HDMI LVDS(eDP) CRT DP x1 (DP0 TXP/N0)
uPGA-722 Package
HDMI Conn.
page 23
DP x2 Page 6~10
Travis LVDS (DP0 TXP/N 0~1)
LVDS
2 LVDS Conn. Translator DP x 4 2
page 21 P_GPP x 3
Reserve eDP GEN2 (DP1 TXP/N 0~4) UMI
page 22 USB20 USB20/B USB30/B CMOS Bluetooth Mini Mini
UAM eDP
M/B*1 *2 *1 Camera Conn.
Card 1 Card 2
page 34 page 35 page 35 page 22 page 35 page 33 page 33
CRT Conn. FCH CRT (VGA DAC) Port 0 Port 1 Port 3 Port5 FSD0 Port 8 Port 9
page 24 FCH USB
Port 2
3.3V 48MHz
GPP1 GPP0
Hudson-M2/M3
HD Audio 3.3V 24.576MHz/48Mhz Port 6
uFCBGA-656 Port 7
MINI Card 1 LAN(GbE) S-ATA Gen2
WLAN BCM57785 Page 25~29 3G/B
page 33 page 31
GPP x 2 port 0 port 1 port 2 *2
3
LPC BUS 3
GEN2 page 35
SATA HDD1 SATA HDD2 ODD HDA Codec
RJ45
page 32 Conn. Conn. Conn. ALC271X page
page 30 page page 30 38
LED
page 37 ENE KB930
page 36
RTC CKT. USB30 USB30
page 25
On SUB/B On M/B Touch Pad Int.KBD
page 35 page 34 page 37 page 37
Power On/Off CKT. External board
page 37
LID SW - Power/B EC I/O Buffer
page 37
Fan Control
4
page 30 4
USB20/B
BIOS ROM
DC/DC -USB20 x2 page 35
Interface CKT. SYS BIOS (2M)
page 39 page 27 Security Classification Compal Secret Data Compal Electronics, Inc.
USB30/B Issued Date 2010/08/04 Deciphered Date 2010/08/04 Title
-USB20 x1+ USB30 x1 Block Diagrams
Power Circuit EC BIOS (128K) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
page 40~48 page 35 page 37 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
P5WS5 LA-6973P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 21, 2011 Sheet 2 of 50
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CLOCK DISTRIBUTION DISPLAY DISTRIBUTION
: LVDS PATH
, : eDP PATH
: APU HDMI PATH
LVDS CONN
B_SODIMM
D A_SODIMM D
: VGA HDMI PATH
TXOUT[0:2]+/- TXOUT[1:2]+/-
TXCLK+/- I2CC_SCL/DA
TZOUT[0:2]+/-
TZCLK+/-
I2CC_SCL/DA TXOUT[1:2]+/-
AMD R
I2CC_SCL/DA
TXOUT[0:2]+/- TZOUT[0:2]+/-
ATI VGA TXCLK+/- TZCLK+/-
I2CC_SCL/DA
MEM_MB_CLK7_P/N
MEM_MB_CLK1_P/N
MEM_MA_CLK7_P/N
MEM_MA_CLK1_P/N
1066~1600MHz
1066~1600MHz
Whistler/Seymour/Granville
APU_TXOUT[0:2]+/-
C
APU_TXOUT[1:2]+/- R R
APU_TXOUT_CLK+/-
APU_TZOUT[0:2]+/- APU_LVDS_CLK/DATA
CLK_PEG_VGAP/N
APU_TZOUT_CLK+/-
100MHz APU_LVDS_CLK/DATA
Place near
the pin
C
APU_DISP_CLKP/N
C
AMD 100MHz AMD LVDS_OUT C
RTD2132 DP0_TXP/N[0:1]_R VGA_TXOUT[1:2]+/-
CPU FS1 SOCKET
FCH DP_IN
DP0_AUXP/N_R VGA_LCD_CLK/DATA
APU_CLKP/N Hudson-M2/M3 VGA_TXOUT[0:2]+/- VGA_TZOUT[0:2]+/-
VGA_TXCLK+/- VGA_TZCLK+/-
100MHz Internal CLK GEN R
VGA_LCD_CLK/DATA
Place near
the pin
DP0_AUX GPP_CLK
100MHz
LVDS Transtator 32.768KHz 25MHz
R
C
DP0_TXP/N[0:1]
DP0_AUXP/N
B B
GPP4 GPP3 GPP2 GPP1 GPP0 DP0 DPE DPF
PCIE_GFX[0:11] C
USB30 M/B USB30 SUS/B WLAN WLAN GbE LAN APU VGA
OPT PCI Socket Mini PCI Socket PCIE_GFX[12:15] C PCIE_GFX[0:15]
DP1 R DAC1 DPA
25MHz
FCH
R R
R R
A A
CRT CONN HDMI CONN
Security Classification Compal Secret Data
Issued Date 2010/08/04 Deciphered Date 2010/08/04 Title
CLOCK / DISPLAY DISTRIBUTION
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom P5WS5 LA-6973P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, April 20, 2011 Sheet 3 of 50
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Voltage Rails
SIGNAL
Power Plane Description S1 S3 S5 STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
VIN Adapter power supply (19V) N/A N/A N/A Full ON HIGH HIGH HIGH HIGH ON ON ON ON
B+ AC or battery power rail for power circuit. N/A N/A N/A
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+CPU_CORE Core voltage for CPU ON OFF OFF
1
+CPU_CORE_1 Core voltage for CPU (0.7-1.2V) ON OFF OFF S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF 1
+CPU_CORE_NB Voltage for On-die VGA of APU ON OFF OFF
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+VGA_CORE 0.95-1.2V switched power rail ON OFF OFF
+0.75VS 0.75V switched power rail for DDR terminator ON ON OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.0VSG 1.0V switched power rail for VGA ON OFF OFF
+1.1ALW 1.1V switched power rail for FCH ON ON ON* Board ID / SKU ID Table for AD channel
+1.1VS 1.1V switched power rail for FCH ON OFF OFF Vcc 3.3V +/- 5%
+1.2VS 1.2V switched power rail for APU ON OFF OFF Ra/Rc/Re 100K +/- 5% BOARD ID Table
+1.5V 1.5V power rail for CPU VDDIO and DDR ON ON OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max Board ID PCB Revision
+1.5VS 1.5V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V 0 NA
+1.8VSG 1.8V switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V 1 P5WS5
+2.5VS 2.5V for CPU_VDDA ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V 2 P5WH5
+3VALW 3.3V always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V 3 P7YE5
+3V_LAN 3.3V power rail for LAN ON ON ON 4 56K +/- 5% 1.036 V 1.185 V 1.264 V 4 P7YS5
+3VS 3.3V switched power rail ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V 5 NA
+5VALW 5V always on power rail ON ON ON* 6 200K +/- 5% 1.935 V 2.200 V 2.341 V 6 NA
2
+5VS 5V switched power rail ON OFF OFF 7 NC 2.500 V 3.300 V 3.300 V 7 NA 2
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON
BTO Option Table WHIS@ U8 M3@ U25 M2@ U25
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BOM Structure BTO Item
UMA@ Display output from APU (UMA only or Mux)
UMAO@ UMA only VGA FCH M3 A13 FCH M2 A13
Part Number = SA00004C720 Part Number = SA000043IB0 Part Number = SA000042C60
APULVDS@ APU output LVDS (UMA only or Mux)
TL@ Translator (UMA only or Mux) BOM Config
APUEDP@ APU output eDP
VGA@ Use VGA (Mux or DIS only)
DISO@ Display output from VGA (DIS only)
x = 1 is read cmd, x= 0 is writee cmd. VAN@ Use Vancouver VGA
MAN@ Use Manhattan VGA
External PCI Devices
GRAN@ Use Granville VGA
Device IDSEL# REQ#/GNT# Interrupts SEYM@ WHIS@ VGA P/N
PX@ WOPX@ With & Without PX function
3 3
BACO@ BACO function (Mux)
WOBACO@ Without BACO function (Mux)
VGALVDS@ VGA output LVDS (DIS only)
VGAEDP@ VGA output eDP (DIS only)
128@ Use VRAM channel A&B
X76@ VRAM ID Table
EC SM Bus1 address EC SM Bus2 address
M2@ Use Hudson-M2
Device Address HEX Device Address HEX M3@ Use Hudson-M3
Smart Battery 0001 011X b 16H ADI ADM1032 (VGA) 1001 101X b 9AH EDP@ Use eDP display (Shared components)
USB30@ USB30 on M/B
USB20@ USB20 on M/B
3G@ With 3G function
930@ Use EC 930
9012@ Use EC 9012
ZERO@ ZERO Power ODD function
FCH FCH
HDT@ HDT debug port
4 SM Bus 0 address SM Bus 1 address 4
Device Address HEX Device Address HEX
DDR DIMM1 1101 000X b D0
DDR DIMM2 1101 001X b D2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/04 Deciphered Date 2010/08/04 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P5WS5 LA-6973P
Date: Wednesday, April 20, 2011 Sheet 4 of 50
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AMD APU FS1
BATTERY BATT+ PU3 PU19 +CPU_CORE
12.6V CHARGER ISL6267HRZ-T 0.7~1.475V VDD CORE 54A
+CPU_CORE
ISL6251AHAZ-T 0.7~1.475V VDDNB 27.5A
+CPU_CORE_NB +CPU_CORE_NB
+2.5VS +2.5VS VDDA 500mA
+2.5VS
+1.5V VDDIO 4.6A
PU13 +1.5V +1.5V
D AC ADAPTOR VIN RT8209MGQW +1.2VS VDDR 6.7A D
PU15 +1.2VS
19V 90W
APL5508
RAM DDRIII SODIMMX2
PU17 +1.2VS +1.5V VDD_MEM 4A
RT8209MGQW VTT_MEM 0.5A
B+ +0.75VS
PU4
+0.75VS
APL5336KAI +0.75VS
VGA ATI
+VGA_CORE Whistler/Seymour/Granville
PU10
+VGA_CORE 0.85~1.1V VDDC 47A
TPS51218DSCR
+VDDCI
0.9~1.0V VDDCI 4.6A
+VDDCI
DPLL_VDDC: 125 mA
PU14 +1.0VSG SPV10: 120 mA
+1.0VSG +1.0VSG
G9731G11U PCIE_VDDC: 2000 mA
DP[A:E]_VDD10: 680 mA
VRAM 512/1GB/2GB
U41 +1.5VSG
+1.5VSG +1.5VSG VDDR1: 3400 mA 64M / 128Mx16 * 4 / 8
AO4430L
PU5 +1.1VALW
RT8209MGQW PLL_PVDD: 75 mA +1.5VSG 2.4 A
TSVDD: 20 mA
AVDD: 70 mA
C VDD1DI: 100 mA C