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GM5(B) Pacino Intel Discrete & UMA Block Diagram
VER : B2A
A
Screw Hole blank Page POWER A
FAN & THERMAL
Penryn SMSC1423
PG 39 REGULATOR CPU VR
PG 45 PG 47 +1.5V_RUN/+1.05V_VCCP
PG 51
(478 Micro-FCPGA) PG 48
DC/DC
CLOCK REGULATOR +3.3V_ALW/+5V_ALW/
SLG8SP513V +1.8V_SUS/+1.25V_RUN +15V_ALW PG 52
POWER SYSTEM (QFN-64) /+0.9V_DDR_VTT
PG 3,4 PG 17 PG 49 VGA Core
RESET CIRCUIT PG 44 PG 50
BATT
AC/BATT CHARGER PG 46 667 / 800 / 1066 MHz FSB
LVDS
CONNECTOR
RUN POWER SW Panel Connector
PG 54 +3.3V_SUS/+5V_SUS
PG 26
PCIEx16 ATI M86-ME-LP
+5V/+3.3V/+1.8V
VGA
PG 53
CRT CONN.
Cantiga PCI EXPRESS GFX PG 27
GDDR2 x 8
B
HDMI B
DDR2-SODIMM1 667 / 800 MHZ DDR II (256M)
1299 uFCBGA HDMI CONN.
PG 23, 24 PG 18,19,20,21,22 PG 25
PG 15,16
667 / 800 MHZ DDR II DP BUS
DDR2-SODIMM2 PI3VDP411LSZDE PG 18
PG 5,6,7,8,9,10
PG 15,16 LAN
USB2.0 x 3
USB conn x 3 BCM5784M RJ45/Magnetics
SATA-ODD SATA PG 35
DMI interface PCIEx1 PG 43
PG 36 PG 42
PCIEx1
SATA-HDD SATA EXPRESS-CARD
USB2.0
PG 36
USB2.0 PG 30
ICH9-M PCIEx2
USB2.0 MINI-CARD
C PCIEx1 WLAN C
676 BGA PG 34
USB2.0
IHDA
USB2.0
USB2.0 MINI-CARD
PG 11,12,13,14 WWAN
AUDIO/AMP PG 33
STAC9228/92HD73C Biometric
Camera + D-MIC
PG 38
PG 40 PG 41 LPC MINI-CARD
WPAN
CIR PG 33
TSOP36136TR
Audio Audio KBC PG 37
SPK conn Jacks x3 ITE8512
18X8 1394 CONN.
PG 40 PG 41 33MHz PCI 8-in-1 Card Reader PG 29
PG 31 Keyboard
R5C833
SPI PS/2 PG 37 Card Reader CONN.
PG 28 PG 30
D
USER D
INTERFACE FLASH Touchpad
PG 38 2Mbyts
QUANTA
PG 32 PG 37
Title
COMPUTER
Schematic Block Diagram1
Size Document Number Rev
GM5 B2A
Date: Wednesday, June 25, 2008 Sheet 1 of 62
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Table of Contents Power States
CONTROL
PAGE DESCRIPTION POWER PLANE VOLTAGE PAGE DESCRIPTION ACTIVE IN
SIGNAL
1 Schematic Block Diagram
2 Front Page +PWR_SRC 10V~+19V 4,26,32,34,48,49,50,51,52,55 MAIN POWER S0~S5
3-4 Penryn
+RTC_CELL +3.0V~+3.3V 11,14,31,32 RTC S0~S5
5-10 Cantiga
3,13,26,31,32,34,36,37,38,44,46,49,52,53,54
A 11-14 ICH9M +3.3V_ALW +3.3V 8051 POWER ALWON S0~S5 A
15-16 DDRII SO-DIMM(200P)
+5V_ALW +5V 35,36,46,48,49,52,53,54 LCD/CHARGE POWER ALWON S0~S5
17 Clock Generator
18-24 VGA +15V_ALW +15V 26,36,37,52,53 LARGE POWER +5V_ALW S0~S5
25 HDMI
+3.3V_LAN +3.3V 42,43 LAN POWER AUX_ON
26 LCD connector
27 CRT +5V_SUS +5V 14,38,50,51,53 SLP_S5# CTRLD POWER SUS_ON
28 Card reader PCI interface
+3.3V_SUS +3.3V 3,11,12,13,14,20,30,37,38,43,48,49,50,51,53 SLP_S5# CTRLD POWER 3.3V_SUS_ON
29 Card reader & 1394
30 Express card & card reader conn. +1.8V_SUS +1.8V 6,8,9,15,48,49,50,53,55 SODIMM POWER DDR_ON
31 SIO
+0.9V_DDR_VTT +0.9V 16,49,53 SODIMM POWER 0.9V_DDR_VTT_ON
32 Flash/RTC
14,20,25,27,36,37,38,39,40,41,53
33 WWAN/WPAN +5V_RUN +5V SLP_S3# CTRLD POWER RUN_ON
34 WLAN 6,8,9,11,12,13,14,15,17,19,20,22,25,26,27,28,
+3.3V_RUN +3.3V 30,33,34,36,38,39,40,41,42,53,55 SLP_S3# CTRLD POWER 3.3V_RUN_ON
35 USB port
B 36 SATA HDD & ODD +1.8V_RUN +1.8V 19,20,21,22,23,24,25,38,53 SDVO POWER RUN_ON B
37 TP/KB/MB/CIR
+1.5V_RUN +1.5V 4,9,14,30,33,34,48,,53,55 CANTIGA/ICH8 POWER 1.5V_RUN_ON
38 switch/LED
39 FAN/Thermal +1.05V_VCCP +1.05V 3,4,5,6,8,9,11,14,37,48,55 CPU/CANTIGA/ICH8 POWER 1.05V_RUN_ON
40-41 Audio/CONN.
+VCC_CORE +0.7V~+1.5V 4,51 CPU CORE POWER IMVP_VR_ON
42-43 Docking Conn/Q-Switch
LCDVCC_TST_EN
44 System Reset Circuit +LCDVCC +3.3V 26 LCD Power & ENVDD
45-46 Screw hole & Charger
+5V_MOD +5V 36 Module Power MODC_EN#
47 Blank page
48 1.05VCCP & 1.5VRUN +5V_HDD +5V 36 HDD Power HDDC_EN#
49 1.8VSUS & 0.9VTT
+5V_ALW2 +5V 37,38.52,53 LED power source LDO output
50 VGA power circuit
51 CPU_ISL6266 (2phase)
52 D/D ISL6237 3.3V/5V
53 RUN Power Switch
C C
54 DCIN,Batt
55 EMI CAP GND PLANE PAGE DESCRIPTION
56 SMBUS BLOCK
8731AGND
57-58 Power statu & Block diagram 46
AGND_0.9V
49
AGND_DC/DC
52
AGND_DC2
48
AGND_DDR
49
AGND_ISL6260
51
GND ALL
D D
QUANTA
Title
COMPUTER
Index & Power Status
Size Document Number Rev
GM5 B2A
Date: Wednesday, June 25, 2008 Sheet 2 of 62
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1 2 3 4 5 6 7 8
H_A#[3..16] U42A H_D#[0..63] U42B H_D#[0..63]
5 H_A#[3..16] 5 H_D#[0..63] H_D#[0..63] 5
H_A#3 J4 H1 H_D#0 E22 Y22 H_D#32
A[3]# ADS# H_ADS# 5 D[0]# D[32]#
H_A#4 L5 E2 H_D#1 F24 AB24 H_D#33
A[4]# BNR# H_BNR# 5 D[1]# D[33]#
ADDR GROUP 0
ADDR GROUP 0
H_A#5 L4 G5 H_D#2 E26 V24 H_D#34
A[5]# BPRI# H_BPRI# 5 D[2]# D[34]#
H_A#6 K5 H_D#3 G22 V26 H_D#35 PAD T168 H_D#32
H_A#7 A[6]# H_D#4 D[3]# D[35]# H_D#36
M3 A[7]# DEFER# H5 H_DEFER# 5 F23 D[4]# D[36]# V23
H_A#8 N2 F21 H_D#5 G25 T22 H_D#37
A[8]# DRDY# H_DRDY# 5 D[5]# D[37]#
H_A#9 J1 E1 H_D#6 E25 U25 H_D#38 PAD T169 H_D#40
A[9]# DBSY# H_DBSY# 5 D[6]# D[38]#
DATA GRP 0
DATA GRP 2
H_A#10 N3 +1.05V_VCCP H_D#7 E23 U23 H_D#39
T176 H_A#11 A[10]# H_D#8 D[7]# D[39]# H_D#40
P5 A[11]# BR0# F1 H_BR0# 5 Layout Note: K24 D[8]# D[40]# Y25
PAD H_A#12 P2 H_D#9 G24 W22 H_D#41 H_D#53
A[12]# Place R116 T153T154 D[9]# D[41]# PAD T172
CONTROL
CONTROL
H_A#13 L2 D20 H_IERR# R132 56 +1.05V_VCCP H_D#10 J24 Y23 H_D#42
A
H_A#14 A[13]# IERR# close to PAD PAD H_D#11 D[10]# D[42]# H_D#43 A
P4 A[14]# INIT# B3 H_INIT# 11 J23 D[11]# D[43]# W24
H_A#15 P1 A[15]#
R116 CPU. H_D#12 H22 D[12]# D[44]# W25 H_D#44 PAD T173 H_D#57
H_A#16 R1 H4 51_NC H_D#13 F26 AA23 H_D#45
A[16]# LOCK# H_LOCK# 5 D[13]# D[45]#
M1 Modify X02-39 H_D#14 K22 AA24 H_D#46
5 H_ADSTB#0 H_REQ#[0..4] ADSTB[0]# D[14]# D[46]#
C1 H_RESET#_L R121 0 H_RESET# H_D#15 H23 AB25 H_D#47
5 H_REQ#[0..4] RESET# H_RESET# 5 D[15]# D[47]#
H_REQ#0 K3 F3 J26 Y26
REQ[0]# RS[0]# H_RS#0 5 5 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 5
H_REQ#1 H2 F4 H26 AA26
REQ[1]# RS[1]# H_RS#1 5 5 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 5
H_REQ#2 K2 G3 H25 U22
REQ[2]# RS[2]# H_RS#2 5 5 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 5
H_REQ#3 J3 G2
REQ[3]# TRDY# H_TRDY# 5 H_D#[0..63] H_D#[0..63]
H_REQ#4 L1
H_A#[17..35] REQ[4]# 5 H_D#[0..63] H_D#[0..63] 5
G6 H_D#16 N22 AE24 H_D#48
5 H_A#[17..35] HIT# H_HIT# 5 D[16]# D[48]#
H_A#17 Y2 E4 H_D#17 K25 AD24 H_D#49
A[17]# HITM# H_HITM# 5 D[17]# D[49]#
H_A#18 U5 H_D#18 P26 AA21 H_D#50
A[18]# D[18]# D[50]#
ADDR GROUP 1
ADDR GROUP 1
H_A#19 R3 AD4 ITP_BPM#0 H_D#19 R23 AB22 H_D#51
H_A#20 A[19]# BPM[0]# ITP_BPM#1 H_D#20 D[19]# D[51]# H_D#52
W6 A[20]# BPM[1]# AD3 Layout Note: L23 D[20]# D[52]# AB21
XDP/ITP SIGNALS
XDP/ITP SIGNALS
PAD T177 H_A#14 H_A#21 U4 AD1 ITP_BPM#2 Place voltage H_D#21 M24 AC26 H_D#53
A[21]# BPM[2]# D[21]# D[53]#
DATA GRP 1
DATA GRP 3
H_A#22 Y5 AC4 ITP_BPM#3 H_D#22 L22 AD20 H_D#54
PAD T180 H_A#9 H_A#23 A[22]# BPM[3]# ITP_BPM#4 divider within H_D#23 D[22]# D[54]# H_D#55
U1 A[23]# PRDY# AC2 M23 D[23]# D[55]# AE22
H_A#24 R4 A[24]# PREQ# AC1 ITP_BPM#5 0.5" of GTLREF H_D#24 P25 D[24]# D[56]# AF23 H_D#56
PAD T185 H_A#24 H_A#25 T5 AC5 ITP_TCK pin H_D#25 P23 AC25 H_D#57
H_A#26 A[25]# TCK ITP_TDI T155 T156 H_D#26 D[25]# D[57]# H_D#58
T3 A[26]# TDI AA6 P22 D[26]# D[58]# AE21
PAD T184 H_A#17 H_A#27 W2 AB3 ITP_TDO PAD PAD H_D#27 T24 AD21 H_D#59
H_A#28 A[27]# TDO ITP_TMS +1.05V_VCCP H_D#28 D[27]# D[59]# H_D#60
W5 A[28]# TMS AB5 R24 D[28]# D[60]# AC22
H_A#29 Y4 AB6 ITP_TRST# H_D#29 L25 AD23 H_D#61
T182 H_A#30 A[29]# TRST# ITP_DBRESET# H_D#30 D[29]# D[61]# H_D#62
U2 A[30]# DBR# C20 ITP_DBRESET# 13 T25 D[30]# D[62]# AF22
PAD H_A#31 V4 H_D#31 N25 AC23 H_D#63
H_A#32 A[31]# D[31]# D[63]#
W3 A[32]# 5 H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 5
H_A#33 AA4 THERMAL R134 56 +1.05V_VCCP
Modify X01-1 R60 M26 AF24
A[33]# 5 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 5
H_A#34 AB2 1K/F N24 AC20
A[34]# 5 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 5
B H_A#35 AA3 D21 H_PROCHOT# B
A[35]# PROCHOT# PAD T13
V1 A24 H_THERMDA V_CPU_GTLREF AD26 R26 COMP0 COMP0
5 H_ADSTB#1 ADSTB[1]# THERMDA H_THERMDA 39 GTLREF COMP[0]
B25 H_THERMDC R137 1K/F_NC CPU_TEST1 C23 MISC COMP[1] U26 COMP1 COMP1
THERMDC H_THERMDC 39 TEST1
A6 R127 1K/F_NC CPU_TEST2 D25 AA1 COMP2 COMP2
11 H_A20M# A20M# TEST2 COMP[2]
ICH
ICH
A5 C7 H_THERM PAD T14 CPU_TEST3 C24 Y1 COMP3 COMP3
11 H_FERR# FERR# THERMTRIP# TEST3 COMP[3]
C4 R53 PAD T147 CPU_TEST4 AF26
11 H_IGNNE# IGNNE# TEST4
R118 56 +1.05V_VCCP 2K/F PAD T3 CPU_TEST5 AF1 E5
TEST5 DPRSTP# H_DPRSTP# 6,11,51
D5 H CLK PAD T148 CPU_TEST6 A26 B5
11 H_STPCLK# STPCLK# TEST6 DPSLP# H_DPSLP# 11
C6 PAD T239 CPU_TEST7 C3 D24
11 H_INTR LINT0 TEST7 DPWR# H_DPWR# 5
B4 A22 B22 D6 R62 R59 R78 R87
11 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 17 6,17 CPU_MCH_BSEL0 BSEL[0] PWRGOOD H_PWRGOOD 11
A3 A21 B23 D7 54.9/F 27.4/F 54.9/F 27.4/F
11 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 17 6,17 CPU_MCH_BSEL1 BSEL[1] SLP# H_CPUSLP# 5
6,17 CPU_MCH_BSEL2 C21 BSEL[2] PSI# AE6 H_PSI# 51
Quard Core Only
F6 D2 Penryn Ball-out Rev 1a
TP6 TDI_1/RSV RSVD[06] TP16
TP7 D3 TDO_2/RSV Comp0,2 connect with
Zo=27.4ohm,Comp1,3 connect with
TP8 N5 BMP_1#[0]/RSV FSB BCLK BSEL2 BSEL1 BSEL0 Zo=55ohm, make those traces
TP9 M4 BMP_1#[1]/RSV
TP10 B2 BMP_1#[2]/RSV 667 166 0 1 1 length shorter than 0.5".Trace
AE8 H_THERMDA C777 H_THERMDC should be at least 25 mils away
TP11 BMP_1#[3]/VSS Modify X01-2/3
D8 2200P_NC 50 800 200 0 1 0
TP5
F8
DCLKPH_1/VSS from any other toggling signal.
TP12 ACLKPH_1/VSS
TP15 D22 GTLREF_2/RSV