Text preview for : DAS18ST_HR.pdf part of Keithley DAS18ST HR Keithley DAS DAS18ST_HR.pdf
Back to : DAS18ST_HR.pdf | Home
DAS-1800ST/HR Series
Register-Level
Programming
USER'S GUIDE
DAS-1800ST/HR Series
Register-Level Programming
User's Guide
Revision B - December 1994
Part Number: 90960
Table of Contents
1 I/O Addresses
Base Address +0h................................................................................................................................................ 1-2
A/D FIFO Data (Read) ............................................................................................................................... 1-3
QRAM Data (Read/Write) ......................................................................................................................... 1-4
A/D Conversion (Write)............................................................................................................................. 1-5
D/A Data (Write) for DAS-1800ST-DA Series ......................................................................................... 1-5
D/A Data (Write) for DAS-1802HR-DA ................................................................................................... 1-6
Base Address +2h (Data Select Register, Read/Write)........................................................................................ 1-7
Base Address +3h (Digital I/O) ........................................................................................................................... 1-8
Base Address +4h (Control Register A, Read/Write) .......................................................................................... 1-9
Base Address +5h (Control Register B, Read/Write) ........................................................................................ 1-13
Base Address +6h (Control Register C, Read/Write) ........................................................................................ 1-16
Base Address +7h (Status Register, Read/Write) .............................................................................................. 1-18
Base Address +8h (Burst Length Register, Read/Write) ................................................................................... 1-23
Base Address +9h (Burst Mode Conversion Rate Register, Read/Write) ......................................................... 1-23
Base Address +Ah (QRAM Address Start Register, Read/Write)..................................................................... 1-24
Base Address +Ch, +Dh, +Eh, and +Fh (82C54 Programmable Interval Counter/Timer)................................ 1-25
2 Programming Example
Programming an A/D Conversion........................................................................................................................ 2-1
Programming the QRAM with Channel-Gain Data ................................................................................... 2-1
Programming the Board Setup ................................................................................................................... 2-2
Writing to the DACs ........................................................................................................................................... 2-3
Preloading the DACs at Board Initialization.............................................................................................. 2-3
Updating DACs 0, 1, or 2 of a DAS-1800ST-DA Series Board ................................................................ 2-4
Updating DAC 3 of a DAS-1800ST-DA Series Board............................................................................... 2-4
Updating DAC 0 of a DAS-1802HR-DA Board......................................................................................... 2-4
Updating DAC 1 of a DAS-1802HR-DA Board......................................................................................... 2-4
Updating DAC 0 and DAC 1 of a DAS-1802HR-DA Board ..................................................................... 2-5
A Summary of I/O Address Bits
i
List of Tables
1 I/O Addresses
Table 1-1. I/O Address Map ...........................................................................................................................................1-1
Table 1-2. Gain-Code-Select Bits GN1 and GN0 ...........................................................................................................1-4
Table 1-3. Data-Source-Select Bits DSL2 and DSL0 .....................................................................................................1-7
Table 1-4. Trigger Modes Using an Internal A/D Pacer Clock.....................................................................................1-12
Table 1-5. Trigger Modes Using an External Pacer Clock ...........................................................................................1-13
Table 1-6. Interrupt Level Select Bits IL2 to IL0.........................................................................................................1-14
Table 1-7. DMA Level Select Bits DL2 to DL0 ...........................................................................................................1-15
Table 1-8. Pacer Clock Select Bits S1 and S0...............................................................................................................1-17
Table 1-9. Status Register Bit Manipulation Operations...............................................................................................1-18
Table 1-10. Read/Write Capabilities of Counter/Timer Registers .................................................................................1-26
A Summary of I/O Address Bits
Table A-1. Bit Assignments for 16-Bit Registers ...........................................................................................................A-1
Table A-2. Bit Assignments for 8-Bit Registers .............................................................................................................A-2
Table A-3. Summary of I/O Address Bits.......................................................................................................................A-3
ii
Preface
This guide describes the register-level functions of the DAS-1800ST/HR
Series boards and is offered as a supplement to the DAS-1800ST/HR
Series User's Guide. Unless this guide refers specifically to a
DAS-1801ST, DAS-1801ST-DA, DAS-1802ST, DAS-1802ST-DA,
DAS-1802HR, or DAS-1802HR-DA board, the guide refers to all boards
collectively as the DAS-1800ST/HR Series boards. At the same time, the
term DAS-1800 Series refers to all members of the DAS-1800 family of
data acquisition boards.
The DAS-1800ST/HR Series Register-Level Programming User's Guide is
intended for users whose applications require operational control beyond
what is provided by the software packages currently available for these
boards. To use the information in this manual, you must be familiar with
data acquisition principles and with the functions of the DAS-1800ST/HR
Series boards. You must also be familiar with the configuration and
installation requirements for the boards, and you must be experienced at
programming register-level functions.
Note: The information in this guide is not intended for use with any of
the software packages currently available for DAS-1800ST/HR Series
boards. If you want information on a particular software package, refer to
the manual for that package.
This guide is organized as follows:
q Chapter 1 describes the functions for each I/O address of the boards.
q Chapter 2 outlines example procedures for programming the boards.
q Appendix A summarizes functions of the bits at each I/O address.
iii
1
I/O Addresses
DAS-1800ST/HR Series boards use 16 addresses in the computer I/O
space. The addresses start at the base address and extend as shown in the
I/O map of Table 1-1.
Table 1-1. I/O Address Map
Location Function Type
Base Address +0h1 A/D FIFO2 Read
QRAM data Read/Write
A/D conversion and D/A data Write
Base Address +2h Data Select register Read/Write
Base Address +3h Digital I/O in byte Read
Digital I/O out byte Write
Base Address +4h Control Register A Read/Write
Base Address +5h Control Register B Read/Write
Base Address +6h Control Register C Read/Write
Base Address +7h Status register Read/Write
Base Address +8h Burst Length register Read/Write
Base Address +9h Burst Mode Conversion Rate register Read/Write
Base Address +Ah QRAM address start Read/Write
Base Address +Bh N/A ---
Base Address +Ch Counter 0 Read/Write
1-1
Table 1-1. I/O Address Map (cont.)
Location Function Type
Base Address +Dh Counter 1 Read/Write
Base Address +Eh Counter 2 Read/Write
Base Address +Fh Counter control Write
Notes
1
Accessto the data sources at Base Address +0h requires indirect addressing.
2
FIFO stands for first in, first out.
Note: Note that all register bits of fixed value, except the identification
value in the upper nibble of the Digital Input register (Base Address +3h),
are reserved for internal use and subject to change without notification; do
not use these bits.
The following sections describe the I/O map in more detail.
Base Address +0h
Base Address +0h is used for the following functions:
q Read data from the A/D FIFO
q Read/write data from/to the QRAM
q Write data to initiate an A/D Conversion
q Write data to DACs
Access to the data sources at Base Address +0h requires indirect
addressing, using the Data Select register. Refer to "Base Address +2h
(Data Select Register, Read/Write)" on page 1-7 for more information.
The use of Base Address +0h for each of these data sources and for A/D
conversion is discussed in the following subsections.
1-2 I/O Addresses
A/D FIFO Data (Read)
The 16-bit A/D FIFO data is read only and uses 16-bit data transfers on
the computer bus. Data is right-justified and in twos complement format
for bipolar mode and positive magnitude for unipolar mode.
While this address uses 16-bit data transfers on the PC bus, data words in
DAS-1800ST Series boards are actually 12-bits long. In bipolar mode,
bit 11 is the sign bit and bits 12 to 15 are sign-extender bits that are
always equal to bit 11. In unipolar mode, all data is positive; bits 12 to 15
are always 0 to indicate positive polarity.
Bit assignments for A/D FIFO data in DAS-1800ST Series boards set for
bipolar mode are as follows:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D11 D11 D11 D11 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Bit assignments for A/D FIFO data in DAS-1800ST Series boards set for
unipolar mode are as follows:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Data words in DAS-1802HR boards are 16-bits long. Bit assignments for
A/D FIFO data in DAS-1802HR boards set for bipolar or unipolar mode
are as follows:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Note: The Data Select register (Base Address +2h) must be set to 00h
prior to reading the A/D FIFO data.
1-3
QRAM Data (Read/Write)
The channel-gain QRAM is read/write when used in conjunction with the
QRAM Address Start register (Base Address +Ah). The QRAM uses
16-bit data transfers on the computer bus.
Bit assignments for QRAM data are as follows:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X X X X X GEXT GN1 GN0 MUX7 MUX6 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0
The bit names are defined and used as follows:
q X = Don't care.
q GEXT is the external gain control bit. This bit controls pin 39 on the
50-pin I/O connector and is used in conjunction with accessories that
have programmable gain. For the EXP-1800, GEXT is as follows: