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Dual P-Channel, Digital FET
General Description Features
These dual P-Channel logic level enhancement mode -25 V, -0.14 A continuous, -0.4 A peak.
field effect transistors are produced using Fairchild's RDS(ON) = 10 @ VGS= -4.5 V,
proprietary, high cell density, DMOS technology. This RDS(ON) = 13 @ VGS= -2.7 V.
very high density process is especially tailored to
minimize on-state resistance. This device has been Very low level gate drive requirements allowing direct
designed especially for low voltage applications as a operation in 3 V circuits (VGS(th) < 1.5 V).
replacement for bipolar digital transistors and small
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