Text preview for : Board_Layout.pdf part of Motorola V3688 Motorola V3688 Cellular phone Service Manual
Back to : Motorola V3688.part1.rar | Home
HEAD_INT KBR0, KBR1, KBR2 ( Keyboard ) KBC0, KBC1, KBC2, KBC3 BKLT_EN DP_EN HS_INT VIB_EN LED_RED LED_GRN LS1_IN LS2_IN LS3_TX LS3_RX CLK_SELCT TX_EN DM_CS TX_KEY RX_EN RX_ACQ RESET ( SDTX ) BDX ( TX_CLK ) BCLKX from / to MAGIC ( SCLK_OUT ) BCLKR ( SDFS ) BFSR ( SDRX ) BDR
N3 H2, H3, H1 K1, J4, J3, J2 K2 E10 KEYPAD L6 DISPLAY K4 INTERFACE M3 M2 E8 SIM D6 INTER E1 E6 FACE A1 C3 D2 C1 F5 E2 CTM E1 E4 E2 MODULE E3 E3 E4 M4 P2 C6 A2 A3 B4 C4 J6 SERIAL INTER FACE DSP
V2 C14, D4, E12, H4, J10, K6, N12 V3 B5, B9, B10, G12, K14, L11, N8 ( CE ) MQSPI_CS1 U700 L8 ( SPI_CLK ) MOSPI_CLK1 WHITE_CAP SPI M8 ( MAGIC SPI ) INTERFACE M7 ( SPI_DATA ) DX1 M E M O R Y CPU I N T E R F A C E
D7 - D0
J700 FLIP CON.
7, 9, 10, 11, 13, 14, 15, 17
DATA BUS
A0
ADDRESS BUS
( Flip Con. ) R_W V2 C9 E9 D11 D9 A9 CE2 CE3 R_W D6, E1 B2 U702 A1 SRAM G6 CE0 CE1 D7 F8 ( WhiteCap ) HS_INT -5V_EN LS_V1 2 U901 STDBY 1 LS_V1 -5V V2 RESET A4, A6, F6 B4 V2 RESET R_W DP_EN BKLT+ GND RTC_BATT
19 3, 4, 6, 12, 16 22 18 21 1 2, 6 ,24, 26 27
U701 EPROM EEPROM
CTM F3 A/D N6 A4 H5
15 PIN EXT CONN.
MAGIC_13MHz
AUDIO SPI
GCAP SPI
GCAP_CLK 13 MHz
GCLK 32.768 KHz
J 600 DSC_EN 13 RS232_RX 7 RS232_TX 6 BATT_FDBK 4 SW_RF 2 EXT_CHG_EN 8
EXT_B+
DEEP SLEEP CIRCUIT
V1
DSC BATT_PD SPI INTERFACE TIMER D7 K5 G14 BATT_SER_DATA CHRGC ISENSE EXT_B+ R932 RTC_BATT 4 3
5
KBR0, KBR1, KBR2 ( WhiteCap ) KBC0, KBC1, KBC2,KBC3 ( GCAP2 ) PWR_SW ( Q938 ) BKLT+
KEYBOARD
3 BATT+ 1, 2, 5, 6
BATT CON. J604 2 4
1
GND
V2
BATT_PD
D6 UART A6 INTERF.
( GCAP2 ) V2 ( WhiteCap ) VIB_EN B+ 1 5
Q932
THERM 6-8 BATT_THERM
1
2 U950
U801
4
4 ( GCAP2 ) V2
J810 J811 VIBRA CON.
14
EXT_B+
DUALBAND KRAMER
B+ CHRGC CR940 ISENSE
Q942 4
1, 2, 3
GND GND GND GND
1 3 10 15
VR830
F5 SPI INTERFACE
E8 C7 D6 CHARGE D9 REAL TIME SELECT F10 CLOCK F7 SENSE D10 F6 LEVEL J7 SHIFT J8 K7 G6 K10 H8 C8 Logic Control G4
VREF REG. V3 REG. V2 REG. V1 REG.
A7 B7
LED_RED ( WhiteCap ) LED_GRN
5 2 6 Q805 1
3 Q805 4
Y900
BATT+ EXT_B+ CLK PD SIM_I/O 6 4 5 LS1_IN LS2_IN LS3_TX LS3_RX PWR_SW STDBY G9 B5 J5 A6 C6 A10, C10 VREF 2.775V,for GCAP V3 1,8V, for WhiteCap V2 2.775V, for WhiteCap logic outputs, RAM, FLASH, EEPROM LS_V1 5.0V, for DSC Bus, Negative Voltage Regulator J900 SIM Con. 1 2 VSIM1
MAN_TEST_AD
5
DSC_EN_AD DOWNLINL_AD BATT_THERM ISENSE
A1 B2 SENSE A2 B3 CNTL. D9
U900 G_CAP2
ON / OFF
9
RESET
G5 C4 D2 C3
RX SIGNAL PATH TX SIGNAL PATH MAIN VCO SIGNAL PATH TUNING VOLTAGES REFERENCE CLOCK Orderable Part Non - Orderable Part EUROPE MIDDLE EAST & AFRICA
BKLT_EN
UPLINK DOWNLINK
11 12
MIC
J2 PA_DRV Interface Audio Codec H6 H7 K9 J9 SPRSPR+
2
VSIM REG. VBOOST1 REG.
VSIM1 3.0 or 5.0V, for SIM Card Circuit
U980
1
H3
H9
K5 E10
J650
B10 ALRTOUT
29.04.99
HEADSET CON.
V2
SPKR
CR901 Q938 L901
CUSTOMER SERVICES LEVEL 3 AL Block Diagram Dualband Kramer
BKLT+ ( Flip Con. )
ALRT HEAD_INT ALRT_VCC B+
V_BOOST1 Internal GCap use only (VSIM1, LS_V1)
Rev. 1.5
Q939
Ralf Lorenzen, Michael Hansen, Colin Jack, Ray Collins Page1
A1
GSM_LNA275
RX LOCAL OSCILLATOR
A9
GSM LNA
GSM_LNA275 DCS_LNA275 C FL460 925-960MHz B Q461 FL470 925-960MHz B Q1254 5 6 EXT ANT SW_RF U101 2 9 1805-1880MHz B FL450 U401 SWITCH CONTROL CIRCUIT DCS_LNA275 MIX_275 PAC_275 B+ Q451 C FL465 RF_V2 B+ RF_V1 1805-1880MHz B Q1254 E MIX_275 E FL457 C 400 MHz C B MIX_275
Osc. discrete circuty
Q1255 CR259 V1
800MHz E9
PLL
C8
U913 MAGIC
F7 ( SCLK_OUT ) BCLKR ( SDFS ) BFSR ( SDRX ) BDR to WhiteCap
4 10
7
Q490 C
C
A7 STEP ATT. SWITCH C7 F2
RXI DEMODULATION RXQ
RX SPI
G9 G8
SW_VCC
C Q242 E E Q240 C
B
F1 REG. H1
PHASE DET Divider 200KHz
G1 H9, J9
VRef
B
H2
13MHz SWITCH
J7
CR230
H7, C8; J1
SUPER FILTER
EGSM: 880-915Mhz DCS: 1710-1785MHz
1-3 U341 5
4
MUX Startup Ref. 1 /2
Prog. Divider 200KHz REF.
DM_CS EGSM: 1325-1360MHz DCS: 1405-1480MHz RVCO_250 DCS_VCO RX VCO CR251 CR250 Q262 C Q455 CR301 B EGSM: 880-915Mhz DCS: 1710-1785MHz PAC_275 Q253 Q255 C257
J6 MAGIC_13MHz G6 CLK_SELCT
to WhiteCap from WhiteCap
SF_OUT
C1 A1 B1
DUALBAND KRAMER
PA_B+
PHASE DET
Divider AFC
C1
REF. OSC. 26 MHz
5 FL300 2 3 4
10-15
1
U300 DCS PA U400 GSM PA
CR300 2 1, 7 C Q300 B
A3
26MHz Y230
PLL V1 DCS_SEL J8 C4 F9 ( CE ) MQSPI_CS1 SPI LOGIC CONTROL FACE G5 ( SPI_CLK ) MOSPI_CLK1 ( SPI_DATA ) DX1 J3 from WhiteCap GP04 INTER H4
10-15
CR306,307
7 2, 8
C
Q400
B
GSM_PINDIODE
-5V
SHIFT LEVEL CIRCUIT 7
U340 PAC
RF_IN 2 PAC_275
2 1, 3 NPA_MUTE 12
DET SAT.
U250 TX VCO
10 G_TX_VCO D_TX_VCO 6
6 4 SF_OUT
TX LOOP FILTER TXI
( SDTX ) BDX TX SPI J2 ( TX_CLK ) BCLKX G7 Q344 MODULATION
TXQ
4, 14 10 12 8 11 U341 DET_SW AOC_DRIVE SAT_DETECT
PA_B+
PAC_275
TVCO_250
( GSM / DCS SELECT )
Q343
TX_EN
RVCO_250
( RX VCO, GSM/DCS SELECT )
DETECT_SW AOC_DRIVE SAT_DETECT TX_KEY_OUT
A5 B6 B4 C5 PA CONTROL H8 LOGIC J4 CONTROL H5
RX_ACQ DM_CS TX_KEY from WhiteCap
TX_KEY_OUT NPA_MUTE TVCO_250 PAC_275 DCS_VCO MIX_275 GSM_LNA275 DCS_LNA275 G_TX_VCO D_TX_VCO GSM_PINDIODE
EUROPE MIDDLE EAST & AFRICA
29.04.99
RX SIGNAL PATH TX SIGNAL PATH
REFERENCE CLOCK Orderable Part Non - Orderable Part
GSM / DCS SELECT CIRCUIT
CUSTOMER SERVICES LEVEL 3 RF Block Diagram Dualband Kramer Ralf Lorenzen, Michael Hansen, Colin Jack, Ray Collins Page1 Rev. 1.5
MAIN VCO SIGNAL PATH TUNING VOLTAGES