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GSM Kramer Interface Document

Revision 1.54

DUAL BAND KRAMER HARDWARE INTERFACE DOCUMENT

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1 REVISION HISTORY ...................................................................................................................................4 2 PURPOSE / INTRODUCTION ...................................................................................................................5 3. GCAP II HARDWARE OVERVIEW ........................................................................................................6 3.1 POWER MANAGEMENT ....................................................................................................................................6 3.1.1 PGM0,1,2 Hardware Configuration .....................................................................................................6 3.1.2 V2 Linear Regulator ...............................................................................................................................7 3.1.3 V3 Linear Regulator ...............................................................................................................................7 3.1.4 VSIM Regulator ......................................................................................................................................7 3.1.5 V1 Regulator ...........................................................................................................................................7 3.1.6 V_BOOST Switcher Regulator...............................................................................................................7 3.1.7 V_BUCK Switcher...................................................................................................................................7 3.1.8 SQ_OUT -5V Charge Pump Switcher ...................................................................................................8 3.1.9 PA_DRV Alert/Backlight Regulator ......................................................................................................8 3.2 AUDIO MANAGEMENT .....................................................................................................................................8 3.2.1 Audio Output...........................................................................................................................................8
3.2.1.1 A1 Earpiece Speaker Amplifier............................................................................................................. 8 3.2.1.2 A2 Alert Amplifier ............................................................................................................................... 8 3.2.1.3 A4 External Audio Output Amplifier..................................................................................................... 8

3.2.2 Audio Input............................................................................................................................................10
3.2.2.1 A3 Transceiver Microphone Amplifier ................................................................................................ 10 3.2.2.2 A5 External Microphone Amplifier ..................................................................................................... 10 3.2.2.3 External Microphone Codec Input....................................................................................................... 10 3.2.2 Audio Paths .............................................................................................................................................. 10 3.2.2 Audio Gain Lineup.................................................................................................................................... 10

3.3 WHITECAP/GCAP II AUDIO CODEC I/F.......................................................................................................14 3.3.1 Audio CODEC Characteristics............................................................................................................14 3.4 SPI PROGRAMMING INTERFACE ............................................................................................................... 1516 3.4.1 SPI Pin Description:.............................................................................................................................16 3.4.2. SPI Operation Requirements ..............................................................................................................16 3.4.3. SPI Operation Description: ................................................................................................................17 3.4.4 SPI Addressing Modes..........................................................................................................................17 3.4.5 SPI Data Structure: ..............................................................................................................................19 3.4.6 SPI Initial Conditions:..........................................................................................................................19 3.5 A/D................................................................................................................................................................23 3.6 BATTERY CHARGER OPERATION ...................................................................................................................24 3.6.1 The following state diagram describes the state of the two charger control ports EXT_B+_EN and CHG/BATT_EN and the transitions between states....................................Error! Bookmark not defined. 4 WHITECAP LOGIC INTERFACES........................................................................................................29 4.1 DSC MODULE ..............................................................................................................................................29 4.2 UART - RS232 ............................................................................................................................................29 4.2.1 BATTERY SERIAL DATA COMMUNICATION (development board only).....................................29 4.2.3 I/O PORT SIGNALS ....................................................................... ERROR! BOOKMARK NOT DEFINED. 4.3 SIM INTERFACE.......................................................................................................................................30 4.3.1 GCAPII / SIM CARD INTERFACE.....................................................................................................30 4.3.2 GCAPII / WHITECAP INTERFACE ...................................................................................................30 4.3.3 SIM CLOCK .........................................................................................................................................30 4.3.4 Synchronous Transceiver (Kramer will not support this feature)...................................................31 4.3.5 UART ....................................................................................................................................................31 4.4 KEYPAD INTERFACE .....................................................................................................................................31 4.4.1 3 Element Keypad.................................................................................................................................32 4.5 MEMORY INTERFACES...................................................................................................................................32

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4.5.1 Flash ................................................................................................................................................ 3233
4.5.1.1 Read While Write (RWW) Capability................................................................................................. 33

4.5.2 EEPROM ..............................................................................................................................................34 4.5.3 SRAM....................................................................................................................................................34 4.5.4 Chip Select Assignments ......................................................................................................................34 4.5.5 Byte Accessing Memory Interface .................................................................................................. 3435 4.6 GPIO PORT ASSIGNMENT ................................................................................................................ 3536 4.6.1 VR/VA............................................................................................................................................... 3536 4.7 DSP DEBUG SIGNALS........................................................................................................................ 3738 4.8 JTAG INTERFACE ............................................................................................................................... 3738 4.9 ONE WIRE BUS.................................................................................................................................... 3839 4.10 DISPLAY INTERFACE...................................................................................................................... 3839 5 WHITECAP RF INTERFACE ..................................................................................................................33 5.0 INTRODUCTION ..............................................................................................................................................33 5.1 REFERENCE OSCILLATOR ..............................................................................................................................34 5.2 RX 2ND L OCAL OSCILLATOR ........................................................................................................................34 5.3 BATTERY SAVE OPERATION..........................................................................................................................34 5.4 TX POWER CONTROL OPERATION ................................................................................................................35 5.5 POWER SUPPLIES ...........................................................................................................................................41 5.6 LOGIC L EVELS ...............................................................................................................................................41 5.7 RXI / RXQ DIGITAL BASEBAND OUTPUTS ....................................................................................................41 5.8 RXI / RXQ ANALOG BASEBAND OUTPUTS ...................................................................................................43 5.9 AGC ..............................................................................................................................................................43 5.10 AFC.............................................................................................................................................................43 5.11 CE ...............................................................................................................................................................48 5.12 ADAPT.......................................................................................................................................................49 5.13 TX DATA T RANSMISSION ...........................................................................................................................49 5.14 PROGRAMMING EXAMPLE ...........................................................................................................................50 5.15 MAGIC / WHITECAP MQSPI INTERACE .....................................................................................................53 5.16 POWER ON RESET (POR) OF SPI................................................................................................................66 5.17 MAGIC / WHITCAP INTERFACE ..............................................................................................................67 5.18 MAGIC / PAC INTERFACE ........................................................................................................................68 5.19 MAGIC / FIRM IC INTERFACE..................................................................................................................68 5.20 MAGIC / TX VCO INTERFACE..................................................................................................................68 5.21 MAGIC / RX VCO INTERFACE..................................................................................................................69 5.22 MAGIC / ISOLATION AMP INTERFACE .......................................................................................................70

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1 REVISION HISTORY
Issue REV 1.0 REV 1.1 REV 1.2 REV 1.3 Date 4/1/98 8/10/98 8/14/98 8/20/98 Purpose Kramer First Release General Editing General Editing Added IRQ Section, Hookswitch Change, Removed Proposed Matrix Added B+ Threshold data, Therm data for 38 deg., new audio gains, contrast control definition. Changed 5V_EN description, ONOFF1/2 power up sequence. Added default states for RTS/EXT_CHG_ENABLE, corrected line states. Added charger section. Added Added display power down sequence.

REV 1.4

10/14/98

REV 1.5

10/29/98

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2 PURPOSE / INTRODUCTION The purpose of this document is to list and define the supplies and interfaces for the International GSM/DCS Kramer cellular phone. The radio will bring to market the WCP (Wireless Communication Processor), GCAP II audio interface and power control IC as well as the air interface MAGIC IC. At the time of market introduction The WCP core will run at 1.8V all the other ICs will run at 2.775V. A 1.8V version will evolve from the original design as soon as the interface ICs (SRAM, Flash ROM etc.) become available. This document is meant as a guide for the hardware and software implementation. All signals are CMOS levels unless otherwise stated. Signals with a '*' in front of them are active low, all others are active high. CMOS levels are taken from the WCP signal specification, and are as follows (Vcc is defined as 2.7V): *Vih: *Vil: *Voh: *Vol: 0.7*Vcc to (Vcc+0.3Vdc) (Vss-0.3Vdc) to 0.2*Vcc (Vcc-0.2Vdc) to Vcc 0 to 0.4Vdc

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3.

GCAP II Hardware Overview

Global Control Audio Power II (GCAP II) is a power and audio management IC. It incorporates many of the functions of various different power and audio management ICs into one platform. Kramer will be using the 100 ball BGA package. · Five programmable linear regulators (VSIM1, Ref, V1, V2, and V3) which provide all voltages for the logic IC' s. · Two Buck or Boost switching regulators (PWM#1 and PWM#2) · Five audio amplifiers (A1 through A5) for driving the speaker, alert, and external audio or amplifying signals from the transceiver microphone, and external microphone · One 13 bit linear audio CODEC for bringing in external digital audio data · One 8 channel 8 bit A/D · One PA high end regulator which is used to create ALRT_VCC for driving the alert and back light. · One real time clock which is used for the sleep mode clock. · A charger control circuit · Turn on and turn off control circuits to properly control powering the transceiver.

3.1

Power Management

3.1.1

PGM0,1,2 Hardware Configuration PGM0 and PGM1 alone determine the battery mode of GPAP II. This is necessary because the startup and shutdown voltages need to be available without processor intervention. The following shows the start-up configurations available.
PGM0 B+ 0 B+ 0 PGM1 0 0 B+ B+ Battery Mode 3 cells 3 cells 4 cells 5 cells Switcher #1 Mode 000 (Pass through) 110 (BOOST) 110 (BOOST) 100 (3.2V BUCK) Switcher #2 Mode 000 (Pass through) 010 (2.2V BUCK) 100 (3.2VBUCK) 010 (2.2V BUCK)

SWModeA and B Bit Definition
SWMode2 0 0 0 0 1 1 1 1 SWMode1 0 0 1 1 0 0 1 1 SWMode0 0 1 0 1 0 1 0 1 Output V Pass thru 1.875V 2.20V 2.775V 3.20V 3.80V 5.60V Power down switcher Mode BUCK BUCK BUCK BUCK BUCK BUCK BOOST

At power-up, SWMode will be determined by PGM0 and PGM1. At power-up PGM2 alone determines the output of V3. If PGM2 is connected to B+, V3 is 2.775V. If PGM2 is connected to ground, as in Kramer, V3 is 2.003V. No processor intervention is necessary.

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3.1.2

V2 Linear Regulator V2 is a programmable linear regulator. It is programmed through the SPI bus to outputs from 2.775V to 3.6V in 0.12V steps. For Kramer V2 is programmed to 2.775V. The regulator is supplied by B+ Note: P1 Modulus B+ can not exceed 7.0V. Future versions of GCAP II will support having V2 supplied by PA_DRV therefore the limit on B+ will change to 9.0V. This regulator is on whenever the radio is turned on. V2 is the supply for WhiteCap logic outputs, RAM, FLASH, and display.

3.1.3

V3 Linear Regulator V3 is a programmable linear regulator with an output voltage which is determined by PGM2 at power-up. It is either 2.008V if PGM2 is connected to ground or 2.775V if PGM2 is connected to B+. After power-up V3 can be programmed through the SPI bus to voltages from 1.8V to 2.8V in 0.13V steps. For Kramer V3 is programmed to 1.8V. The regulator is supplied by B+ Note: P1 Kramer B+ can not exceed 7.0V. Future versions of GCAP II will support having V3 supplied by PA_DRV therefore the limit on B+ will change to 9.0V. V3 is the supply for the WhiteCap core (does not include logic output supply). For example, V3 supplies the ARM core, Clock amplifier, DSP Core, and input logic. For Ram 2 Whitecap V3 is programmed to 1.8V.

3.1.4

VSIM Regulator VSIM is a programmable linear regulator. It is programmed through the SPI bus to either 5.0V or 3.0V. For Kramer VSIM is programmed dynamically to 5.0V. VSIM is supplied by V_BOOST1 and supplies the SIM card.

3.1.5

V1 Regulator V1 is a programmable linear regulator. It is programmed through the SPI bus to either 5.0V or 2.775V. For Kramer V1 is programmed to 5.0V and is supplied by V_BOOST1 This regulator is on whenever the radio is turned on. V1 supplies the DSC bus.

3.1.6

V_BOOST1 Switcher Regulator V_BOOST1 is a switching regulator. At power up pins PMG0 and PMG1 determine the mode of the switcher. For Kramer V_BOOST1 is programmed to 5.6V because PMG0 is shorted to B+ and PMG1 is shorted to ground. This regulator is on whenever the radio is turned on. V_BOOST1 supplies V1 and VSIM. The Boost regulator is PWM#2 for P1 Modulus Note: P1 Kramer B+ can not exceed 7.0V. Future designs of GCAP II will have PWM#1 as the boost regulator in 4 cell mode. Therefore the 7.0V limit on B+ will increase to 9.0V.

3.1.7

V_BUCK Switcher V_BUCK is a switching regulator. At power up, pins PMG0 and PMG1 determine the mode of the switcher. For Kramer V_ BUCK is not used. The current GCAP II design uses PWM#1 as the Buck

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regulator in 4 cell mode. This will change to PWM#2 in the future. Note: the max. input voltage on PWM#2 (PSCR2) is 7.0V.

3.1.8

SQ_OUT -5V Charge Pump Switcher SQ_OUT is a square wave with a peak to peak voltage equal to VIN1-0.1V. It is used to create an unregulated charge pump voltage equal to -(VIN1-0.1V-2*VFdiode). For Kramer this output should be disabled.

3.1.9

PA_DRV Alert/Backlight Regulator PA_DRV is a programmable linear regulator which drives an external P channel MOSFET. It is programmed by setting PA_B3-0 to one of 16 codes corresponding to an output of 2.6V to 7.00V incremented by 0.40V steps. Initially PA_DRV is off until set via SPI. For Kramer PA_DRV regulates ALRT_VCC to 3.0V (PA_B3-0=0001). This regulator is turned on and off by LS3_TX if PA_ON1 is enabled (high). PA_DRV powers the alert and backlights. Future GCAP IIs will have PA_DRV power up at 5.8V and only allow programming up to 7.0V. This way PA_DRV can supply V2IN and V3IN without exceeding the 7.0V maximum input.

3.2

Audio Management

3.2.1

Audio Output

3.2.1.1 A1 Earpiece Speaker Amplifier A1 is the transceiver earpiece speaker amplifier. It is powered by V2 and is driven through a multiplexer by the audio CODEC output. A1CTRL disables SPKR+ if high, but does not enable or disable SPKR-.

3.2.1.2 A2 Alert Amplifier A2 is the alert amplifier. It is powered by ALRT_VCC and is driven through a multiplexer by the audio CODEC output.

3.2.1.3 A4 External Audio Output Amplifier A4 is the external speaker amplifier. It is powered by V2 and is driven through a multiplexer by the audio CODEC output.

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SPKROUT SPKRIN AUDOG AUDOS A1 SPKR+ SPKRALRT+ DAC PGA A2 ALRTEXTOUT

A4

Above is a block diagram of the audio output section. Any one of three outputs can be selected. These outputs connect to the earpiece speaker amplifier, A1, the alert amplifier, A2, and the external audio out amplifier, A4. All outputs use the same converter so only one output is active at a time (unless A2ON is programmed high).The gain of the output can be selected in 5dB steps from -35dB to +0dB. This gain block is an analog system. The Audio Output bits are programmed via SPI and they control the configuration of the output section. These bits select the gain, enable or disable the audio output, select or deselect dithering, and select or deselect the high pass output filter. CODEC Output High Pass/Low Pass Filter
AUDOHPF 0 1 Description Low pass filter only Enables high pass filter with low pass filter

At this point in development high pass filter should be disabled. Audio Output Bit Definition (all are R/W)
Name AUDOG AUDOS ADITH AUDOHPF # of Bits 3 2 1 1 Description Audio Output Gain (-35dB to +0dB in 5dB steps) Audio Output Select (A1, A2, A4, or no output) Audio Output Dither bit. Logic low enables dithering. Audio Output High Pass Filter. Logic high enables the filter.

For Kramer the Audio Output bits for AUDOS, ADITH, and AUDOHPF should be set to all zeros. (This is the same as power-up default for AUDOS and ADITH. See 3.4.5 SPI Data Structure for addresses.) AUDOG should be set to all ones for lowest gain. AUDOG Bit Definition
Bit AUDOG0 AUDOG1 AUDOG2 Description Logic high adds -5dB, logic low adds 0dB Logic high adds -10dB, logic low adds 0dB Logic high adds -20dB, logic low adds 0dB

AUDOS Bit Definition
AUDOS1 0 0 1 1 AUDOS0 0 1 0 1 Output Selected None (to power off, CDC_EN =0 and AUDOS =00) A1 (A1 powered up) A2 (A2 powered up) A4 (A4 powered up)

Audio Output Dither, ADITH When the output dither bit, ADITH, is reset to a logic low, dithering is enabled. Dithering decorrelates the periodic modulator quantization noise of the output converter. If ADITH is set to a logic high, dithering is disabled.

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3.2.2.1 A3 Transceiver Microphone Amplifier A3 is the transceiver microphone amplifier. It is powered by V2 and, through a multiplexer, drives the audio CODEC input

3.2.2.2 A5 Aux Microphone Amplifier A5 is the AUX microphone amplifier. I t is powered by V2 and, through a multiplexer, drives the audio CODEC input

3.2.2.3 External Microphone Codec Input This is an external microphone input without amplification and is used for the headset microphone. This input, through a multiplexer, drives the audio CODEC input Below is a block diagram of the audio input section. Any one of three equivalent microphone inputs can be selected. These inputs are EXT_MIC, the output of the differential input microphone amplifier, A3 or, the output of the differential auxiliary microphone amplifier, A5. These three inputs are single ended with respect to VAG. Note that MICIN+ should be DC connected to VAG to avoid an offset relative to the A/D input. MIC_BIAS is derived from VAG for best noise performance. MB_CAP bypasses the gain from VAG to MIC_BIAS to keep the noise balanced. MIC_BIAS is disabled if CDC_EN is low or if AUDIS is programmed to 00.
MIC_OUT MICIN+ MICINVAG AUX_MICAUX_OUT EXT_MIC A5 PGA A3 ADC AUDIS AUDIG

Following the input stage and multiplexer is a selectable gain stage and 30kHz low-pass antialiasing filter. This lowpass filter may be designed to whatever order is needed to insure that aliased components are not present in the output. The gain of the selectable gain stage can be selected in 1dB steps from -7dB to +8dB. Depending on the design of the A/D converter the output of the antialiasing filter may be clamped to keep from overdriving the A/D converter. The audio input A/D converter converts the incoming signal to 13-bit 2's compliment linear PCM words at an 8 or 8.1 kHz rate. Following the A/D converter, the signal is digitally filtered, lowpass and selectable high-pass. The digital filter characteristics are shown below. The filter characteristics are the same for both input and output except for the high pass function. (Note that all filter frequencies increase by 8.1/8.0 if DCLK is selected to generate FSYNC = 8.1kHz) CODEC Input High Pass/Low Pass Filter
AUDIHPF 0 1 Description Low pass filter only Enables high pass filter with low pass filter

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The audio input bits control the configuration of the input section. These bits select the gain, enable or disable the input, select between the EXT_MIC, A5 amplifier output, or A3 amplifier output, and select or deselect the high pass input filter. Also, these bits can select a loopback mode that takes the digital output of the input A/D converter, and loops it directly back to the D/A output section for testing. Audio Input Bit Definition (all are R/W)
Name AUDIG AUDIS AUDIHPF ALM # of Bits 4 2 1 1 Description Audio Input Gain (-7dB to +8dB in 1dB steps) Audio Input Select (EXT_MIC, AUX_MIC, or A3) Audio Input High Pass Filter. Logic high enables the filter. Audio Loopback Mode. Logic high enables loopback.

For Kramer the Audio Input bits for AUDIG, AUDIS, AUDIHPF, and ALM should be set to all zeros. (This is the same as power-up default for AUDIS and ALM. See 3.4.5 SPI Data Structure for addresses.) AUDIG Bit Definition
Bit AUDIG0 AUDIG1 AUDIG2 AUDIG3 Description Logic high adds 0dB, logic low adds -1dB Logic high adds 0dB, logic low adds -2dB Logic high adds 0dB, logic low adds -4dB Logic high adds 8dB, logic low adds 0dB

AUDIS Bit Definition
AUDIS1 0 0 1 1 AUDIS0 0 1 0 1 Input Selected None (input section and MIC_BIAS powered off) MICIN (and powers up A3) AUX_MIC (and powers up A5) EXT_MIC

Audio Loopback Mode, ALM When audio loopback mode, ALM, is set to a logic high, the output of the A/D converter is looped back to the input of the D/A converter. In this mode the performance of the CODEC is degraded to that of a second order modulator. Loopback mode is used for testing. When ALM is reset to logic low, loopback is disabled. 3.2.3 Audio Paths The Following table shows the required settings for the different audio configurations supported by Kramer. GCAP II SPI AUDIS1,0 01b 10b GPIO BOOM_EN H L

Configuration Internal Audio Boom Headset

AUDOS1,0 01b 01b

A1CTRL L H

3.2.4

Gain Lineups The Following tables define the audio output gains for the various Kramer audio configurations.

KRAMER AUDIO GAIN TABLE

9/24/98

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Handsfree - Default Table(Regular Voice) BIC Vol. Hardware Cntrl Vol. Cntrl 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 Handsfree - Alert Table BIC Vol. Hardware Cntrl Vol. Cntrl 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 Handsfree - Tones Table(DTMF Tones) BIC Vol. Hardware Cntrl Vol. Cntrl 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0

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Spkr Multiplier 0 0 0 0 0 0 0 0

Sdtone Multiplier 0 0 0 0 0 0 0 0

Speaker Attenuation 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF

Sdtone Attenuation 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF

Total Spkr Gain -20.0 -15.0 -10.0 -5.0 0.0 5.0 10.0 15.0

Total Sdtone Sidetone Lev Gain 0.0 XX 0.0 XX 0.0 XX 0.0 XX 0.0 XX 0.0 XX 0.0 XX 0.0 XX

Spkr Multiplier 0 0 0 0 0 0 0 0

Sdtone Multiplier 0 0 0 0 0 0 0 0

Speaker Attenuation 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF

Sdtone Attenuation 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF

Total Spkr Gain -20.0 -15.0 -10.0 -5.0 0.0 5.0 10.0 15.0

Total Sdtone Sidetone Lev Gain 0.0 XX 0.0 XX 0.0 XX 0.0 XX 0.0 XX 0.0 XX 0.0 XX 0.0 XX

Spkr Multiplier 0 0 0 0 0 0 0 0

Spkr/Sdtone Mult. 0 0 0 0 0 0 0 0

Speaker Attenuation 4800 4800 4800 4800 4800 4800 4800 4800

Sdtone Attenuation 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF

Total Spkr Gain -25.0 -20.0 -15.0 -10.0 -5.0 0.0 5.0 10.0

Total Sdtone Sidetone Lev Gain 0.0 XX 0.0 XX 0.0 XX 0.0 XX 0.0 XX 0.0 XX 0.0 XX 0.0 XX

HandSet - Default Table(Regular Voice) BIC Vol. GCAPII Vol. Spkr Cntrl Cntrl Multiplier 3 4 0 4 3 0 4 3 0 5 2 0 6 1 0 6 1 0 7 0 0 7 0 0

Spkr/Sdtone Mult. 2 2 1 1 0 0 0 0

Speaker Attenuation 7200 5A7E 7FFF 65AB 50C2 7200 5A7E 7FFF

Sdtone Attenuation 65AB 47FA 6567 47FA 65AB 47FA 32FA 2412

Total Spkr Gain -21.0 -18.0 -15.0 -12.0 -9.0 -6.0 -3.0 0.0

Total Sdtone Sidetone Lev Gain 10.0 -11.0 7.0 -11.0 4.0 -11.0 1.0 -11.0 -2.0 -11.0 -5.0 -11.0 -8.0 -11.0 -11.0 -11.0

HandSet - Default Boosted Table(Alert)

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BIC Vol. Cntrl 0 0 0 0 0 0 0 0

GCAPII Vol. Spkr Cntrl Multiplier 3 0 3 0 2 0 1 0 1 0 0 0 0 0 0 1

Spkr/Sdtone Mult. 0 0 0 0 0 0 0 0

Speaker Attenuation 5A7E 7FFF 65AB 50C2 7200 5A7E 7FFF 7FFF

Sdtone Attenuation 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF

Total Spkr Gain -18.0 -15.0 -12.0 -9.0 -6.0 -3.0 0.0 6.0

Total Sdtone Sidetone Lev Gain 0.0 XX 0.0 XX 0.0 XX 0.0 XX 0.0 XX 0.0 XX 0.0 XX 0.0 XX

HandSet - Tones Table(In Call -Tones) BIC Vol. GCAPII Vol. Spkr Cntrl Cntrl Multiplier 3 4 0 3 4 0 3 4 0 4 3 0 5 2 0 5 2 0 6 1 0 6 1 0 HandSet - Tones Boosted Table(Out of Call - Tones) BIC Vol. GCAPII Vol. Spkr Cntrl Cntrl Multiplier 4 0 0 3 0 0 3 0 0 2 0 0 1 0 0 1 0 0 0 0 0 0 0 0 Boom Headset - Default Table(Regular Voice) BIC Vol. GCAPII Vol. Spkr Cntrl Cntrl Multiplier 4 0 0 3 0 0 3 0 0 2 0 0 1 0 0 1 0 0 0 0 0 0 0 0

Spkr/Sdtone Mult. 3 2 2 1 1 0 0 0

Speaker Attenuation 4000 5A7E 7FFF 65AB 50C2 7200 5A7E 7FFF

Sdtone Attenuation 5A7E 7FFF 5A7E 7FFF 5A7E 7FFF 5A7E 4000

Total Spkr Gain -26.0 -23.0 -20.0 -17.0 -14.0 -11.0 -8.0 -5.0

Total Sdtone Sidetone Lev Gain 15.0 -11.0 12.0 -11.0 9.0 -11.0 6.0 -11.0 3.0 -11.0 0.0 -11.0 -3.0 -11.0 -6.0 -11.0

Spkr/Sdtone Mult. 0 0 0 0 0 0 0 0

Speaker Attenuation 7200 5A7E 7FFF 65AB 50C2 7200 5A7E 7FFF

Sdtone Attenuation 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF

Total Spkr Gain -21.0 -18.0 -15.0 -12.0 -9.0 -6.0 -3.0 0.0

Total Sdtone Sidetone Lev Gain 0.0 XX 0.0 XX 0.0 XX 0.0 XX 0.0 XX 0.0 XX 0.0 XX 0.0 XX

Spkr/Sdtone Mult. 1 1 0 0 0 0 0 0

Speaker Attenuation 7200 5A7E 7FFF 65AB 50C2 7200 5A7E 7FFF

Sdtone Attenuation 7FFF 5A7E 7FFF 5A7E 4000 2D6A 2026 16C2

Total Spkr Gain -21.0 -18.0 -15.0 -12.0 -9.0 -6.0 -3.0 0.0

Total Sdtone Sidetone Lev Gain 6.0 -15.0 3.0 -15.0 0.0 -15.0 -3.0 -15.0 -6.0 -15.0 -9.0 -15.0 -12.0 -15.0 -15.0 -15.0

Boom Headset - Tones Table(In Call Tones) (Out of call same Level)

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BIC Vol. Cntrl 0 0 0 0 0 0 0 0 GCAPII Vol. Spkr Cntrl Multiplier 4 0 4 0 4 0 4 0 4 0 4 0 3 0 3 0 Spkr/Sdtone Mult. 3 3 3 2 2 1 1 0 Speaker Attenuation 1449 1CA7 2879 392C 50C2 7200 5A7E 7FFF

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Sdtone Attenuation 7FFF 7FFF 5A7E 7FFF 5A7E 7FFF 5A7E 7FFF Total Spkr Gain -36.0 -33.0 -30.0 -27.0 -24.0 -21.0 -18.0 -15.0 Total Sdtone Sidetone Lev Gain 18.0 -18.0 18.0 -15.0 15.0 -15.0 12.0 -15.0 9.0 -15.0 6.0 -15.0 3.0 -15.0 0.0 -15.0

AUDOG2 Bit5 GCAPII Decimal 0 1 2 3 4 5 6 7

AUDOG1 Bit6

AUDOG0 Bit7 H/W Attenuation 0 -5 -10 -15 -20 -25 -30 -35

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

3.3

WhiteCap/GCAP II Audio Codec I/F

3.3.1

Audio CODEC Characteristics The Audio CODEC uses the SPI interface for control and uses a four wire serial interface for transfer of the digital audio to the DSP. The clock input to the CODEC is a direct coupled sinusoidal signal from CLK_IN (or may be a CMOS square wave from CLK_IN with a duty cycle of 40/60 or better) which should always be on unless the CODEC core is reset or powered down. If CDC_EN is low and AD_EN is low then the slicer on CLK_IN is disabled. CLK_IN is divided within GCAP II to generate the DCLK signal. DCLK is divided within GCAP II to generate the FSYNC signal. The input clock and division rates are selected by the CODEC control bits as defined below. In all cases CLK_IN, FSYNC, and DCLK are derived from the same reference. If DCLK0-2 is set to 000 then FSYNC and DCLK are accepted as inputs from the external device connected to the serial interface. The IC will power up to this default state. CODEC Control Bit Definition (All are R/W except as noted.)
Name DCLK CDBYP # of Bits 3 1 Description Selects the CODEC clock input and output frequencies A logic high routes the ADC input to the DAC output and powers down the CODEC core. In this mode CLK_IN does not need to be present, and CDC_EN needs to be programmed high. A logic high inverts the serial interface clock (IN or OUT) A logic high inverts the frame sync (IN or OUT) DF_RESET resets the digital filter in the CODEC. (Write only) A logic high enables the CODEC, logic low puts the CODEC in battery save mode. Power up default is 0.

CLK_INV FS_INV DF_RESET CDC_EN

1 1 1 1

For Kramer the CODEC bits described above should be set to power-up default state: all bits are zero.

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DCLK Bit Definition
DCLK2 0 0 0 0 1 1 DCLK1 0 0 1 1 0 0 DCLK0 0 1 0 1 0 1 CLK_IN 13MHz 13MHz 16.8MHz 19.44MHz 19.44MHz 8.4MHz Min Input 700mVp/p 700mVp/p 700mVp/p 1Vp/p 1Vp/p 700mVp/p FSYNC 8kHz(IN) 8kHz(OUT) 8kHz(OUT) 8kHz(OUT) 8.1kHz(OUT) 8kHz(OUT) DCLK 512kHz(IN) 200kHz(OUT) 200kHz(OUT) 360kHz(OUT) 202.5kHz(OUT) 200kHz(OUT)

The serial interface uses short frame sync. Data is transmitted and received in a two's compliment format. The FSYNC pin is held high for one falling DCLK edge. The PCM data word is output on the TX pin, beginning with the following rising edge of DCLK. Data is transmitted beginning with the MSB. Since the CODEC is 13 bits, the last three bits are zero. This results in the TX output going low impedance with the rising edge of FSYNC, and remaining low impedance until the middle of the MSB (16 and one half DCLK cycles). At power up the CODEC will release the TX line to be low impedance beginning with the third rising edge of FSYNC if DCLK[2:0] = 0. If any other DCLK mode is selected then GCAP II is the master of FSYNC and TX will be valid whenever an FSYNC occurs.
FSYNC [Input]

TX [DCLK=0]

Low Z

Low Z

FSYNC [Output]

TX [DCLK°0] Low Z Low Z Low Z Low Z

If FSYNC is high for one falling edge of DCLK, then GCAP II will start latching the 16 bit serial word into the receive data input on the following 16 falling edges of DCLK. GCAP will count the DCLK cycles and transfer the PCM data word to the D/A converter on the rising DCLK edge after the LSB has been latched. The timing diagram below summarizes the serial interface operation.

FSYNC DCLK TX RX X 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 Don' t 15 14 13 12 11 10 9 8 7 6 5 4 3 X X X Care Don' t Care

3.4

SPI Programming Interface

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3.4.1 SPI Pin Description:

Revision 1.54

SPI_DW: serial data input line. SPI_DR: serial data output line. CLK: clock input line, data shifting occurs at the rising edge of this signal. CE: clock enable line, active high. Note that data is latched into GCAP II after the last valid bit of the addressed register has been loaded. GCAP II does NOT latch data on the falling edge of CE. For example, if address is 010 then after bit 13 is loaded the data will latch and the remaining bits of the field are ignored. If the address is 111 then after bit 25 is loaded the data will latch. GCAP II is actually composed of two die. In one packaging option these two die are packaged separately. In this situation the two ICs can run SPI independently. If they are packaged together the interconnect is as shown below. SPI_DW, CLK, and EN are connected in parallel HRXD daisy chains to the CMOS IC before routing out as SPI_DR.
SPI SPI _D _D W R

Chip#1 (BiCMOS)

CL EN K

Chip #2 (CMOS)

1 HRXD 0 1 2 3 4 5 6 7

3.4.2.

SPI Operation Requirements The maximum clock rate is recommended at 5MHz. All inputs have to be above 0.7*V2 for a logic 1 and below 0.3*V2 for a logic 0. Data are transmitted least significant bit first. Data from the next SPI segment is transmitted from the output of the read data string if excess clocks are received. 4) Data and SPI_CLK signals will be ignored as long as CE has been low (logic 0) for at least 5nsec. SPI_DR will be tri-stated if CE is programmed low. 5) CE should be active (logic 1) only during the serial data transmission. 6) All write data is sampled at the rising edge of the SPI_CLK signal. Transitions on SPI_DW occur at least 5ns after the rising edge of SPI_CLK and stabilize before the next rising edge of SPI_CLK. 7) All read data is updated at the falling edge of the SPI_CLK signal. Transitions on SPI_DR occur at least 5ns after the falling edge of SPI_CLK and stabilize before the next falling edge of SPI_CLK. 8) CE has to be active (logic 1) at least 10nsec before the rising edge of the first SPI_CLK signal, and has to remain active (logic 1) at least 10nsec after the last rising edge of SPI_CLK. The recommended time interval for both cases is half a clock cycle. CE must remain inactive (logic 0) for at least 30nsec to latch in the data. 9) Coincident rising or falling edges of SPI_CLK and CE are not allowed. If the SPI_CLK signal is to be held at a logic 1 after the data transmission, the falling edge of the SPI_CLK signal must occur at least 5nsec. before CE becomes an active logic 1 for the next set of data. 10) If CE goes low before enough bits are sent then any write will be aborted. 1) 2) 3)

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3.4.3.

SPI Operation Description: The control bits are organized into 8 fields. Each of these fields may contain up to 32 bits. A maximum of 28 bits are used per field with the remaining four bits used to address the 8 fields and to inhibit writing if only a read from GCAP II is desired. For each SPI transfer, a one is written to the SPI_DW pin if this SPI transfer is to be a write. A zero is written to the SPI_DW pin if this is to be a read command only. If a zero is written, then any data sent after the address bits is ignored and the internal contents of the field addressed does not change when CE transitions from high to low. Next the three bit address is written to the SPI_DW pin LSB first. Finally, data bits are written to the SPI_DW pin LSB first. Once all the data bits are written then CE transitions from high to low to complete the SPI sequence. Note that not all bits are truly writeable. For instance, it does not make sense to write an interrupt. Refer to the individual subcircuit descriptions to determine the read write capability of each bit. To read a field of data, the SPI_DR pin will output the data field pointed to by the three address bits loaded at the beginning of the SPI sequence. Below is a diagram showing the details of an SPI transfer.
CE

SPI_CLK

SPI_DW

Write En

Address 0

Address 1

Address 2

Data 0

Data 1

Data 25

Data 26

Data 27

SPI_DR

Data 0

Data 1

Data 25

Data 26

Data 27

3.4.4

SPI Addressing Modes Three addressing modes are supported. Mode 1 is used in IC test. It allows continuous reading and writing of the SPI. Once the SPI address reaches 111 it rolls over to 000 and continues. Mode 2 is for normal radio operation. It allows reading SPI addresses one at a time. Mode 3 is a partial read mode. As many bits as desired can be read. If write is enabled then a write will occur once all valid bits of the addressed field have been loaded.

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1) Contiguous Read/Write CE Preamble SPI_DW First Address 28 Bits Data Next Address 28 Bits Data

Revision 1.54

SPI_DR

28 Bits Data

28 Bits Data

2) Register Read/Write CE Preamble SPI_DW First Address 28 Bits Data Preamble Another Address 28 Bits Data

SPI_DR

28 Bits Data

28 Bits Data

3) Partial Read CE Preamble SPI_DW First Address SPI_DR X Bits Data A write will occur if CE is high when the last valid bit of the addressed register is loaded.

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3.4.5
Address 000 Bit Name AUDOS1 AUDOS0 A2ON V1L VS1L SQP V2L2 V2L1 V2L0 V3L2 V3L1 V3L0 ENVR ENV1 STVR STV1 SWMB2 SWMB1 SWMB0 SWMA2 SWMA1 SWMA0 STSKA STSKB ENSKA ENSKB A1CRTL

SPI Data Structure:
Address 001 Bit Name LOST LOSTC TODAI TODAM 1HZI 1HZM 3SECI 3SECM ONOFFI ONOFFM ONOFF2I INT/EXTI INT/EXTM PWRONI PWRONM OVERI OVERM MOBPORTI MOBPORTM ONOFFSNS ONOFFSNS2 MOBSENSB PWRONSNS INTEXTSNS Address 010 Bit Name UNUSED MUTE1 MUTE_EN EXT_CLK AUX_LSEN MONITOR CH_EN LIADC PA_ON2 PA_ON1 PA_B3 PA_B2 PA_B1 PA_B0 TX_EN AUX_EN MAIN/AUX CHECK IDH0 IDH1 IDH2 PCEN Address 011 Bit Name TODA16 TODA15 TODA14 TODA13 TODA12 TODA11 TODA10 TODA9 TODA8 TODA7 TODA6 TODA5 TODA4 TODA3 TODA2 TODA1 TODA0 Address 100 Bit Name TOD16 TOD15 TOD14 TOD13 TOD12 TOD11 TOD10 TOD9 TOD8 TOD7 TOD6 TOD5 TOD4 TOD3 TOD2 TOD1 TOD0 Address 101 Bit Name ST4 ST3 ST2 ST1 ST0 DAY14 DAY13 DAY12 DAY11 DAY10 DAY9 DAY8 DAY7 DAY6 DAY5 DAY4 DAY3 DAY2 DAY1 DAY0 IDJ0 IDJ1 IDJ2 Address 110 Bit Name DWNEN DSCEN DF_RESET AUDOHP ADITH AUDOG2 AUDOG1 AUDOG0 ALM AUDIHP AUDIS1 AUDIS0 AUDIG3 AUDIG2 AUDIG1 AUDIG0 FS_INV CLK_INV CDBYP DCLK2 DCLK1 DCLK0 CDC_TEST3 CDC_TEST2 CDC_TEST1 CDC_TEST0 CDC_EN Address 111 Bit Name ATO3 ATO2 ATO1 ATO0 ADEN ASC DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 ADA3 ADA2 ADA1 ADA0

Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

3.4.6

SPI Initial Conditions: The following is a list of initial states for the data bits which need initial states. GCAP II Pass 2.7
SQP ENSKB ENVR V2L1 DCLK1 FS_INV ALM ASC DAC5 DAC1 CH_EN PA_ON2 DSCEN 1HZM OVERM AUX_EN CDC_TEST0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 STSKA STV1 VS1L V2L2 DCLK2 DF_RESET AUDOS0 ADEN DAC4 DAC0 MONITOR MUTE_EN DWNEN TODAM ONOFFM CDC_TEST3 CDC_EN 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 STSKB STVR V1L A2ON CDBYP AUDIS0 AUDOS1 DAC7 DAC3 EN LIADC MUTE1 EXT_CLK PWRONM MOBPORTM CDC_TEST2 A1CRTL 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ENSKA ENV1 V2L0 DCLK0 CLK_INV AUDIS1 ADITH DAC6 DAC2 LOSTC PA_ON1 MUTE2 3SECM INTEXTM TX_EN CDC_TEST1 CHECK 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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GCAPII Pass 3.0 initial state changes
AUX_LSEN PA_B1 AUDIHP 0 0 0 PA_ON2 PA_B0 EN 1 PA_B3 0 PCEN deleted 1 0 PA_B2 AUDOHP 1 0

Note: The above table lists the additions to the GCAPII pass 2.7 initial state table. Also the EN bit no longer exists

3.4.7 SPI programming requirements Address 000 Initial State Label Initial state pass 3.0 AUDOS1 0 AUDOS0 0 A2 ON 0 V1L 0 VS1L 0 SQP 0 V2L2 0 V2L1 0 V2L0 0 V3L2 0 V3L1 0 V3L0 0 ENVR 1 ENV1 1 STVR 1 STV1 0 SWMB2 1 SWMB1 0 SWMB0 0 SWMA2 1 SWMA1 1 SWMA0 0 STSKA 0 STSKB 0 ENSKA 0 ENSKB 0 A1 CRTL 0 0 0

Bit# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

The initial state of address 000 is dependent on the configuration of three hardware pins (PGM2, PGM1, and PGM0) see section 3.1.1 for state definitions. The above table defines the initial states for Kramer as of 8/10/98. These pins predetermine the states for switching supplies PWM1, PWM2 and LDO supply V3. Care must be taken when writing to these bits if the new state causes a hardware conflict the part may power down or damage itself. Bits 16-18 control PWM2 and Bits 19-21 control PWM1. The PWMs are supplies for the linear regulators therefore the PWM must not be programmed lower than the voltage the linear regulator is programmed to regulate to. Likewise the linear regulators which are controlled by bits 3,4,6-15 must not be

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programmed to regulate a voltage higher than that which it is supplied with. The linear regulator must be powered down before or simultaneously with the PWM feeding it. Address 000 register after SW Init. Label SW Init. state pass 3.0 with V3 @ 2.0V AUDOS1 0 AUDOS0 0 A2 ON 0 V1L 1 VS1L 1 SQP 0 V2L2 0 V2L1 0 V2L0 0 V3L2 0 V3L1 0 V3L0 0 ENVR 1 ENV1 1 STVR 1 STV1 0 SWMB2 1 SWMB1 1 SWMB0 1 SWMA2 1 SWMA1 1 SWMA0 0 STSKA 0 STSKB 0 ENSKA 0 ENSKB 0 A1 CRTL 0 0 0

Bit#

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

The above table lists the state that address 000 should be programmed to after reset for GCAP II. Kramer currently only uses the boost PWM supply therefore the buck PWM should be turned off. This should be performed as soon as possible. Care should be taken not to turn the buck PWM back on during a subsequent write. Note that the CHECK bit in address 010 must be set to 1 to change the switcher and regulator settings.

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Address 010 Register after SW Init. Label SW Init. state pass 3.0 with V3 @ 2.0V UNUSED 0 MUTE1 0 MUTE_EN 0 EXT_CLK 1 AUX_LSEN 1 MONITOR 0 CH_EN 0 LIADC 1 PA_ON2 1 PA_ON1 0 PA_B3 0 PA_B2 0 PA_B1 0 PA_B0 1 TX_EN 0 AUX_EN 1 MAIN/AUX 0 CHECK 1 IDH0 X IDH1 X IDH2 X PCEN 1

Revision 1.54

Bit#

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

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3.5

A/D and D/A Read and write operations will be accomplished through the SPI bus. The DAC can be set by writing to DAC[7:0]. All zeros is the low power state. The DAC output is internally fed to the battery charger circuit and is not directly available at any output pin. The charger within GCAP II is not used in Kramer. (See 3.6 Battery Charger Operation) The ADC is 8 bits with 10 inputs. CLK_IN must be present when using the A/D converter. Input address 7 (ADA[3:0] = 0111) is internally connected to the output of BATSENSE. Input address 8 (ADA[3:0] = 1000) is internally connected to the output of B+SENSE. Input address 9 (ADA[3:0] = 1001) is internally connected to the output of AUX_SENSE. Input address 6 (ADA[3:0] = 0110) has a high input impedance buffer and is internally connected to LI_CELL. These inputs are not directly accessible at any output pin. The other 6 A/D inputs are available as AD0 through AD5. The ADC will have the ability to execute a conversion in two ways: Enable the conversion with the Start Convert (ASC) bit. Enable the conversion with the rising edge of the ADTRIG signal.

1) 2)

In both of the above cases the conversion will begin after a delay set by the ATO register. This register will be 4 bits long and will be driven by CLK_IN/256. Once conversion is initiated all 10 channels will be sequentially converted and stored in registers. This is shown in the diagram below. The signals labels SC0-2 refer to the interdie connections to control the SNS_OUT addressing.
ASC ATO ADA AD0 Read AD1 Read AD2 Read AD3 Read AD4 Read AD5 Read LI_CELL Read BATSENSE Read B+SENSE Read AUX_SENSE Read SNS2 SNS1 SNS0 0 1 2 3 4 5 6 7 8 9

To convert multiple channels starting the conversion with the SC bit, the following steps are executed:

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1) 2) 3) 4) 5) 6)

Revision 1.54

Enable A/D. (ADEN=1) Start conversion at channel 0 by writing a 1 to the start conversion bit. (ASC) The conversion will begin once ATO counts down to zero. Wait for completion. (ASC will reset to zero when complete.) Write the result address. (ADA[3:0]) Note that it is possible to write the starting address of the next SPI read while reading out the present data. Read conversion values. Repeat steps 5 and 6 for all channel results.

To convert multiple channels starting the conversion with the rising edge of ADTRIG, the following steps are executed: 1) Enable A/D. (ADEN=1) 2) The conversion will automatically start at channel 0 once ATO counts down to zero. 3) Wait for completion. (ASC will reset to zero when complete.) 4) Write the result address. (ADA[3:0]) Note that it is possible to write the starting address of the next SPI read while reading out the present data. 5) Read conversion values. 6) Repeat steps 5 and 6 for all channel results. A/D and D/A Bits Definition (all are R/W)
Name ASC ADEN ADA[3:0] ADD[7:0] DAC[7:0] ATO[3:0] # of Bits 1 1 4 8 8 4 Description Logic high starts A/D conversion. This bit will self clear when the conversion is complete. Logic high enables the A/D converter. Selects the results register read when reading the A/D data. The value of the last conversion for the channel selected by ADA[3:0]. Read only. Data used for the D/A conversion. A read of this register is used for testing purposes. Delay from the A/D trigger event until conversion begins.

3.6

3.6

Battery Charger Operation

The GCAP II IC contains an on-board rapid charger, whose charge capability is controlled by an on board D/A. The GCAP II monitors battery voltage and the call processor monitors battery type in order to determine the manner in which to charge the battery. The GCAP II contains an error amplifier and a feedback amplifier. An external pass device (FET) and sense resistor account for the remainder of the charge circuit. External connections for the charger on the GCAP include ISENSE, CHRGC.

3.6.1

ISENSE

ISENSE is an input for measuring the voltage across the external sense resistor (0.24 ohm). The voltage difference measured is fed to the feedback amp in GCAP II.

3.6.2

CHRGC

CHRGC is an output from the internal error amplifier that drives the gate of the external FET accordingly. The FET passes current from EXT_B+ to the battery to be charged. The following table shows the relationships between the D/A counts and charger capability.

D/A Code 0

I BATT 0 OFF

Comment

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10 21 128 255

Still may be OFF ON 480mA ±50mA 1.000A±100mA Full Scale

3. 7 3.7.1

A/D Thresholds B+

Lithium ion thresholds
Description Standby: Software Shutdown Standby: Battery Bar 1 Off Standby: Battery Bar 2 Off Standby: Battery Bar 3 Off Transmit: Software Shutdown Transmit: Battery Bar 1 Off Transmit: Battery Bar 2 Off Transmit: Battery Bar 3 Off Vb+sense=(( B+)-1.98)*0.55 Voltage 2.85 3.5 3.65 3.8 2.85 3.05 3.2 3.4 A/D 49 85 94 102 60 68 80 28 HEX 31 55 5E 66 3C 44 50 1C

3.7.2

BATT+
Description Battery Minimum Battery Maximum Vbattsense=(( BATT)-1.33)*0.60 Voltage TBD TBD Scaled Voltage TBD TBD A/D TBD TBD HEX TBD TBD

3.7.3
NO BAT -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20

Thermistor (AD2)
DAC value 255 255 255 255 255 255 249 240 229 217 203 188 173 157 HEX FF FF FF FF FF FF F9 F0 E5 D9 CB BC AD 9D infinity 336.6 242.8 177 130.4 97.12 72.98 55.34 42.34 32.66 25.4 19.9 15.71 12.49 2.75 2.695 2.665 2.627 2.577 2.516 2.441 2.35 2.245 2.125 1.991 1.847 1.696 1.541

Temp( C) Rth(Dale) V(NTC)

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25 30 35 38 40 45 50 55 60 65 70 75 80 10 8.06 6.53 5.88 5.33 4.37 3.6 2.99 2.49 2.08 1.75 1.48 1.26 1.388 1.238 1.096 1.0229 0.964 0.844 0.735 0.639 0.553 0.478 0.413 0.358 0.31 142 126 112 104 98 86 75 65 56 49 42 36 32 8E 7E 70 68 62 56 4B 41 38 31 2A 24 20

Revision 1.54

3.7.4 DOWNLINK (AD4) DSC Downlink Typical 5 22000 Max 5.15 24420 Min 4.85 19580 95000 95000

V1 R1 +/5% R2 +/5% R3 +/5%

100000 105000 100000 105000

Accesso Pull Down resistor ry R4 Type Typical Max Min - Typica +5% 5% l NONE DHFA Data 3.7.5 none 56000 22000 None 58800 23100 none 2.252

A/D voltage Max Min Typical

DAC value Max

DAC Min ranges

2.463 1.896 1.393

2.053 1.451 1.003

230 170 121

251 193 142

209 148 102

201 145 <145

53200 1.663 20900 1.185

DSC_EN (AD3)

DSC_EN Definitions Typical 5 10000 Max 5.15 10500 Min 4.85 9500 95000 95000 139650

V1 R1 +/5% R2 +/5% R3 +/5% R5 +/5%

100000 105000 100000 105000 147000 154350

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Accesso ry Type Typical

Pull Down resistor A/D voltage R4 Max Min -5% Typi Max Min +5% cal None 23100 23100 none 20900 20900 2.24 2.44 1.59 1.77 1.59 1.77 2.04 1.40 1.40

Typical

DAC value Max

DAC Min ranges

IGN Low IGN Hi Data

none 22000 22000

228 162 162

249 180 180

208 143 143

194 138 138

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3.7.6 MAN_TEST (AD5)

Revision 1.54

MAN_TEST Definitions Typical Max 2.775 2.85 10000 10500 Min 2.7 9500

V1 R1 +/5%

Accesso ry Type Typical

Pull Down resistor R4 Max Min +5% 5% none none

A/D voltage Typical Max Min Typical

DAC value Max

DAC Min ranges

NONE

none

2.775

2.85

2.7

255

255

255

250

FAST CHRG Off hk MID CHRG off hk

33000

34650

31350

2.130

2.237

2.023

217

228

206

180

10000

10500

9500

1.388

1.496

1.283

142

153

131

102

FAST CHRG On hk

33K || 3.3K 3000

below 3150 2850 0.640 0.710 0.576 65 72 59 102

Note: Software uses MAN_TEST in a test mode if MAN_TEST is grounded.

3.8 RTC Module
The RTC module is contained in GCAP2. Its power source is hardware-switched between an internal supply and an external rechargeable (secondary) battery. The charge circuit for the battery is internal to GCAP and is switched on and off via SW control. The module counter uses an external 32.768khz xtal. The RTC in the first phase of Kramer will be similar to the StarTac implementation, in that only hours and minutes will be displayed. The format will be user selectable in 12-hour or 24-hour mode. The time will be displayed in the graphics area of the LCD. In StarTac it was displayed as a separate icon. The time will be displayed after the wake-up message has terminated and until the user presses a key or goes into the menu. Once the user has cleared the display (ended a call, exited menus, clearing key presses) the time will reappear in the display. The graphical size of the digits is in the marketing requirements document. The voltage of the rechargeable battery will be read using the Li_Sense A/D in GCAP. The formula for the Li_Sense is (Li_Cell-0.93)*0.70, where Li_Cell is the battery voltage.

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When Li_Cell discharges to a voltage of 2.3V the charger should be switched on and remain on until Li_Cell reaches a voltage of 2.8V, at which point it is switched off. Li_Cell Voltage 2.8V 2.3V DAC Value 133 100

The rechargeable battery can and will be charged off of any power source (main battery, CLA, etc). There is no phasing requirement for the secondary cell.

4 WHITECAP LOGIC INTERFACES
4.1 DSC Module The DSC module implements the GSM Data Speech Control interface in the Whitecap IC. It accepts manchester encoded data input on the DSC bus and generated manchester coded data onto the DSC bus. DSC data may be transmitted to or received from the TI LEAD megamodule or TI ARM megamodule via the XIO interface and PIF interface, respectively. The PIF interface also provides control of the DSC module. The DSC module generates a clock and frame sync to the audio codec interface. The frame sync is synchronized so the DSC LEAD interrupt occurs at the same time as the Audio CODEC interrupt. An ARM interrupt is generated to synchronize the ARM megamodule to the DSC interrupt. The DSC time slots are the basic data structures in the DSC module. The function of the DSC is to transmit and receive DSC frames on the DSC bus. These frames may come from or be sent to the Lead DSP Audio Coder XIO port, the ARM Call Processor PIF port, or the Manchester coded DSC bus. The DSC module in Whitecap operates only in the Master mode at a controllable bit rate of 128kHz or 512kHz. The audio CODEC clock always operates at 512Khz. Switching the DSC from 128kHz to 512kHz is held off until DSC time slot boundaries. This functionality is changed from BIC 4.X for the Whitecap DSC module to accommodate the CODEC interface and synchronization for the Lead DSP.

4.2 UART - RS232 The UART is based upon a TL16C550 compatible UART. It is used to communicate serially over an RS232 interface. Refer to TI document BRK_UART ver: 1.1 for detailed information. The module sends and receives characters of 8bits. The number of stop bits can be programmed to 1 or 2. Parity can be programmed to even, odd, or disabled completely. The module contains a 32 deep FIFO for the received characters and a 16 deep FIFO for transmit. It generates its own baud rate based upon a programmable divisor and its input clock. 4.2.1 BATTERY SERIAL DATA COMMUNICATION (development board only) Kramer will not support this feature. The feature is used to communicate via the UART interface with the serial ROM inside the "Smart" battery (Lithium-Ion). This port is also used to read data contained in a serial ROM device like the Dallas DS2401 integral part of the security scheme implemented in other DCS phones design.

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4.3 SIM INTERFACE

Revision 1.54

The SIM Interface is a peripheral in the Whitecap Chip that allows the ARM Core to communicate with pre-paid cards or SIM cards. It communicates with the ARM via the 16-bit internal Peripheral Bus. The SIM interface contains 2 ports, one allowing synchronous or asynchronous (pre-paid cards) serial transmission and the other allowing only asynchronous serial transmission.

4.3.1 GCAPII / SIM CARD INTERFACE Kramer can support both 3V and 5V SIM Cards. GCAP II contains level shifters that can translate 5V logic down to 3V. If a 3V SIM card is present it will merely be buffered through to Whitecap. SIM Card Block RESET - Input to SIM Card CLOCK - Input to SIM Card SIMPD - Output to WCP SIM I/O Input/Output VCC VPP Table X. GCAPII - SIM CARD INTERFACE GCAP II Level Shifter Input LS2_INTG1A, ball K7 LS1_IN, ball G6 GCAP II Level Shifter Output LS2_OUT_TG1, ball J7 LS1_OUT, ball F6 Comments

3.25 Mhz provided by WCP

SIMI_O, ball J8

LS3_TX and LS3_RX, balls K10 and H8 VSIM1, 5.0V VSIM1, 5.0V

The phone will always assume that it is talking to a 5 volt SIM card since 3 volt SIM cards are required to operate at 5 volts. This way on power up, VSIM is programmed to 5 volts. RESET and CLOCK will come from Whitecap at 3 volts and be level translated to 5 volts in GCAP II before being sent to the card. SIM I_O is a serial data communication line that is connected in a wired-or configuration.

4.3.2 GCAPII / WHITECAP INTERFACE The Whitecap chip SIM Peripheral contains a UART and a Synchronous Transceiver. Control bits are set through the ARM interface and control the overall function of the SIM interface for both the UART and the Synchronous Transceiver. The control registers control operation of mode, baud rate, enables, status, interrupt conditions, and interrupt masks. SIM auto power down and presence detect are also handled by writing and reading SIM registers. Kramer will operate using a SIM in asynchronous mode (Port 1). This will be the default normal operation for the phone.

4.3.3 SIM CLOCK The SIM peripheral receives a 13 Mhz clock. Within the module, this clock is divided down in frequency for the respective transceivers. For the synchronous SIM, clocks are generated to provide a 13 Mhz "divide_by_32" and 3.25 Mhz "divide_by_8" clock. The clock derivatives are controlled by the Control Register Setting (CSRC). Within the synchronous transceiver, both of these clocks are further divided down

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by 40 before being sent to the SIM card. This clock is approximately 13 kHz. Internally, the SIM also requires a 13 Mhz "divide_by_2" and a 3.25 Mhz "divide_by_2". For the asynchronous SIM, the clock generated and sent to the SIM card is basically a 13 Mhz or 3.25 Mhz clock (Again, chosen according to the setting of Control Register CSRC). For port 1, which only allows asynchronous operation, the clock to the card is this system clock. For port 2, the clock may be either Synchronous or Asynchronous depending on the type of SIM card connected to the port (Determined by control register settings). Internally, the asynchronous SIM receive and transmit functions will use clocks that are selected by the baud rate.

4.3.4 Synchronous Transceiver (Kramer will not support this feature) The synchronous transceiver' function is to communicate with a pre-paid card. The pre-paid card requires s different modes of operation. These modes are defined sequences that the interface must follow. The modes include reset, read, and special writes. Control bits are used to control the state machine that implements the required transitions for these modes. Refer to SIM Interface Specification pp. 6 - 15 for more detailed information regarding the Synchronous Transceiver.

4.3.5 UART The SIM UART consists of a receiver, transmitter, special logic to detect auto power down of ports, and sim card presence detection. It facilitates transmitting and receiving data with a SIM card. The asynchronous SIM card interface does not have the same type of modes that the Synchronous transceiver has. In the UART, the "mode" is a baud rate that can be selected for the receive and transmit. The SIM UART baud rate selector provides different sampling rates for the transmitter and receiver. Based on the selected baud rate, the receiver will serially receive data from the SIM card and collect the data in a pre-defined fifo queue. Also, for the selected baud rate the transmitter accepts data loaded into a shift register and serially transmits data to the SIM card. The receive and transmit functions include parity checking, interrupt generation, and interrupt enables. The data to be transmitted or received is