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To all our customers
Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp. Customer Support Dept. April 1, 2003
Cautions
Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
PF08114B
MOS FET Power Amplifier Module for E-GSM and DCS1800 Dual Band Handy Phone
ADE-208-1029B (Z) Rev.2 Dec. 2001 Application
· Dual band amplifier for E-GSM (880 MHz to 915 MHz) and DCS1800 (1710 MHz to 1785 MHz) · For 3.5 V nominal operation
Features
· 2 in / 2 out dual band amplifier · Simple external circuit including output matching circuit · Simple power control · 2stage amplifier : 10 dBm input Typ · Lead less thin & small package : 8 × 12.3 × 1.6 mm Typ · High efficiency : 54% Typ at 34.5 dBm for E-GSM : 52% Typ at 31.5 dBm for DCS1800
Pin Arrangement
· RF-K1-10
G7 6
98 10
5
34 2G 1
1: Pin GSM 2: Vapc 3: Vdd2 4: Pout GSM 5: GND 6: Pout DCS 7: Vdd1 8: Vband 9: Pin DCS 10: GND G: GND
PF08114B
Absolute Maximum Ratings
(Tc = 25°C)
Item Supply voltage Vapc voltage Input power Operating case temperature Storage temperature Symbol Vdd Vapc Pin Tc (op) Tstg Rating 7* 15 -25 to +100 -30 to +100
1 2
Unit V V dBm °C °C
4.3 *
Notes: 1. This value is specified at no operation. (Vapc = 0 V) 2. This value is specified at no operation. (Vdd = 0 V) At Vdd > 0, Vapc controlled, Idd = 0 to x A, where x = current at Pout = 34.5 dBm (@GSM), 31.5 dBm (@DCS), 50 Load, Vdd = 3.5 V and Tcase = 25°C
Electrical Characteristics for DC
(Tc = 25°C)
Item Drain cutoff current Symbol Ids Min Vapc control current Iapc Typ Max 10 500 3 Unit µA µA mA Test Condition Vdd = 4.5 V, Vapc = 0 V, Vband = 0 V Vdd = 4.5 V, Vapc = 0 V, Vband = 2 V Vdd = 3.5 V, Pin = 8 to 12 dBm, Pout = 34.5 dBm @GSM900 Pout = 31.5 dBm @DCS1800 Vapc controlled, Rg = Rl = 50
ESD Product quality guide level for ESD is 500 V at following test circuit.
10 M to 30 M High-voltage power supply
1500 Test pin (Bold line indicates the discharging transmission line) Sample 100 pF socket Common pin
Rev.2, Dec. 2001, page 2 of 15
PF08114B
Electrical Characteristics for E-GSM mode
(Tc = 25°C)
Test conditions unless otherwise noted:
Vdd1 = Vdd2 = 3.5 V, Pin = 8 to 10 dBm, Vband = 0 V, Rg = Rl = 50 , Tc = 25°C, Pulse operation with pulse width 577 µs and duty cycle 1:8 shall be used.
Item Frequency range Band select (GSM active) Input power Supply voltage Total efficiency 2nd harmonic distortion 3rd harmonic distortion Input VSWR Output power (1) Output power (2) Isolation Isolation at DCS RF-output when GSM is active Switching time Stability Symbol f Vband Pin Vdd T 2nd H.D. 3rd H.D. VSWR (in) Pout (1) Pout (2) Min 880 0.0 8 2.9 45 34.5 32.9 Typ 10 3.5 54 -50 -50 1.5 35.0 33.5 -40 -30 Max 915 0.2 12 4.5 -41.5 -41.5 3 -25 -20 Unit MHz V dBm V % dBc dBc dBm dBm dBm dBm Vapc = 2.2V Vdd = 2.9V, Vapc = 2.2V, Tc = +90°C Vapc = 0.2 V, Pin = 12dBm Pout GSM = 34.5dBm, Measured at f = 1760 to 1830MHz Pout GSM = -10 to 34.5dBm, t = 90% All combinations of the following parameters: Vapc controlled *1, Pin = min to max, Vdd = 2.9 to 4.5V, Tcase = -20 to 90°C, Load VSWR = 7.5 : 1, All phase angles All combinations of the following parameters: Vapc controlled *1, Pin = min to max, Vdd = 2.9 to 4.5V, Tcase = -20 to 90°C, Load VSWR = 7.5 : 1, All phase angles Pout GSM = 34.5dBm, Vapc = controlled Test Condition
t r, t f
1
2
µs
No parasitic oscillation > -36 dBm
Load VSWR tolerance
No degradation
Note:
1. Id = 0 A to x A, where x = current at Pout = 34.5 dBm, 50 load, Vdd = 3.5 V and Tcase = 25°C. Vapc can range from 0.2 V to 4.3 V to control Idd.
Rev.2, Dec. 2001, page 3 of 15
PF08114B
Electrical Characteristics for DCS1800 mode
(Tc = 25°C)
Test conditions unless otherwise noted:
Vdd1 = Vdd2 = 3.5 V, Pin = 8 to 10 dBm, Vband = 2 V, Rg = Rl = 50 , Tc = 25°C, Pulse operation with pulse width 577 µs and duty cycle 1:8 shall be used.
Item Frequency range Band select (DCS active) Input power Supply voltage Total efficiency 2nd harmonic distortion 3rd harmonic distortion Input VSWR Output power (1) Output power (2) Isolation Switching time Stability Symbol f Vctl Pin Vdd T 2nd H.D. 3rd H.D. VSWR (in) Pout (1) Pout (2) t r, t f Min 1710 1.9 8 2.9 45 31.5 30.0 Typ 10 3.5 52 -50 -50 1.5 32.5 31.0 -42 1 Max 1785 2.9 12 4.5 -38.5 -38.5 3 -36 2 Unit MHz V dBm V % dBc dBc dBm dBm dBm µs Vapc = 2.2V Vdd = 2.9V, Vapc = 2.2V, Tc = +90°C Vapc = 0.2 V Pout DCS = -10 to 31.5dBm, t = 90% All combinations of the following parameters: Vapc controlled *1, Pin = min to max, Vdd = 2.9 to 4.5V, Tcase = -20 to 90°C, Load VSWR = 7.5 : 1, All phase angles Pout = 31.5dBm, Pinterferer at output, Fo + 3MHz at -11.5dBm, Measure Fo - 3MHz, RBW = 300kHz All combinations of the following parameters: Vapc controlled *1, Pin = min to max, Vdd = 2.9 to 4.5V, Tcase = -20 to 90°C, Load VSWR = 7.5 : 1, All phase angles Pout DCS = 31.5dBm, Vapc = controlled Test Condition DCS1800 (1710 to 1785MHz)
No parasitic oscillation > -36 dBm
Intermodulation
-59
-52
dBc
Load VSWR tolerance
No degradation
Note:
1. Id = 0 A to x A, where x = current at Pout = 31.5 dBm, 50 load, Vdd = 3.5 V and Tcase = 25°C. Vapc can range from 0.2 V to 4.3 V to control Idd.
Rev.2, Dec. 2001, page 4 of 15
PF08114B
Internal Diagram and External Circuit
Pin 9 Pin DCS Pin 1 Pin GSM Pin 6 Pout DCS Pin 4 Pout GSM
Z1
Z2 Pin 2 Vapc
Bias circuit Pin 8 Vband Pin 7 Vdd1 Pin 3 Vdd2 C1 C3 FB C4 FB C5 FB C6 FB C2
Z3
Z4
Pin DCS
Pin GSM
Vapc
Vband
Vdd1
Vdd2
Pout GSM Pout DCS
C1 = C2 = 10 µF TANTALUM ELECTROLYTE C3 = C4 = 1000 pF CERAMIC CHIP C5 = C6 = C7 = 10000 pF CERAMIC CHIP FB = FERRITE BEAD BLO1RN1-A62-001 (Manufacture: MURATA) or equivalent Z1 = Z2 = Z3 = Z4 = 50 MICROSTRIP LINE
Rev.2, Dec. 2001, page 5 of 15
PF08114B
Test Fixture Pattern
Top View
1 4 4.8 1 6 0.6 1.6 2.5
42 1 6 4 1 6 1
3
12.7 1.575 15.525 2.5 1.35 0.6 1.4 1.6 0.2 3.85 0.6 1.6 0.6 1.4 0.525 1.35 2 6.775 1.350 1.575
2 1 40 3 1 3 1.5 1.5 0.525 3 3 9.55 7.55
6.775 1.575 1.350 1.575 15.525
0.6 0.925 1.35
Bottom View
42 0.5 4.8 0.5
0.5 2.5 0.5
3.6 1.575 1.350 1.575 15.525 8.125 6.775 1.4 1.35 40 0.5 0.5 1.4 0.525 1.7 2.0 1.4 2.5 0.5 1.2 0.5 16.875 15.9 11.4
0.5 1.0 2.1 0.5 1.4 1.4 1.35 0.6 0.525 6.775 15.525 16.875 1.575 1.350 1.575 1.7
3.95 1.4 0.5 1.4 1.7 1.4 1.4 1.4 0.5
Scale: 1/1 Grass Epoxy Double sided P.C.B (t = 1.6 mm, r = 4.8)
Unit: mm
Rev.2, Dec. 2001, page 6 of 15
PF08114B
Characteristic Curves
GSM mode (880 MHz) Pout, Eff vs. Vapc 40 Pout Efficiency Vdd = 3.5 V, Vband = 0 V, Pin = 10 dBm, Tc = 25°C, Rg = Rl = 50 60
20
50
0
40
-20
30
-40
20
-60
10
-80 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Vapc (V) 1.6 1.8 2.0
0 2.2
GSM mode (915 MHz) Pout, Eff vs. Vapc 40 Pout Efficiency Vdd = 3.5 V, Vband = 0 V, Pin = 10 dBm, Tc = 25°C, Rg = Rl = 50 60
20
50
0
40
-20
30
-40
20
-60
10
-80 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Vapc (V) 1.6 1.8 2.0
0 2.2
Rev.2, Dec. 2001, page 7 of 15
Efficiency (%)
Pout (dBm)
Efficiency (%)
Pout (dBm)
PF08114B
DCS mode (1710 MHz) Pout, Eff vs. Vapc 40 Pout Efficiency Vdd = 3.5 V, Vband = 2 V, Pin = 10 dBm, Tc = 25°C, Rg = Rl = 50 60
20
50
0
Pout (dBm)
40
Efficiency (%) Efficiency (%)
-20
30
-40
20
-60
10
-80 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Vapc (V) 1.6 1.8 2.0
0 2.2
DCS mode (1785 MHz) Pout, Eff vs. Vapc 40 Pout Efficiency Vdd = 3.5 V, Vband = 2 V, Pin = 10 dBm, Tc = 25°C, Rg = Rl = 50 60
20
50
0
Pout (dBm)
40
-20
30
-40
20
-60
10
-80 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Vapc (V) 1.6 1.8 2.0
0 2.2
Rev.2, Dec. 2001, page 8 of 15
PF08114B
GSM mode (880 MHz) Pout vs. Pin 37 Vapc = 2.2 V, Vband = 0 V, Rg = Rl = 50 36
Pout (dBm)
35
34
33
2.9 V, 25°C 3.5 V, 25°CPout(1) 2.9 V, 90°CPout(2) 3.5 V, 90°C 0 2 4 6 8 Pin (dBm) 10 12 14
32
GSM mode (915 MHz) Pout vs. Pin 37 Vapc = 2.2 V, Vband = 0 V, Rg = Rl = 50 36
Pout (dBm)
35
34
33
2.9 V, 25°C 3.5 V, 25°CPout(1) 2.9 V, 90°CPout(2) 3.5 V, 90°C 0 2 4 6 8 Pin (dBm) 10 12 14
32
Rev.2, Dec. 2001, page 9 of 15
PF08114B
DCS mode (1710 MHz) Pout vs. Pin 34 Vapc = 2.2 V, Vband = 2 V, Rg = Rl = 50 33
Pout (dBm)
32
31
30
2.9 V, 25°C 3.5 V, 25°CPout(1) 2.9 V, 90°CPout(2) 3.5 V, 90°C 0 2 4 6 8 Pin (dBm) 10 12 14
29
DCS mode (1785 MHz) Pout vs. Pin 34 Vapc = 2.2 V, Vband = 2 V, Rg = Rl = 50 33
Pout (dBm)
32
31
30
2.9 V, 25°C 3.5 V, 25°CPout(1) 2.9 V, 90°CPout(2) 3.5 V, 90°C 0 2 4 6 8 Pin (dBm) 10 12 14
29
Rev.2, Dec. 2001, page 10 of 15
PF08114B
GSM mode Pout(1) vs. Vdd 40 f = 880 MHz f = 915 MHz Vapc = 2.2 V, Vband = 0 V, Pin = 10 dBm, Tc = 25°C, Rg = Rl = 50
39
38
Pout(1) (dBm)
37
36
35
34 3.0
3.5
4.0 Vdd (V)
4.5
5.0
5.5
DCS mode Pout(1) vs. Vdd 37 f = 1710 MHz f = 1785 MHz Vapc = 2.2 V, Vband = 0 V, Pin = 10 dBm, Tc = 25°C, Rg = Rl = 50
36
35
Pout(1) (dBm)
34
33
32
31 3.0
3.5
4.0 Vdd (V)
4.5
5.0
5.5
Rev.2, Dec. 2001, page 11 of 15
PF08114B
GSM mode Efficiency vs. Pout 70 f = 880 MHz f = 915 MHz Vdd = 3.5 V, Vband = 0 V, Pin = 10 dBm, Vapc = control, Tc = 25°C, Rg = Rl = 50
60
50
Efficiency (%)
40
30
20
10
0 20
25
30 Pout (dBm)
35
40
DCS mode Efficiency vs. Pout 70 f = 1710 MHz f = 1785 MHz Vdd = 3.5 V, Vband = 0 V, Pin = 10 dBm, Vapc = control, Tc = 25°C, Rg = Rl = 50
60
50
Efficiency (%)
40
30
20
10
0 20
25
30 Pout (dBm)
35
40
Rev.2, Dec. 2001, page 12 of 15
PF08114B
GSM mode Pout(1) vs. Frequency 37 Vdd = 3.5 V, Vapc = 2.2 V, Vband = 0 V, Tc = 25°C, Rg = Rl = 50 36
Pout (dBm)
35
34 GSM
33 800
850
900 Frequency (MHz)
950
1000
DCS mode Pout(1) vs. Frequency 35 Vdd = 3.5 V, Vapc = 2.2 V, Vband = 0 V, Tc = 25°C, Rg = Rl = 50 34
Pout (dBm)
33
32 DCS
31 1650
1700
1750 Frequency (MHz)
1800
1850
Rev.2, Dec. 2001, page 13 of 15
PF08114B
Package Dimensions
Unit: mm
9 8 G 7 6
1.6 - 0.2
+ 0.1
8.0 ± 0.3 7.8
10
5
1
2 G 3 (Upper side)
4 G7 6
8.0 ± 0.3
98
12.3 ± 0.3 12.3 ± 0.3
(5.15) (5.15) (4.8) (4.8) (2.9) (2.9) (3.4) (1.4) (1.4) (2.5) (1.4)(1.4) (1.4) (1.4) (1.4) (1.0) (1.0)
5
10
34 2G 1
8.0 ± 0.3
(1.4)
(1.4)
(1.2) (0.7)
(2.6) (2.6)
1: Pin GSM 2: Vapc 3: Vdd2 4: Pout GSM 5: GND 6: Pout DCS 7: Vdd1 8: Vband 9: Pin DCS 10: GND G: GND
(3.0)
(3.0)
(2.4)
(2.4)
(2.4)
(Bottom side)
Remark: Coplanarity of bottom side of terminals are less than 0 ± 0.1mm.
Hitachi Code JEDEC JEITA Mass (reference value) RF-K1-10
Rev.2, Dec. 2001, page 14 of 15
PF08114B
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
http://www.renesas.com
Copyright © 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan.
Colophon 0.0
Rev.2, Dec. 2001, page 15 of 15