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To all our customers

Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com

Renesas Technology Corp. Customer Support Dept. April 1, 2003

Cautions
Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.

PF08107BP
MOS FET Power Amplifier Module for E-GSM and DCS1800 Dual Band Handy Phone

ADE-208-1399C (Z) Rev.3 Dec. 2001 Application
· Dual band amplifier for E-GSM (880 MHz to 915 MHz) and DCS1800 (1710 MHz to 1785 MHz). · For 3.5 V nominal operation

Features
· 2 in / 2 out dual band amplifier · Simple external circuit including output matching circuit · Simple power control · High gain 3stage amplifier : 0 dBm input Typ · Lead less thin & Small package : 8 × 13.75 × 1.6 mm Typ · High efficiency : 46 % Typ at 35.0 dBm for E-GSM 40 % Typ at 32.0 dBm for DCS1800

Pin Arrangement
· RF-K-8
5 G6 8 7 G 12

G 4 G 3

1: Pin GSM 2: Vapc 3: Vdd1 4: Pout GSM 5: Pout DCS 6: Vdd2 7: Vctl 8: Pin DCS G: GND

PF08107BP
Absolute Maximum Ratings
(Tc = 25°C)
Item Supply voltage Supply current Vctl voltage Vapc voltage Input power Operating case temperature Storage temperature Output power Symbol Vdd Idd GSM Idd DCS Vctl Vapc Pin Tc (op) Tstg Pout GSM Pout DCS Rating 8 3.5 2 4 4 10 -30 to +100 -30 to +100 37 34.8 Unit V A A V V dBm °C °C dBm dBm

Note: The maximum ratings shall be valid over both the E-GSM-band (880 to 915 MHz), and the DCS1800-band (1710 to 1785 MHz).

Electrical Characteristics for DC
(Tc = 25°C)
Item Drain cutoff current Symbol Ids Min Typ Max 20 300 Unit µA µA Test Condition Vdd = 4.7 V, Vapc = 0 V, Vctl = 0.2 V Vdd = 8 V, Vapc = 0 V, Vctl = 0.2 V, Tc = -20 to +70°C Vapc = 2.2 V Vctl = 3 V

Vapc control current Vctl control current

Iapc Ictl





3 2

mA µA

Rev.3, Dec. 2001, page 2 of 19

PF08107BP
Electrical Characteristics for E-GSM mode
(Tc = 25°C) Test conditions unless otherwise noted: f = 880 to 915 MHz, Vdd1 = Vdd2 = 3.5 V, Pin = 0 dBm, Vctl = 2.0 V, Rg = Rl = 50 , Tc = 25°C, Pulse operation with pulse width 577 µs and duty cycle 1:8 shall be used.
Item Frequency range Band select (GSM active) Input power Control voltage range Supply voltage Total efficiency 2nd harmonic distortion 3rd harmonic distortion 4th~8th harmonic distortion Input VSWR Output power (1) Output power (2) Isolation Isolation at DCS RF-output when GSM is active Switching time Stability Symbol F Vctl Pin Vapc Vdd T 2nd H.D. 3rd H.D. 4th~8th H.D. VSWR (in) Pout (1) Pout (2) Min 880 2.0 ­2 0.2 3.0 41 35.0 34.0 Typ 0 3.5 46 -45 -45 1.5 36.0 35.0 -42 -30 Max 915 2.8 2 2.2 4.5 -35 -35 -35 3 -37 -20 Unit MHz V dBm V V % dBc dBc dBc dBm dBm dBm dBm Vapc = 2.2 V Vdd = 3.1 V, Vapc = 2.2 V, Tc = +70°C Vapc = 0.2 V, Pin = 2 dBm Pout GSM = 35 dBm, Measured at f = 1760 to 1830 MHz Pout GSM = 0 to 35.0 dBm Vdd = 3.1 to 4.5 V, Pout 35 dBm, Vapc GSM 2.2 V, Rg = 50 , Tc = 25°C, Output VSWR = 6 : 1 All phases Vdd = 3.1 to 4.5 V, Pout GSM 35 dBm, Vapc GSM 2.2 V, Rg = 50 , t = 20 sec., Tc = 25°C, Output VSWR = 10 : 1 All phases Pout GSM = 35 dBm, Vapc = controlled Test Condition

t r, t f



1

2

µs

No parasitic oscillation

Load VSWR tolerance



No degradation



Rev.3, Dec. 2001, page 3 of 19

PF08107BP
Electrical Characteristics for DCS1800 mode
(Tc = 25°C)

Test conditions unless otherwise noted:
f = 1710 to 1785 MHz, Vdd1 = Vdd2 = 3.5 V, Pin = 0 dBm, Vctl = 0 V, Rg = Rl = 50 , Tc = 25°C, Pulse operation with pulse width 577 µs and duty cycle 1:8 shall be used.
Item Frequency range Band select (DCS active) Input power Control voltage range Supply voltage Total efficiency 2nd harmonic distortion 3rd harmonic distortion 4th~8th harmonic distortion Input VSWR Output power (1) Output power (2) Isolation Switching time Stability Symbol F Vctl Pin Vapc Vdd T 2nd H.D. 3rd H.D. 4th~8th H.D. VSWR (in) Pout (1) Pout (2) t r, t f Min 1710 0 ­2 0.2 3.0 34 32.5 31.0 Typ 0 3.5 40 -45 -45 1.5 33.5 32.0 -42 1 Max 1785 0.1 2 2.2 4.5 -35 -35 ­35 3 -37 2 Unit MHz V dBm V V % dBc dBc dBc dBm dBm dBm µs Vapc = 2.2 V Vdd = 3.1 V, Vapc = 2.2 V, Tc = +70°C Vapc = 0.2 V, Pin DCS = 2 dBm Pout DCS = 0 to 32 dBm Vdd = 3.1 to 4.5 V, Pout DCS 32 dBm, Vapc 2.2 V, Rg = 50 , Output VSWR = 6 : 1 All phases Vdd = 3.1 to 4.5 V, Pout DCS 32 dBm, Vapc 2.2 V, Rg = 50 , t = 20 sec., Output VSWR = 10 : 1 All phases Pout DCS = 32 dBm, Vapc = controlled Test Condition DCS1800 (1710 to 1785)

No parasitic oscillation

Load VSWR tolerance



No degradation



Rev.3, Dec. 2001, page 4 of 19

PF08107BP
Internal Diagram and External Circuit
PIN8 Pin DCS PIN5 Pout DCS

PIN1 Pin GSM

Z1

Z2 Bias circuit

PIN4 Pout GSM

Z3

Z4

PIN2 Vapc

PIN7 Vctl

PIN3 Vdd1 C1

PIN6 Vdd2 C2 C5 FB C6 FB Vdd2 Pout GSM Pout DCS

C3 FB Pin Pin Vapc

C4 FB Vctl

FB

Vdd1

Note: C1 to C4 = 0.01 µF CERAMIC CHIP C5 = C6 = 4.7 µF TANTALUM ELECTROLYTE FB = FERRITE BEAD BLO1RN1-A62-001 (MURATA) or equivalent Z1 = Z2 = Z3 = Z4 = 50 MICRO STRIP LINE

Rev.3, Dec. 2001, page 5 of 19

PF08107BP
Characteristic Curves
GSM mode Pout, Efficiency vs. Vapc 40 30 20 10
Pout (dBm)

60 f = 880 MHz, Pin = 0 dBm, Vdd = 3.5 V, Tc = 25°C Pout Eff 55 50 45 40 35 30 25 20 15 0 0.5 1 Vapc (V) 1.5 2 10 2.5
Efficiency (%) Efficiency (%)

0 -10 -20 -30 -40 -50 -60

GSM mode Pout, Efficiency vs. Vapc 40 30 20 10
Pout (dBm)

60 f = 915 MHz, Pin = 0 dBm, Vdd = 3.5 V, Tc = 25°C Pout Eff 55 50 45 40 35 30 25 20 15 0 0.5 1 Vapc (V) 1.5 2 10 2.5

0 -10 -20 -30 -40 -50 -60

Rev.3, Dec. 2001, page 6 of 19

PF08107BP
GSM mode Efficiency vs. Pout 60 f = 880, 915 MHz, Pin = 0 dBm, Vdd = 3.5 V, Tc = 25°C 880 MHz 915 MHz

50

Efficiency (%)

40

30

20

10

0 0 5 10 15 20 Pout (dBm) 25 30 35 40

Rev.3, Dec. 2001, page 7 of 19

PF08107BP
GSM mode Pout, Efficiency vs. Pin 40 f = 880 MHz, Vdd = 3.5 V, Tc = 25°C, Pout: Vapc = 2.2 V Eff: Pout = 35 dBm Pout Eff 60

39

55

37

45

36

40

35

35

34 -10

-8

-6

-4

-2

0 Pin (dBm)

2

4

6

8

30 10

GSM mode Pout, Efficiency vs. Pin 40 f = 915 MHz, Vdd = 3.5 V, Tc = 25°C, Pout: Vapc = 2.2 V Eff: Pout = 35 dBm Pout Eff 60

39

55

37

45

36

40

35

35

34 -10

-8

-6

-4

-2

0 Pin (dBm)

2

4

6

8

30 10

Rev.3, Dec. 2001, page 8 of 19

Efficiency (%)

38
Pout (dBm)

50

Efficiency (%)

38
Pout (dBm)

50

PF08107BP
GSM mode Pout vs. Vdd 40 39 38 f = 880, 915 MHz, Pin = 0 dBm, Vapc = 2.2 V, Tc = 25°C 880 MHz 915 MHz

Pout (dBm)

37 36 35 34 33 3 3.25 3.5 3.75 Vdd (V) 4 4.25 4.5

Rev.3, Dec. 2001, page 9 of 19

PF08107BP
GSM mode Pout, Efficiency vs. Frequency 40 55

38

50

Pout (dBm)

36

45

34

32

Pin = 0 dBm, Vdd = 3.5 V, Tc = 25°C, Pout: Vapc = 2.2 V Eff: Pout = 35 dBm Pout Eff 860 880 900 Freq (MHz) 920 940

40

35

30 840

30 960

Rev.3, Dec. 2001, page 10 of 19

Efficiency (%)

PF08107BP
GSM mode Pout vs. Pin: Temperature variation 38

37

Pout (dBm)

36

35

34

f = 880 MHz, Vdd = 3.1 V, 3.5 V, Vapc = 2.2 V, Tc = 25°C, 70°C Vdd = 3.5 V, 25°C Vdd = 3.5 V, 70°C Vdd = 3.1 V, 70°C -8 -6 -4 -2 0 Pin (dBm) 2 4 6 8 10

33 -10

GSM mode Pout vs. Pin: Temperature variation 38 f = 915 MHz, Vdd = 3.1 V, 3.5 V, Vapc = 2.2 V, Tc = 25°C, 70°C

37

Pout (dBm)

36

35

34

Vdd = 3.5 V, 25°C Vdd = 3.5 V, 70°C Vdd = 3.1 V, 70°C -8 -6 -4 -2 0 Pin (dBm) 2 4 6 8 10

33 -10

Rev.3, Dec. 2001, page 11 of 19

PF08107BP
DCS mode Pout, Efficiency vs. Vapc 40 30 20 10
Pout (dBm)

50 f = 1710 MHz, Pin = 0 dBm, Vdd = 3.5 V, Tc = 25°C Pout Eff 45 40 35 30 25 20 15 10 5 0 0.5 1 Vapc (V) 1.5 2 0 2.5
Efficiency (%) Efficiency (%)

0 -10 -20 -30 -40 -50 -60

DCS mode Pout, Efficiency vs. Vapc 40 30 20 10
Pout (dBm)

50 f = 1785 MHz, Pin = 0 dBm, Vdd = 3.5 V, Tc = 25°C Pout Eff 45 40 35 30 25 20 15 10 5 0 0.5 1 Vapc (V) 1.5 2 0 2.5

0 -10 -20 -30 -40 -50 -60

Rev.3, Dec. 2001, page 12 of 19

PF08107BP
DCS mode Efficiency vs. Pout 50 f = 1710, 1785 MHz, Pin = 0 dBm, Vdd = 3.5 V, Tc = 25°C 1710 MHz 1785 MHz

40

Efficiency (%)

30

20

10

0 0 5 10 15 20 Pout (dBm) 25 30 35 40

Rev.3, Dec. 2001, page 13 of 19

PF08107BP
DCS mode Pout, Efficiency vs. Pin 35.0 f = 1710 MHz, Vdd = 3.5 V, Tc = 25°C, Pout: Vapc = 2.2 V Eff: Pout = 32 dBm Pout Eff 60

34.5

55

33.5

45

33.0

40

32.5

35

32.0 -10

-8

-6

-4

-2

0 Pin (dBm)

2

4

6

8

30 10

DCS mode Pout, Efficiency vs. Pin 34.0 f = 1785 MHz, Vdd = 3.5 V, Tc = 25°C, Pout: Vapc = 2.2 V Eff: Pout = 32 dBm Pout Eff 60

33.5

55

32.5

45

32.0

40

31.5

35

31.0 -10

-8

-6

-4

-2

0 Pin (dBm)

2

4

6

8

30 10

Rev.3, Dec. 2001, page 14 of 19

Efficiency (%)

33.0
Pout (dBm)

50

Efficiency (%)

34.0
Pout (dBm)

50

PF08107BP
DCS mode Pout vs. Vdd 38 37 36 f = 1710, 1785 MHz, Pin = 0 dBm, Vapc = 2.2 V, Tc = 25°C 1710 MHz 1785 MHz

Pout (dBm)

35 34 33 32 31 30 3 3.25 3.5 3.75 Vdd (V) 4 4.25 4.5

Rev.3, Dec. 2001, page 15 of 19

PF08107BP
DCS mode Pout, Efficiency vs. Frequency 38 37 36 Pin = 0 dBm, Vdd = 3.5 V, Tc = 25°C, Pout: Vapc = 2.2 V Eff: Pout = 32 dBm Pout Eff 50

45

Pout (dBm)

35 34 33 32 31

40

35

30 1650

1700

1750 Freq (MHz)

1800

30 1850

Rev.3, Dec. 2001, page 16 of 19

Efficiency (%)

PF08107BP
DCS mode Pout vs. Pin: Temperature variation 35

34

33
Pout (dBm)

32 f = 1710 MHz, Vdd = 3.1 V, 3.5 V, Vapc = 2.2 V, Tc = 25°C, 70°C Vdd = 3.5 V, 25°C Vdd = 3.5 V, 70°C Vdd = 3.1 V, 70°C -8 -6 -4 -2 0 Pin (dBm) 2 4 6 8 10

31

30

29 -10

DCS mode Pout vs. Pin: Temperature variation 35

34

33
Pout (dBm)

32 f = 1785 MHz, Vdd = 3.1 V, 3.5 V, Vapc = 2.2 V, Tc = 25°C, 70°C Vdd = 3.5 V, 25°C Vdd = 3.5 V, 70°C Vdd = 3.1 V, 70°C -8 -6 -4 -2 0 Pin (dBm) 2 4 6 8 10

31

30

29 -10

Rev.3, Dec. 2001, page 17 of 19

PF08107BP
Package Dimensions
Unit: mm

1.6 ± 0.2 8
8.0 ± 0.3

7

G

6

5
8.0 ± 0.3

G

G

1

2

G 3 (Upper side)

4 5 G6 8 7 G 12 G 4 G 3

13.75 ± 0.3
(5.375) (5.375)

(3.275) (3.275) (1.6) (1.6)
(1.4)

(3.7) (1.3)

(1.6) (1.6)

(3.7)

(1.4) (2.4)
(1.4)

(3.7)

(2.4)

(2.2)

(0.7)

(1.5) (1.5)

1: Pin GSM 2: Vapc 3: Vdd1 4: Pout GSM 5: Pout DCS 6: Vdd2 7: Vctl 8: Pin DCS G: GND

(3.7)

(3.7)

(Bottom side)

Remark: Coplanarity of bottom side of terminals are less than 0 ± 0.1mm.
Hitachi Code JEDEC JEITA Mass (reference value) RF-K-8

Rev.3, Dec. 2001, page 18 of 19

PF08107BP

Sales Strategic Planning Div.
Keep safety first in your circuit designs!

Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.

http://www.renesas.com

Copyright © 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan.
Colophon 0.0

Rev.3, Dec. 2001, page 19 of 19