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Data Sheet No. PD-6.034G
IR2151
SELF-OSCILLATING HALF-BRIDGE DRIVER
Features
n Floating channel designed for bootstrap operation Fully operational to +600V Tolerant to negative transient voltage dV/dt immune n Undervoltage lockout n Programmable oscillator frequency
Product Summary
VOFFSET Duty Cycle IO+/VOUT Deadtime (typ.) 600V max. 50% 100 mA / 210 mA 10 - 20V 1.2 µs
f =
1 1.4 × (R T + 75) × CT
n Matched propagation delay for both channels n Low side output in phase with RT
Description
The IR2151 is a high voltage, high speed, self-oscillating power MOSFET and IGBT driver with both high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The front end features a programmable oscillator which is similar to the 555 timer. The output drivers feature a high pulse current buffer stage and an internal deadtime designed for minimum driver cross-conduction. Propagation delays for the two channels are matched to simplify use in 50% duty cycle applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration that operates off a high voltage rail up to 600 volts.
Packages
Typical Connection
up to 600V
V CC RT CT COM
VB HO VS LO
TO LOAD
CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL
B-187
IR2151
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions.
Symbol
VB VS VHO VLO VRT VCT ICC IRT dVs/dt PD RJA TJ TS TL
Parameter Definition
High Side Floating Supply Voltage High Side Floating Supply Offset Voltage High Side Floating Output Voltage Low Side Output Voltage RT Voltage CT Voltage Supply Current (Note 1) RT Output Current Allowable Offset Supply Voltage Transient Package Power Dissipation @ TA +25°C Thermal Resistance, Junction to Ambient Junction Temperature Storage Temperature Lead Temperature (Soldering, 10 seconds) (8 Lead DIP) (8 Lead SOIC) (8 Lead DIP) (8 Lead SOIC)
Value Min.
-0.3 VB - 25 VS - 0.3 -0.3 -0.3 -0.3 -- -5 -- -- -- -- -- -- -55 --
Max.
625 VB + 0.3 VB + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 25 5 50 1.0 0.625 125 200 150 150 300
Units
V
mA V/ns W °C/W
°C
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. The VS offset rating is tested with all supplies biased at 15V differential.
Symbol
VB VS VHO VLO ICC TA Note 1:
Parameter Definition
High Side Floating Supply Absolute Voltage High Side Floating Supply Offset Voltage High Side Floating Output Voltage Low Side Output Voltage Supply Current (Note 1) Ambient Temperature
Value Min.
VS + 10 -- VS 0 -- -40
Max.
VS + 20 600 VB VCC 5 125
Units
V
mA °C
Because of the IR2151's application specificity toward off-line supply systems, this IC contains a zener clamp structure between the chip VCC and COM which has a nominal breakdown voltage of 15.6V. Therefore, the IC supply voltage is normally derived by forcing current into the supply lead (typically by means of a high value resistor connected between the chip VCC and the rectified line voltage and a local decoupling capacitor from VCC to COM) and allowing the internal zener clamp circuit to determine the nominal supply voltage. Therefore, this circuit should not be driven by a DC, low impedance power source of greater than VCLAMP.
B-188 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL
IR2151
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 12V, CL = 1000 pF and TA = 25°C unless otherwise specified.
Symbol
tr tf DT D
Parameter Definition
Turn-On Rise Time Turn-Off Fall Time Deadtime RT Duty Cycle
Value Min. Typ. Max. Units Test Conditions
-- -- 0.50 48 80 40 1.20 50 120 70 2.25 52 ns µs %
Static Electrical Characteristics
VBIAS (VCC , VBS) = 12V, CL = 1000 pF C T = 1 nF and TA = 25°C unless otherwise specified. The VIN, VTH and IIN , parameters are referenced to COM. The V O and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
Symbol
fOSC VCLAMP VCT+ VCTVCTUV VRT+ VRTVRTUV VOH VOL I LK I QBS I QCC ICT VCCUV+ VCCUVVCCUVH I O+ I O-
Parameter Definition
Oscillator Frequency VCC Zener Shunt Clamp Voltage 2/3 VCC Threshold 1/3 VCC Threshold CT Undervoltage Lockout RT High Level Output Voltage, V CC - RT RT Low Level Output Voltage RT Undervoltage Lockout, VCC - RT High Level Output Voltage, VBIAS - VO Low Level Output Voltage, VO Offset Supply Leakage Current Quiescent VBS Supply Current Quiescent VCC Supply Current CT Input Current VCC Supply Undervoltage Positive Going Threshold VCC Supply Undervoltage Negative Going Threshold VCC Supply Undervoltage Lockout Hysteresis Output High Short Circuit Pulsed Current Output Low Short Circuit Pulsed Current
Value Min. Typ. Max. Units Test Conditions
19.4 94 14.4 7.8 3.8 -- -- -- -- -- -- -- -- -- -- -- -- 7.7 7.4 200 100 210 20.0 100 15.6 8.0 4.0 20 0 200 20 200 0 -- -- -- 10 400 0.001 8.4 8.1 500 125 250 20.6 106 16.8 8.2 4.2 50 100 300 50 300 100 100 100 50 50 950 1.0 9.2 8.9 -- -- -- V µA mV 2.5V
mV mA VO = 0V VO = 15V
CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL
B-189
IR2151
Functional Block Diagram
VB R RT + R + R UV DETECT R S Q Q VCC 15.6V DEAD TIME DELAY LO
HV LEVEL SHIFT
Q PULSE FILTER R S VS
HO
DEAD TIME
PULSE GEN
CT
COM
Lead Definitions
Lead Symbol Description
RT CT Oscillator timing resistor input,in phase with LO for normal IC operation Oscillator timing capacitor input, the oscillator frequency according to the following equation:
f =
1 1.4 × (R T + 75) × CT
VB HO VS VCC LO COM
where 75 is the effective impedance of the RT output stage High side floating supply High side gate drive output High side floating supply return Low side and logic fixed supply Low side gate drive output Low side return
Lead Assignments
8 Lead DIP
SO-8
IR2151
B-190 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL
IR2151S
IR2151
Device Information
Process & Design Rule Transistor Count Die Size Die Outline HVDCMOS 4.0 µm 231 68 X 101 X 26 (mil)
Thickness of Gate Oxide Connections First Layer
Second Layer Contact Hole Dimension Insulation Layer Passivation Method of Saw Method of Die Bond Wire Bond Leadframe
Material Width Spacing Thickness Material Width Spacing Thickness Material Thickness Material Thickness
Package Remarks:
Method Material Material Die Area Lead Plating Types Materials
800Å Poly Silicon 5 µm 6 µm 5000Å Al - Si - Cu (Si: 1.0%, Cu ±0.5%) 6 µm 9 µm 20,000Å 5 µm X 5 µm PSG (SiO2) 1.7 µm PSG (SiO2) 1.7 µm Full Cut Ablebond 84 - 1 Thermo Sonic Au (1.0 mil / 1.3 mil) Cu Ag Pb : Sn (37 : 63) 8 Lead PDIP / SO-8 EME6300 / MP150 / MP190
CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL
B-191
IR2151
VCCUV + VCC VCLAMP
RT (HO)
RT CT
50%
50%
RT (LO)
tr tf 90% 90%
HO
LO
LO HO
10%
10%
Figure 1. Input/Output Timing Diagram
Figure 2. Switching Time Waveform Definitions
RT
50% 50%
90%
HO LO
90%
10% DT
10%
Figure 3. Deadtime Waveform Definitions
B-192 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL