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5 4 3 2 1
Schematics Page Index (Title / Revision / Change Date)
Page Title of Schematics Page Rev. Date Page Title of Schematics Page Rev. Date
01 Schematics Page Index 1.0 2007/8/24 41 ICH8-M( POWER) 4/5 1.0 2007/8/24
02 Block Diagram 1.0 2007/8/24 42 ICH8-M( GND) 5/5 1.0 2007/8/24
03 CLOCK GEN (CK505) 1.0 2007/8/24 43 LAN (88E8055 MARVELL) 1.0 2007/8/24
D
04 MEROM(HOST BUS) 1/2 2.0 2007/8/30 44 EC+KBC (3910) 2.0 2007/8/30 D
05 MEROM(HOST BUS) 2/3 1.0 2007/8/24 45 Flash ROM/XBUS 1.0 2007/8/24
06 MEROM(Power/Gnd) 3/3 1.0 2007/8/24 46 SATA HDD RAID 1.0 2007/8/24
07 Crestline (HOST) 1/7 1.0 2007/8/24 47 PATA CD-ROM 1.0 2007/8/24
08 Crestline (DMI) 2/7 1.0 2007/8/24 48 PCI (PCI BUS) 1.0 2007/8/24
09 Crestline (GRAPHIC) 3/7 1.0 2007/8/24 49 PCI ( ILINK) 1.0 2007/8/24
10 Crestline (DDRII) 4/7 1.0 2007/8/24 50 PCI (MS-STD/DUO/MDC/SD) 1.0 2007/8/24
11 Crestline (POWER,VCC) 5/7 1.0 2007/8/24 51 PCI ( PCMCIA) 1.0 2007/8/24
12 Crestline (VCC CORE) 6/7 1.0 2007/8/24 52 Bluetooth 1.0 2007/8/24
13 Crestline (VSS) 7/7 1.0 2007/8/24 53 Mini-PCIE Card 1.0 2007/8/24
14 DDRII(SO-DIMM_0) 1/3 1.0 2007/8/24 54 EXPRESS 1.0 2007/8/24
15 DDRII(SO-DIMM_1) 2/3 1.0 2007/8/24 55 USB2.0 1.0 2007/8/24
16 DDRII(Termination) 3/3 1.0 2007/8/24 56 CIR Reciver 1.0 2007/8/24
17 VGA(PCI-E) 1.0 2007/8/24 57 FAN / HW THERMAL PROTECTION 1.0 2007/8/24
18 VGA(STRAP) 1.0 2007/8/24 58 Daughter Board Conn. 1.0 2007/8/24
C C
19 VGA(GDDR) 1.0 2007/8/24 59 CAM/OIDE 1.0 2007/8/24
20 VGA(MULTIUSE) 1.0 2007/8/24 60 Logo LED 1.0 2007/8/24
21 VGA(LVD/VDAC ) 1.0 2007/8/24 61 AUDIO(CODEC & POWER) 1.0 2007/8/24
22 VRAM(GDDR)# 1/4 1.0 2007/8/24 62 AUDIO( AMP & HP & SPK) 1.0 2007/8/24
23 VRAM(GDDR)# 2/4 1.0 2007/8/24 63 AUDIO (MUTE & INTMIC) 1.0 2007/8/24
24 VRAM(GDDR)# 3/4 1.0 2007/8/24 64 AUDIO (Second Codec) 1.0 2007/8/24
25 VRAM(GDDR)# 4/4 1.0 2007/8/24 65 Audio BOARD conn 1.0 2007/8/24
26 VGA(POWER) 1/3 1.0 2007/8/24 66 Power Design Diagram 1.0 2007/8/24
27 VGA(POWER) 2/3 1.0 2007/8/24 67 DCIN&Charger 1.0 2007/8/24
28 VGA(POWER) 3/3 1.0 2007/8/24 68 SYS Power (+3_3V/+5V) 1.0 2007/8/24
29 VRAM(BYPASS) 1/4 1.0 2007/8/24 69 SYS Power(+1_5V/+1_05V) 1.0 2007/8/24
30 VRAM(BYPASS) 2/4 1.0 2007/8/24 70 DDR2 Power(+1_8V/+0_9V) 1.0 2007/8/24
31 VRAM(BYPASS) 3/4 1.0 2007/8/24 71 CPU_Vcore ---MAX8771 1.0 2007/8/24
32 VRAM(BYPASS) 4/4 1.0 2007/8/24 72 Others power plan 1.0 2007/8/24
B 33 TVIN and OUT/Semi-PnP# 1.0 2007/8/24 73 OVP protection 1.0 2007/8/24 B
34 CRT 1.0 2007/8/24 74 VGA POWER(+1_1V/ +1_2V) 1.0 2007/8/24
35 LVDS 1.0 2007/8/24 75 Inverter Boost Circuit 1.0 2007/8/24
36 HDMI 1.0 2007/8/24 76 HOLE & BOSS 2.0 2007/8/30
37 MINI PCI (TV) 1.0 2007/8/24 77 HISTORY(DVT) 1.0 2007/8/24
38 ICH8-M( PCI/USB ) 1/5 1.0 2007/8/24 78 1.0 2007/8/24
39 ICH8-M(LPC,IDE,SATA)2/5 1.0 2007/8/24 79 1.0 2007/8/24
40 ICH8-M( GPIO) 3/5 1.0 2007/8/24 80 1.0 2007/8/24
P. Leader Check by Design by
A A
HON HAI PRECISION IND. CO., LTD.
Project Code & Schematics Subject: M612 PVT Main Board PCB P/N: FOXCONN
Title
CPBG - R&D Division
Index Page
Size Document Number Rev
A3 (M612-1-01 )MainBoard (MBX-176) 2007.8.24 1.0
Date: Friday, August 31, 2007 Sheet 1 of 81
5 4 3 2 1
1 2 3 4 5 6 7 8
M612(Beagle Santa Rosa )Block Diagram Red texts:
New modified
A
S-OUT EEPROM GFX CPU Clock Gen. A
PAGE 29 HDMI A KEY
S-OUT/LVDS/VGA/HDMI
nVIDIA Merom CK505 X,TAL
LVDS ICS,ICS9LPR358YGLFT 14.318MHZ
WSXGA+ H NB8P-GS(HDMI) Processor
PAGE 31 ACL262 M NB8M-GT(HDMI)
SPDIF SPDIF CODEC
PAGE 3
Micro-FCBGA-478
VGA Audio board PAGE 60 L NB8M-GT(HDMI) (Socket 478 -pin Micro FCPGA)
D-type-15p GDDR3 1.8V SDRAM 256MB/512MB/1GMB/2GMB
PAGE 30 Ext. Mic In PAGE 17~31
Jack PAGE 4~6 SO-DIMM 0
Audio SPDIF
PCIE X16
HDMI Audio board 667 MHZ
(HDCP) Daughter for FSB
DDR(II)
Board 800 MHZ
HEAD HDMI
PAGE 32 200 pin
PHONE
USB 2.0 JACK PAGE 14
CONN Audio board AZALIA
North Bridge
Audio board
Crestline SO-DIMM 1
667 MHZ
FCBGA-1299pin DDR(II)
CXD9872AKD
Int. Speaker CODEC 200 pin
B 1.0 Walt x 2 APA2068KAI-TRL AZALIA PAGE 7~13
PAGE 15
B
PAGE 58 PAGE 58 PAGE 57
ANPEC Controller X2/X4 DMI USB 2.0
Int. Microphone Link0 (Direct Media Interface) CONN.X2
USB2.0 2
PAGE 51
PAGE 59
MDC 1.5 PCIE + USB2.0
Modem AZALIA Express Card
RJ11 12 pin South Bridge PCIE PAGE 50
PAGE 46
USB2.0 ICH8M / ICH8M-E
USB2.0 Mini-Card
33MHZ, 3.3V PCI BUS BGA_652pin
SKU(H):Enhanced PCIE
M611 BOM configuration SKU(M)(L):Base USB2.0 PAGE 49
PCMCIA PAGE 34~38
unstuff NC_ Conn.
PCIE
LCI
NV_ PAGE 47 CAM(1.3M)
SATA 3Gb/s
NB8P-GS + NB8M-GT
TI PCI8412ZHK LPC PAGE 50
NB8P-GS NV8P_ MS DUO Mini stereo
PAGE 46 PAGE 29
NB8M-GT NV8M_
IDE ATA 100
C SD
CardBus
B-CAS JP Digital only Mini PCI ENE KB3910SFC1 USB2.0 Bluetooth
C
NB8M-GT NV8MM_ PAGE 46 PAGE 33 (TV) LQFP-176
CardReader PAGE 48
NB8M-GT for L Model i.LINK S-IN PAGE 33
NV8ML_ i.LINK
PAGE 29
PAGE 45 PAGE 44~47 Oide
NB8X + Hynix VRAM NVH_ USB2.0
F/PAL Ethernet G-LAN PAGE 40 PATA SATA SATA PAGE 50
ODD HDD -RAID0 HDD -RAID1
88E8055
NB8M+16Mx32 VRAM NVNEW MARVELL PAGE 43 PAGE 42 PAGE 42
Transformer
RJ45 Netswap, 10/100/1000 USB2.0 IR Reciver
NB8P + 16Mx32bit VRAM NVNOR PAGE 39 NS682403P, SMB Channel 1
PAGE 39 PAGE 52
PAGE 39
NB8M + 8Mx32bit VRAM NVNOR SMB Channel 2
PWM
NB8X + Infineon VRAM NVI_ PS/2
NB8X + ISA
Infineon & Samsung VRAM NVIS_ Thermal Sensor Thermal Sensor
NB8X + FAN Lid Switch Flash BIOS F75384M F75383M
Hynix & Infineon VRAM NVHS_ & LED Touchpad 1MB BATT CONN. (CPU/GMCH) (VGA/DIMM)
D
uSOP-8 uSOP8 D
NB8X + 16Mx32bit VRAM PAGE 53 PAGE 54 PAGE 54 PAGE 41 PAGE 63 PAGE 4 PAGE 20
NV16_
NB8X + 8Mx32bit VRAM NV8_
*JP Digital TV Tuner SKU HON HAI PRECISION IND. CO., LTD.
unstuff JDTVNC_ FOXCONN
Title
CPBG - R&D Division
Block Diagram
Mini PCI CONN,BT CONN,
IR CONN,FeliCa CONN LNC_ Size Document Number Rev
C (M612-1-01 )MainBoard (MBX-176) 2007.8.24 1.0
unstuff for L Model
Date: Friday, August 31, 2007 Sheet 2 of 81
1 2 3 4 5 6 7 8
5 4 3 2 1
11/2 backup
+3VRUN HCB2012KF-121T30
for EMI request L17 120R-100MHZ_0805
FSB Frequency Table:
close to R46 +1_25VRUN HCB2012KF-121T30 R39 R41
C1941 R46 0_J 0805 L6 120R-100MHZ_0805 1_F 0402 1_F 0402
FSLC FSLB FSLA CPU SRC[7:0] PCI FSB
2 1 1 2 V1P0B +3V_CLK_3D 1 2 1 2 +3V_CLK_3A
1 0 1 100 100 33 /
1
1
1
1
1
1
NC_0.1U_10V_K C151 C87 C43 C782 C46 C785
0 0 1 133 100 33 /
2
0402_X5R 0.1U_16V_Y_Y 10U_6.3V_M 0.01U_16V_K_B 1U_25V_K_B 0.01U_16V_K_B 1U_25V_K_B
CKG_IO_VOUT R47
NC_10_J
HCB2012KF-121T30
L10 120R-100MHZ_0805
0402 0805_X5R 0402 0603
R42 R44
0402 0603 0 1 1 166 100 33 667
2
2
2
2
2
2
2
R1023
0603 V1P0D
+3V_CLK_3E
1_F
1
0402
2
1_F
1
0402
2 +3V_CLK_3B
0 1 0 200 100 33 800
1
1
NC_33_J C135 C96
0 0 0 266 100 33 /
31
1
1
1
1
D 0402 0.1U_16V_Y_Y 10U_6.3V_M C44 C784 C47 C783 D
D Q23 HCB2012KF-121T30
L15 120R-100MHZ_0805
0402 0805_X5R 0.01U_16V_K_B
0402
1U_25V_K_B
0603
0.01U_16V_K_B
0402
1U_25V_K_B
0603
1 0 0 333 100 33 /
1
2
2
1 V1P0C R43 R45
1 1 0 400 100 33 /
2
2
2
2
G S NC_BSS138 1_F 0402 1_F 0402
1
1
NC_100P_50V_K_N
C155 C97 +3V_CLK_3F 1 2 1 2 +3V_CLK_3C
1 1 1 (Reserced)
1
C928 0402
0.1U_16V_Y_Y 10U_6.3V_M C45
2
1
1
1
1
1
HCB2012KF-121T30 0402 0805_X5R 0.01U_16V_K_B C781 C83 C48 C786
L13 120R-100MHZ_0805 0402 1U_25V_K_B 10U_6.3V_M 0.01U_16V_K_B 1U_25V_K_B
2
2
V1P0S 0603 0805_X5R 0402 0603 0
R2113 NC_10K_J 402
2
1 2 R_PCI_F5_ITP_EN pin7 setting 0=SRC8,1=ITP for pin 46,47
2
2
2
2
2
+3VRUN
1
1
If 9LP505, populate R47,R1023,C928,Q23 C149 C150
61 +3V_CLK_3D
2 +3V_CLK_3C
39 +3V_CLK_3E
9 +3V_CLK_3B
16 +3V_CLK_3A
55 +3V_CLK_3F
and depopulate R46. 0.1U_16V_Y_Y 10U_6.3V_M
Ig 9LP501, populate R46 and depopulate 0402 0805_X5R R2103 NC_10K_J 0402
R47,R1023,C928,Q23. 1 2
2
2
R2104 10K_J 0402
U18 1 2 R_PCI2_TME pin4 setting 0= Overclocking of CPU and SRC Allowed
+3VRUN
Y1 V1P0B 12 1= Overclocking of CPU and SRC NOT allowed
VDDPCI
VDDREF
VDD48
VDDPLL3
VDDCPU
VDDSRC
ITTI_L5030-14.31818-20 V1P0D VDD96_IO
49 VDDCPU_IO
14.318MHZ_20P_30PPM V1P0C 20 R2285 NC_10K_J 0402
A0501 V1P0S VDDPLL3_IO
1 2 45 VDDSRC_IO3 1 2
1
1
36 VDDSRC_IO2 PCI_STOP# 38 PM_STPPCI# 40
C80 C81 26 37
VDDSRC_IO1 CPU_STOP# STP_CPU# 40
33P_50V_J_N 33P_50V_J_N 1 TP737 2007/1/1 Roger request R2105 10K_J 0402
0402 0402 51 R_CLK_MCH_BCLK 3 2 26MIL 1 2 R_PCI4_27M_SEL pin6 setting 0= LCD_SST 100MHz differential clock.
2
2
CPUT1_F CLK_MCH_BCLK 7 +3VRUN
Length as short CPUC1_F 50R_CLK_MCH_BCLK# RP1 4 1 CLK_MCH_BCLK# 7 for pin17,18 1= 27MHz non-spread SE clock,
0404_4P2R 33 R2106 NC_10K_J 0402
C as possible. R1055 1 0_J 2 0402 U2_XTALIN 60 54 R_CLK_CPU_BCLK 3 2 1 2 C
X1 CPUT0 CLK_CPU_BCLK 4
R59 1 12.1_F 2 0402 53R_CLK_CPU_BCLK# RP2 4 1
48 CLK_CB48 CPUC0 CLK_CPU_BCLK# 4
U2_XTALOUT 59 0404_4P2R 33
R62 X2
40 CLK_USB48 1 12.1_F 2 0402 SRCT8/CPUT2_ITP 47 R_SRC8_CPU2ITP 1
SRCC8/CPUC2_ITP 46 R_SRC8#_CPU2#ITP 1 TP997 26MIL
CPU_BSEL0 R65 1 2.2K_J 2 0402R_FSLA_USB48M 10 TP998 26MIL R2107 10K_J 0402
CPU_BSEL1 R74 FSLA/USB_48MHZ
1 0_J 2 0402R_FSLB_TEST_MODE 57 FSLB/TEST_MODE SRCT7/CR#_F 44 R_SRCT7_CR#_F 1 +3VRUN 1 2
This dumping resistor TP999 26MIL
TP943 26MIL 1 CKG_IO_VOUT 48 30 R_CLK_MCH_3GPLL 4 1 R_PCI0_CR#_A 1 475_F 2 0402
and FB should be NC SRCT9 RP4 3 CLK_MCH_3GPLL 8 SATACLKREQ# 40
31 R_CLK_MCH_3GPLL# 2 CLK_MCH_3GPLL# 8
R2108
placed close to U18, R72 1 22_F 2 0402R_PCI_F5_ITP_EN7 SRCC9 0404_4P2R 33
38 CLK_ICHPCI PCI_F5/ITP_EN
update for MOR SRCC11/CR#_G 32 R_SRCC11_CR#_G R2109 10K_J 0402
requirement on12/23. +3VRUN 1 2
R68 1 22_F 2 0402R_PCI3 5 41 R_SRC6 3