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Philips Semiconductors Product specification

PowerMOS transistor PHD3N20L
Logic level FET

GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effect power transistor in a
plastic envelope suitable for surface VDS Drain-source voltage 200 V
mounting featuring high avalanche ID Drain current (DC) 3.5 A
energy capability, stable blocking Ptot Total power dissipation 50 W
voltage, fast switching and high RDS(ON) Drain-source on-state resistance 1.5
thermal cycling performance with low
thermal resistance. Intended for use
in Switched Mode Power Supplies
(SMPS), motor control circuits and
general purpose switching
applications.

PINNING - SOT428 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION tab d

1 gate
2 drain
g

3 source
2
s
tab drain
1 3

LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
ID Continuous drain current Tmb = 25