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Si6924EDQ
Vishay Siliconix
N-Channel 2.5-V (G-S) Battery Switch, ESD Protection
PRODUCT SUMMARY
VDS (V) rDS(on) (W) ID (A)
0.033 @ VGS = 4.5 V "4.6
28 0.038 @ VGS = 3.0 V "4.3 ESD Protected
0.042 @ VGS = 2.5 V "4.1 2000 V
FEATURES
D Low rDS(on) D rDS(on) Rating at 2.5-V VGS
D VGS Max Rating: 14 V D 28-V VDS Rated
D Exceeds 2-kV ESD Protection D Symetrical Voltage Blocking (Off Voltage)
D Low Profile TSSOP-8 Package
DESCRIPTION
The Si6924EDQ is a dual n-channel MOSFET with ESD designed to protect the gate from any remaining ESD energy
protection and gate over-voltage protection circuitry and over-voltages above the gates inherent safe operating
incorporated into the MOSFET. The device is designed for use range. The series resistor used to limit the current through the
in Lithium Ion battery pack circuits. The common-drain second stage diode during over voltage conditions has a
contsruction takes advantage of the typical battery pack maximum value which limits the input current to v 10 mA @
topology, allowing a further reduction of the device's 14 V and the maximum toff to 12 ms. The Si6924EDQ has been
on-resistance. The 2-stage input protection circuit is a unique optimized as a battery or load switch in Lithium Ion applications
design, consisting of two stages of back-to-back zener diodes with the advantage of both a 2.5-V rDS(on) rating and a safe
separated by a resistor. The first stage diode is designed to 14-V gate-to-source maximum rating.
absorb most of the ESD energy. The second stage diode is
APPLICATION CIRCUITS
D
ESD and ESD and
R**
Overvoltage Overvoltage
Protection Protection G
S
**R typical value is 1.8 kW by design.
Battery Protection Circuit
See Typical Characteristics,
Gate-Current vs. Gate-Source Voltage, Page 3.
*Thermal connection to drain pins is required to achieve specific performance.
FIGURE 1. Typical Use In a Lithium Ion Battery Pack FIGURE 2. Input ESD and Overvoltage Protection
Circuit.
Document Number: 70814 www.vishay.com
S-59522--Rev. C, 30-Nov-98 1
Si6924EDQ
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
*D *D
TSSOP-8
D 1 D 8 D 1.8 kW 1.8 kW
S1 2 Si6924EDQ 7 S2 G1 G2
S1 3 6 S2
G1 4 5 G2
Top View
S1 S2
N-Channel N-Channel
*Thermal connection to drain pins is required to achieve specific performance.
FIGURE 3. FIGURE 4.
ABSOLUTE MAXIMUM RATINGS (TA = 25_C UNLESS OTHERWISE NOTED)
Parameter Symbol Limit Unit
Drain-Source Voltage, Source-Drain Voltage VDS - to +
V
Gate-Source Voltage VGS "14
TA = 25_C "4.6
_
Continuous Drain-to-Source Current (TJ = 150_C)a, b ID
TA = 70_C "3.7
A
Pulsed Drain-to-Source Current IDM "20
Pulsed Source Current (Diode Conduction)a, b IS 1.25
TA = 25_C 1.1
Maximum Power Dissipationa, b PD W
TA = 70_C 0.72
Operating Junction and Storage Temperature Range TJ, Tstg -55 to 150 _C
THERMAL RESISTANCE RATINGS
Parameter Symbol Typical Maximum Unit
t v 10 sec 125
Maximum Junction-to-Ambienta RthJA _C/W
Steady-State 115
Notes
a. Surface Mounted on FR4 Board.
b. t v 10 sec.
www.vishay.com Document Number: 70814
2 S-59522--Rev. C, 30-Nov-98
Si6924EDQ
Vishay Siliconix
SPECIFICATIONS (TJ = 25_C UNLESS OTHERWISE NOTED)
Parameter Symbol Test Condition Min Typ Max Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 mA 0.5 V
VDS = 0 V, VGS = "4.5 V "1 mA
Gate-Body Leakage IGSS
VDS = 0 V, VGS = "14 V "10 mA
VDS = 22.4 V, VGS = 0 V 1
Zero Gate Voltage Drain Current IDSS mA
m
VDS = 22.4 V, VGS = 0 V, TJ = 55_C 5
On-State Drain Currentb ID(on) VDS w 5 V, VGS = 5 V 10 A
VGS = 4.5 V, ID = 4.6 A 0.026 0.033
Drain-Source On-State Resistanceb rDS(on) VGS = 3.0 V, ID = 4.3 A 0.029 0.038 W
VGS = 2.5 V, ID = 4.1 A 0.031 0.042
Forward Transconductanceb gfs VDS = 10 V, ID = 4.6 A 18 S
Diode Forward Voltageb VSD IS = 1.25 A, VGS = 0 V 0.7 1.1 V
Dynamica
Total Gate Charge Qg 14 20
Gate-Source Charge Qgs VDS = 10 V, VGS = 4.5 V, ID = 4.6 A 2.1 nC
Gate-Drain Charge Qgd 4.2
Turn-On Delay Time td(on) 0.55 1.0
Rise Time tr 2.0 4.0
VDD = 10 V, RL = 10 W
ms
m
Turn-Off Delay Time td(off) ID ^ 1 A, VGEN = 4.5 V, RG = 6 W 7.0 12
Fall Time tf 4.5 8
Notes
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width v 300 ms, duty cycle v 2%.
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Gate-Current vs. Gate-Source Voltage Gate Current vs. Gate-Source Voltage
8 10,000
1,000
I GSS - Gate Current (mA)
I GSS - Gate Current (mA)
6
100
10 TJ = 150_C
4
1
0.1
2
TJ = 25_C
0.01
0 0.001
0 4 8 12 16 0 2 4 6 8 10 12 14
VGS - Gate-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V)
Document Number: 70814 www.vishay.com
S-59522--Rev. C, 30-Nov-98 3
Si6924EDQ
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Output Characteristics Transfer Characteristics
20 20
VGS = 5 thru 2,5 V
16 2V 16
I D - Drain Current (A)
I D - Drain Current (A)
12 12
8 8
TC = 125_C
4 1.5 V 4
25_C
1V -55 _C
0 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5
VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V)
On-Resistance vs. Drain Current Capacitance
0.05 1200
r DS(on) - On-Resistance ( W )
0.04 900
C - Capacitance (pF)
VGS = 2.5 V
Ciss
0.03 600
Coss
VGS = 3 V
VGS = 4.5 V
0.02 300
Crss
0.01 0
0 4 8 12 16 20 0 4 8 12 16 20 24 28
ID - Drain Current (A) VDS - Drain-to-Source Voltage (V)
Gate Charge On-Resistance vs. Junction Temperature
4.5 1.8
VDS = 10 V VGS = 4.5 V
V GS - Gate-to-Source Voltage (V)
ID = 4.6 A 1.6 ID = 4.6 A
3.6
r DS(on) - On-Resistance (W)
1.4
(Normalized)
2.7
1.2
1.8
1.0
0.9
0.8
0.0 0.6
0 4 8 12 16 -50 -25 0 25 50 75 100 125 150
Qg - Total Gate Charge (nC) TJ - Junction Temperature (_C)
www.vishay.com Document Number: 70814
4 S-59522--Rev. C, 30-Nov-98
Si6924EDQ
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage
20 0.08
r DS(on) - On-Resistance ( W )
10 0.06
I S - Source Current (A)
TJ = 150_C
ID = 4.6 A
0.04
TJ = 25_C
0.02
1 0.00
0 0.4 0.6 0.8 1.0 1.2 0 1 2 3 4 5
VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V)
Threshold Voltage Single Pulse Power
0.2 30
ID = 250 mA
0.1 25
V GS(th) Variance (V)
-0.0 20
Power (W)
-0.1 15
-0.2 10
-0.3
5
-0.4 0
-50 -25 0 25 50 75 100 125 150 0.01 0.1 1 10 30
TJ - Temperature (_C) Time (sec)
Normalized Thermal Transient Impedance, Junction-to-Ambient
2
1
Duty Cycle = 0.5
Normalized Effective Transient
Thermal Impedance
0.2
Notes:
0.1
PDM
0.1
0.05
t1
t2
t1
1. Duty Cycle, D =
t2
0.02
2. Per Unit Base = RthJA = 115_C/W
3. TJM - TA = PDMZthJA(t)
Single Pulse 4. Surface Mounted
0.01
10- 4 10- 3 10- 2 10- 1 1 10 100 600
Square Wave Pulse Duration (sec)
Document Number: 70814 www.vishay.com
S-59522--Rev. C, 30-Nov-98 5
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Revision: 18-Jul-08 1