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ICs for Consumer Electronics
SDA 545XOTP
Programming Manual
Version 1.0
2. Dec. 1998
SDA 545XOTP
Revision History: Previous Version Page Page (in previous (in new Version) Version) V1.0 Current Version: 12.98
Edition 12.98 This edition was realized using the software system FrameMaker®. Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München © Siemens AG 12/3/98. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.
Programming Interface SDA 545XOTP
1
Introduction
This OTP programming specification defines the basic access mechanisms for the C500 OTP derivatives. It especiallly covers the first OTP TVText product, the SDA 545XOTP. Figure 1 shows all signals of the SDA 545XOTP which are used for OTP programming. VDD/VDDA VSS/VSSA
SDA 545XOTP Port 0 A0-A7/ A8-A15 Port 1 P4.2 P4.3 P4.7 P3.3 P4.0 RST N.C.(PSEN) P3.2 P3.0 Iref IREF P3.1 D0-D7 EA/VPPpixel EA/VPPprogr. PROG PRD "0" PSEN PSEL PMSEL0 PMSEL1
PALE
XTAL1 XTAL2
Figure 1 : Programming Mode Configuration (in normal working mode 'N.C.' means 'not connected'. This pin may not be connected to anything!) Port 0 provides the bidirectional data lines. Port 1 provides the multiplexed address inputs. The address information at port 1 is latched with the signal PALE. For basic programming mode selection the inputs RST, PSEN, PROG, PRD, PALE, PSEL, and EA/VPPx are used. EA/VPPpixel is used for programming the character ROM, EA/VPPprogr is used for programming the program ROM. Further, the inputs PMSEL1,PMSEL 0 are required to select the access types (e.g. program/verify data, write lock bits, ....) in the programming mode as they are defined in table 2. During OTP programming mode VDD, VSS, VDDA, VSSA, IREF, XTAL1 and XTAL2 must be applied to the SDA 545XOTP. The 11.5V external programming voltages are input through the EA/VPPx pin.
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2
Pin Description
The following table 1 contains the functional description of all SDA 545XOTP pins which are required for OTP memory programming. Table 1 : Pin Definitions and Functions in Parallel Programming Mode Symbol VSS, VSSA VDD, VDDA IREF EA/VPPpixel Pin Number S-DIP-52 P-MQFP-64 10, 35, 24 11, 37, 28 29 38 2, 3, 35, 36, 54 5, 6, 37, 38, 58 59 7 Circuit ground potential must be applied in programming mode. Power supply terminal must be applied in programming mode. Reference Current must be applied in programming mode. Programming voltage for character ROM This pin must be at 11.5V voltage level (VPP) during programming of a character OTP memory cell/byte/ bit. During read/verify access modes VIH1 must be applied to this pin. This pin is also used for basic programming mode selection and the selection, which of the OTP ROMs is to be used - program or character. During this selection phase a low level must be applied to EA/VPPpixel and a high level must be applied to EA/VPPprogr. Programming voltage for program ROM This pin must be at 11.5V voltage level (VPP) during programming of a program OTP memory cell/byte/bit. During read/verify access modes VIH1 must be applied to this pin. This pin is also used for basic programming mode selection and the selection, which of the OTP ROMs is to be used - program or character. During this selection phase a low level must be applied to EA/ VPPprogr and a high level must be applied to EA/ VPPpixel. I/O Function
EA/VPPprogr 39
8
D7-D0
2-9
26-31, 33, 34 44, 46, 47, 48, 50, 51, 52, 53 42
I/O Data lines 0-7 During programming mode, data bytes are transfered via the bidirectional port 0 lines. I Address lines P1.0-1.7 are used for the address input lines A0-A7 and A8-A15. A8-A15 must be latched in programming/verify mode using the signal PALE. Reset This input must be at static "0" level (active) during the whole programming mode.
A7-A0, A15-A8
16-23
RST
15
I
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Table 1 : Pin Definitions and Functions in Parallel Programming Mode (cont'd) Symbol PSEN 26 Pin Number S-DIP-52 P-MQFP-64 56 I Program store enable This input must be at static "0" level during the whole programming mode. In normal working mode this pin must be unconnected! Basic programming mode select This input is used for the basic programming mode selection and must be switched according figure 4. Programming mode write strobe This input is used in programming mode as a write strobe. During basic programming mode selection a low level must be applied to PROG.At a program operation in Latched Mode, PROG (falling edge) also latches the adresses A0-A7. Programming mode read strobe This input is used for read access control for OTP verify, read signature, read lock bits, and test mode operations. At a verify operation in Latched Mode, PRD (falling edge) also latches the addresses A0-A7. Programming address latch enable PALE is used to latch the high address lines. The high address lines must satisfy a setup and hold time to/ from the falling edge of PALE. PALE must be at low level when the logic level of PMSEL1,0 is changed. Programming mode selection pins These pins are used to select the different programming modes. If PALE is required for an access operation, PMSEL1,0 must satisfy a setup time to the rising edge of PALE. When the logic level of PMSEL1,0 is changed, PALE must be at low level. External Clock must be applied in programming mode I/O Function
PSEL
44
15
I
PROG
46
18
I
PRD
36
4
I
PALE
14
41
I
PMSEL0 PMSEL1
52 1
24 25
I I
XTAL1 XTAL2
12 13
39 40
I 0
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PMSEL1 (P3.1) D7 (P0.7) D6 (P0.6) D5 (P0.5) D4 (P0.4) D3 (P0.3) D2 (P0.2) D1 (P0.1) D0 (P0.0) VSS VDD XTAL1 XTAL2 PALE (P4.0) RST A7/A15 (P1.7) A6/A14 (P1.6) A5/A13 (P1.5) A4/A12 (P1.4) A3/A11 (P1.3) A2/A10 (P1.2) A1/A9 (P1.1) A0/A8 (P1.0) VSSA FIL3 PSEN (N.C.)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41
PMSEL0 (P3.0) COR BLAN B G R PROG (VS/P4.7) HS/SC PSEL P3.4 P3.5 P3.6 P3.7 EA/VPPprogr (P4.3) EA/VPPpixel (P4.2) VDD PRD VSS P2.0 P2.1 P2.2 P2.3 CVBS1 IREF VDDA CVBS2 (P3.3) (P3.2)
SDA 545XOTP
40 39 38 37 36 35 34 33 32 31 30 29 28 27
Figure 2 : Pin Configuration SDA 545XOTP in Programming Mode (Top View), 'N.C.' means that pin has to be unconnected (Pin 26 in normal working mode)!
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48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 N.C. A3/A11(P1.3) 50 A2/A10(P1.2) 51 A1/A9 (P1.1) A0/A8 (P1.0) VSSA FIL3 PSEN (N.C.) CVBS2 VDDA IREF CVBS1 P2.3 P2.2 P2.1 N.C. 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P2.0 VSS VSS PRD (P3.3) VDD VDD EA/VPPpixel (P4.2) EA/VPPprogr(P4.3) P3.7 P3.6 N.C. N.C. P3.5 P3.4 (P3.2) PSEL HS/SC 32 N.C. 31 D2 (P0.2) 30 D3 (P0.3) 29 D4 (P0.4) 28 D5 (P0.5) 27 D6 (P0.6) 26 D7 (P0.7) 25 PMSEL1(P3.1) 24 PMSEL0(P3.0) 23 COR 22 BLAN 21 B 20 G 19 R 18 PROG(VS/P4.7) 17 N.C.
Figure 3 : Pin Configuration SDA 545XOTP M in Programming Mode (Top View), 'N.C.' means that pin has to be unconnected (especially Pin 56 in normal working mode)!
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A4/A12 (P1.4) A5/A13 (P1.5) A6/A14 (P1.6) N.C. A7/A15 (P1.7) N.C. RST PALE (P4.0) XTAL2 XTAL1 VDD VDD VSS VSS D0 (P0.0) D1 (P0.1)
SDA 545XOTP M
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3
Programming Mode Selection
The selection for the OTP programming mode can be separated into two different parts : Basic programming mode selection Access mode selection With the basic programming mode selection the device is put into the mode in which it is possible to access the OTP through the programming interface logic. Further, after selection of the basic programming mode, each OTP access is executed by using one of the access modes. These access modes allow OTP byte program/verify, test mode register read/write operations, and programming lock byte access. 3.1 Basic Code Programming Mode Selection
PSEL PMSEL1,0 PROG '0' '0', '1'
RESET = '0' = VIL PSEN = '0' = VIL
PRD
'1'
VPP VIH1
EA/VPPprogr '0'
Figure 4 : Basic Code Programming Mode Selection, EA/VPPpixel = '1' The basic programming mode is selected by applying the following signal levels to dedicated pins: RST pin is set to '0' level and PSEN are set to '0' level; they must be at these static signal levels during the whole programming mode. PROG, PMSEL1 and EA/VPPprogr are set to '0' level; PMSEL0, PSEL, and PRD are set to '1' level; EA/VPPpixel is set to '1' PSEL is set to '0' level and must stay at '0' level during the whole programming mode; after this falling edge of PSEL the programming mode is selected PROG is set to '1' (inactive) level EA/VPPprogr and PMSEL1,0 can now be set to the voltage levels which are required for OTP access modes. With a falling edge of PSEL the logic state of PROG and EA/VPPprogr is internally latched. The selected OTP Model remains active until PSEL is raised again. These two signals are now used as
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programming write pulse signal (PROG) and as programming voltage input pin VPP. When EA/ VPPprogr is raised to VIH1 or VPP level, the access modes according table 2 can be activated. 3.1.1 Access Mode Selection Table 2 defines the access modes which are available in the code programming mode. Table 2 : Programming Access Modes - Selection Access Mode Program code byte of program ROM Verify code byte of program ROM Program lock bits of program ROM Verify/read lock bits of program ROM EA/ EA/ VPPpixel VPPprogr PROG 1 1 1 1 PRD 1 1 1 1 1 0 D1,D0 see table 4 PMSEL 1 1 0 1 Address (Port 1) A0-7 A8-15 Data (Port 0) D0-7
VPP VIH1 VPP VIH1
The access modes from the table above are basically selected by the two PMSEL1,0 lines. The PROG and PRD signal are the write and read strobe signals. Data is transfered at port 0 and addresses are applied to port 1. Depending on the selected access mode, addresses must be latched at port 1. 3.1.2 Program and Verify Code Bytes The program/verify code byte access mode is defined by PMSEL1,0 = '1','1'. It is initiated when the PMSEL1,0 = '1','1' is valid at the rising edge of PALE. In the program/verify code byte access mode a so called Page Mode timing is specified. In the Page Mode timing only the lower address byte must be latched at port 1. This is the standard timing which is used for programming and verifying the code bytes of the OTP memory. If subsequent OTP address locations are accessed with constant address information at the high address lines A8-15, A8-A15 must only be latched once per page at port 1 (page address mechanism). 3.1.2.1 Program Code Bytes
Figure 5 shows a typical Page Mode basic programming cycle .
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PMSEL1,0 A8A15
'1', '1'
Port 1
A0-A7
A0-A7
PALE D0-D7 D0-D7
Port 0 EA/VPPprogr PROG
VPP VIH1
PRD Figure 5 : Code Byte Programming Access Waveform (Page Mode), EA/VPPpixel = '1'
The following steps must be executed for programming of a code byte: 1. Program access mode has to be selected by setting PMSEL1,0 to '1', '1' and A8-A15 must be set. PALE must be activated (high pulse). PMSEL1,0 must fulfill a setup time to the rising edge of PALE and A8-A15 must satisfy a setup and hold time to the falling edge of PALE. 2. Addresses A0-A7 must be statically applied to port 1. 3. The code/character byte to be programmed must be applied to port 0. 4. EA/VPPprogr must be set to VPP (if it was not at VPP before), EA/VPPpixel is set to '1' 5. PROG is pulsed to low level for the OTP code byte programming. For multiple code byte programming, steps 2 to 5 are repeated. If the address lines A8-A15 must be updated, PALE must be activated for the latching of the new A8-A15 value (step 1). The programming voltage at EA/VPPprogr can be stable at VPP during multiple byte programming. Control, address, and data information as well as the programming voltage VPP must only be switched when the PROG and PRD signals are at high level. Step 1 must be always executed if a different access mode has been executed prior to the actual programming cycle or if the value of the high address A8-A15 is different to the high address of the last programming/verify mode access. Pin EA/VPPprogr must be raised from VIH1 to VPP at least before PROG becomes active for the first time.
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3.1.2.2
Verify Code Bytes
Figure 6 shows a typical Page Mode basic verify cycle.
PMSEL1,0 A8A15
'1', '1'
Port 1
A0-A7
A0-A7
PALE D0-D7 D0-D7
Port 0 EA/VPPprogr PROG
VIH1
PRD Figure 6 : Code Byte Verify Access Waveform (Page Mode), EA/VPPpixel = '1' The following steps must be executed for verifying of a code byte: The appropriate OTP module has to be selected according to Fig. 4 1. EA/VPPprogr is set to VIH1, EA/VPPpixel is set to '1'. 2. Verify access mode has to be selected by setting PMSEL1,0 to '1', '1' and A8-A15 must be set. PALE must be activated (high pulse). PMSEL1,0 must fulfill a setup time to the rising edge of PALE and A8-A15 must satisfy a setup and hold time to the falling edge of PALE. 3. Addresses A0-A7 must be statically applied to port 1. 4. PRD is set to low level. 5. Read data becomes available at port 0 and can be latched with the rising edge of PRD. For multiple verify operations, steps 3 to 5 are repeated. If the address lines A8-A15 must be updated, PALE must be activated for the latching of the new A8-A15 value (step 2). Control and address information as well as the programming voltage VPP must only be switched when the PRD or PROG signals are at high level. Step 2 must be always executed if a different access mode has been executed prior to the actual programming cycle or if the value of the high address A8-A15 is different to the high address of the last programming/verify mode access.
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Figure 7 shows a waveform example of the program/verify mode access in Page Mode. Example 1 : Programming addresses 3FD to 400, verify addresses 400 and 3FD PMSEL1,0 PALE
(Address) 3FD
03 FD
'1', '1'
3FE
FE
3FF
FF 04
400
00
400
00 03
3FD
FD
Port 1 Port 0 PROG PRD
Data 1
Data 2
Data 3
Data 4
Data 4
Data 1
VPP
EA/VPPprogr
VIH1
Figure 7 : Code Byte Programming Access Mode Waveform - Page Mode, EA/VPPpixel = '1' 3.2 Basic Character Programming Mode Selection
In the main programming the character ROM is done in the same way as programming the program ROM. Mainly, EA/VPPpixel is exchanged with EA/VPPprogram. The lock bits have slightly different functionality.
PSEL PMSEL1,0 PROG '0' '0','1'
RESET = '0' = VIL PSEN = '0' = VIL
PRD
'1'
VPP VIH1
EA/VPPpixel '0'
Figure 8 : Basic Character Programming Mode Selection, EA/VPPprogr = '1'
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The basic programming mode is selected by applying the following signal levels to dedicated pins: RST pin is set to '0' level and PSEN are set to '0' level; they must be at these static signal levels during the whole programming mode. PROG, PMSEL1 and EA/VPPpixel are set to '0' level; PMSEL0 , PSEL, and PRD are set to '1' level; EA/VPPprogr is set to '1' PSEL is set to '0' level and must stay at '0' level during the whole programming mode; after this falling edge of PSEL the programming mode is selected PROG is set to '1' (inactive) level EA/VPPpixel and PMSEL1,0 can now be set to the voltage levels which are required for OTP access modes. With a falling edge of PSEL the logic state of PROG and EA/VPPpixel is internally latched. These two signals are now used as programming write pulse signal (PROG) and as programming voltage input pin VPP. When EA/VPPpixel is raised to VIH1 or VPP level, the access modes according table 2 can be activated.The selected OTP Model stay selected until PSEL is raised again. 3.2.1 Access Mode Selection Table 2 defines the access modes which are available in the character programming mode. Table 3 : Programming Access Modes - Selection Access Mode Program code byte of character ROM Verify code byte of character ROM Program lock bits of character ROM Verify/read lock bits of character ROM EA/ EA/ VPPpixel VPPprogr PROG PRD 1 1 1 1 1 0 D1,D0 see table 4 PMSEL 1 1 0 1 Address (Port 1) A0-7 A8-15 Data (Port 0) D0-7
VPP VIH1 VPP VIH1
1 1 1 1
The access modes from the table above are basically selected by the PMSEL1,0 lines. The PROG and PRD signal are the write and read strobe signals. Data is transfered at port 0 and addresses are applied to port 1. Depending on the selected access mode, addresses must be latched at port 1. 3.2.2 Program and Verify Character Bytes The program/verify character byte access mode is defined by PMSEL1,0 = '1', '1'. It is initiated when the PMSEL0 = '1', '1' is valid at the rising edge of PALE. Only the lower address byte must be latched at port 1. This is the timing which is used for programming and verifying the code bytes of the OTP memory. If subsequent OTP address locations are accessed with constant address information at the high address lines A8-15, A8-A15 must only be latched once per page at port 1 (page address mechanism).
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3.2.2.1
Program Character Bytes
Since each line of one character consists of 12 bits, it is split into two bytes and as such has two addresses. The first character byte (having an even address) contains the first 8 bits of the character line, the second character byte (having an odd address) contains the remaining four bits at its four LSBs. The four MSBs must be '0'. Due to that, it is strongly recommended to first program all character bytes and to perform the verification afterwards. To reduce programming time, every second programming pulse width (at even address) can be reduced to 1µs instead of tPWW. Figure 9 shows a typical Page Mode basic programming cycle of one OTP character byte.
PMSEL1,0 A8A15
'1', '1'
Port 1
A0-A7
PALE D0-D7 D0-D7
Port 0 EA/VPPpixel PROG
VPP VIH1
PRD Figure 9 : Character Byte Programming Access Waveform (Page Mode), EA/VPPprogr = '1'
The following steps must be executed for programming of a character byte: 1. Program access mode has to be selected by setting PMSEL1,0 to '1', '1' and A8-A15 must be set. PALE must be activated (high pulse). PMSEL1,0 must fulfill a setup time to the rising edge of PALE and A8-A15 must satisfy a setup and hold time to the falling edge of PALE. 2. Addresses A0-A7 must be statically applied to port 1. 3. The code/character byte to be programmed must be applied to port 0. 4. EA/VPPpixel must be set to VPP (if it was not at VPP before), EA/VPPprogr is set to '1' 5. PROG is pulsed to low level for the OTP code byte programming. For multiple code byte programming, steps 2 to 5 are repeated. If the address lines A8-A15 must be updated, PALE must be activated for the latching of the new A8-A15 value (step 1). The programming voltage at EA/VPPpixel can be stable at VPP during multiple byte programming. Control,
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address, and data information as well as the programming voltage VPP must only be switched when the PROG and PRD signals are at high level. Step 1 must be always executed if a different access mode has been executed prior to the actual programming cycle or if the value of the high address A8-A15 is different to the high address of the last programming/verify mode access. Pin EA/VPPpixel must be raised from VIH1 to VPP at least before PROG becomes active for the first time. 3.2.2.2 Verify Character Bytes
Figure 10 shows a typical Page Mode basic character verify cycle.
PMSEL1,0 A8A15
'1', '1'
Port 1
A0-A7
A0-A7
PALE D0-D7 D0-D7
Port 0 EA/VPPpixel PROG
VIH1
PRD Figure 10 : Character Byte Verify Access Waveform (Page Mode), EA/VPPprogr = '1' The following steps must be executed for verifying of a code or character byte, respectively: The appropriate OTP module has to be selected according to Fig. 4 1. EA/VPPpixel is set to VIH1, EA/VPPprogr is set to '1'. 2. Verify access mode has to be selected by setting PMSEL1,0 to '1', '1' and A8-A15 must be set. PALE must be activated (high pulse). PMSEL1,0 must fulfill a setup time to the rising edge of PALE and A8-A15 must satisfy a setup and hold time to the falling edge of PALE. 3. Addresses A0-A7 must be statically applied to port 1. 4. PRD is set to low level. 5. Read data becomes available at port 0 and can be latched with the rising edge of PRD. For multiple verify operations, steps 3 to 5 are repeated. If the address lines A8-A15 must be updated, PALE must be activated for the latching of the new A8-A15 value (step 2). Control and address information as well as the programming voltage VPP must only be switched when the PRD or PROG signals are at high level. Step 2 must be always executed if a different access mode has
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been executed prior to the actual programming cycle or if the value of the high address A8-A15 is different to the high address of the last programming/verify mode access. Note: It is strongly recommended to first program all character bytes and to perform the verification afterwards, because each character line is written in two steps as described in 3.2.2.1. 3.2.3 Access of Lock Bits The SDA 545XOTP has two programmable lock bits which, when programmed according table 4 or table 5, protect the on-chip memory. Erasing the EPROM also erases the program lock bits, returning the OTP device to full functionality. Obviously, the erasing of the lock bits is no more possible when the OTP device is mounted in a plastic package. The state of the lock bits can also be read. Table 4 : Lock Bit Protection Types for Program ROM Lock Bits at D1,D0 D1 1 0 D0 1 0 Protection Protection Type Level Level 0 Level 3 No OTP lock feature enabled. OTP programming and verification is disabled.
Table 5 : Lock Bit Protection Types for Character ROM Lock Bits at D1,D0 D1 1 0 D0 1 0 Protection Protection Type Level Level 0 Level 3 No OTP lock feature enabled. OTP programming and verification is disabled.
Note : '1' means that the lock bit is unprogrammed. '0' means that lock bit is programmed. Figure 11 and figure 12 show the waveform of a lock bit write/read access. When a protection level has been activated by programming of the lock bits, the basic programming mode must be left for activation of the protection mechanisms. This means, after the activation of a protection level further OTP program/verify operations are still possible if the basic programming mode is maintained.
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PMSEL1,0 PALE Port 0
(D1,D0)
'1', '0'
1,0
PROG PRD
VPP
EA/VPPprogr
VIH1
The example shows the programming of a protection level 3.
Figure 11 : Write Program ROM Lock Bit Waveform
PMSEL1,0 PALE Port 0
(D1,D0)
'1', '0'
1,0
PROG PRD
VPP
EA/VPPpixel
VIH1
The example shows the programming of a protection level 3.
Figure 12 : Write Character ROM Lock Bit Waveform
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4
Character ROM Organization
Since the organization of pixel data inside the ROM differs from former TVText-versions (SDA 525x), it is explained in this chapter. A further explanation is necessary due to the splitting of the 12 pixel per character-line into two 8-bit write cycles. 4.1 Basics of the ROM Organization
The character ROM consists of 4096 words of 12 bit each. Since each character has 10 lines, a maximum of 409 characters can be stored. There are six basic blocks of character data: 1.) the OSD64 character set, 2.) the G0 character set, 3.) the OSD character set, 4.) the Extended West character set, 5.) the Turkish character set, and 6.) the Extended East character set. The mosaic graphics character set is generated by hardware and, due to this, not included in the character ROM. The data format used is the same as in the former TVT-circuits (SDA 525x) based on ASCII (consisting of 0 and 1). To use this data for the OTP version, the order of data has to be changed, due to the linear addressing of the OTP-ROM and the character organization. In the first step, the character sets must be reordered, in the second step the 12b-words must be handled in a special way. 4.2 Order of the character sets inside the address space
The first step is a reordering of pixel data according to the following specification: 4.2.1 Order of the character sets in former ASCII-files (SDA525x) Address 000-01F 020-07F 080-09F 0A0-0FF 100-11F 120-13F 140-15F 160-17F 180-19F 1A0-1FF Character Set empty G0 OSD Extended West empty Mosaic Graphic 1 OSD64 Mosaic Graphic 2 Turkish Extended East
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4.2.2 New Order of the character sets in ASCII-file (SDA545x) Address 000-01F 020-07F 080-09F 0A0-0FF 100-11F 120-17F Character Set OSD64 G0 (as before) OSD Extended West (as before) Turkish Extended East
The mosaic graphic character sets are generated by hardware and, by this, are not included neither in the ROM nor in the pixel data file. 4.3 Organization of Words inside the Address Space
After reordering of the character sets the pixel lines must be ordered. This is necessary because each character has 10 lines. In the former TVT-Versions each character line was addressed by ,,character-address . line-number". The address mapping was performed by hardware. In the OTPversion the line addresses must be scrambled before programming to exploit the full linear address space. This scrambling must be done as described in the following:
CA: Character address (9 bit); LA: line address (4 bit); C-symbols are used (||: or; !: not) Case 1: Valid for character adresses 0dec to 255dec (000000000b to 011111111b; 000h to 0FFh): Character Line Address = LA3; LA2; LA1; LA0; CA7; CA6; CA5; CA4; CA3; CA2; CA1; CA0 Case 2: Valid for character adresses 256dec to 383dec (100000000b to 101111111b; 100h to 17Fh): Character Line Address = 1; LA3 || LA2; !LA2; LA1; LA0; CA6; CA5; CA4; CA3; CA2; CA1; CA0 4.4 Order of MSB and LSB
The MSB represents the leftmost pixel, the LSB represents the rightmost pixel.
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Programming Interface SDA 545XOTP
5 5.1
Device Specification for Programming Mode Programming Mode DC Characteristics
VDD = 5 V ± 5%; VSS = 0 V
Parameter Symbol
TA = 0 to 70 °C
Limit Values min. max. 0.2 VDD + 0.9 0.8 VDD 0.7 VDD 0.6 VDD 11 -0.5 Unit V V V V V mA V Test Condition
Input high voltage (except XTAL1, VIH EA/VPPx, RESET and CTRAP) Input high voltage to EA/VPPx Input high voltage to XTAL1 Input high voltage to RESET and CTRAP Programming voltage Supply current at EA/VPPx
VDD + 0.5 VDD + 0.5 VDD + 0.5 VDD + 0.5
12 30 0.8
VIH1 VIH1 VIH2 VPP ICCP VIL
L-input voltage
Note : All other DC characteristics (e.g. VOL, VOH etc.) are defined in the C504 Data Sheet 05.96. 5.2 Programming Mode AC Characteristics
VDD = 5 V ± 5 %; VPP = 11.5 V ± 5 %;
Parameter ALE pulse width PMSEL setup to ALE rising edge
TA = 25 °C ± 10 °C
Symbol min. Limit Values max. 75 20 ns ns ns ns ns ns µs ns ns ns ns ns 35 10 10 10 100 0 10 10 100 100 100 Unit
tPAW tPMS tPAS tPAH tPCS tPCH tPMS tPMH tPWW tPRW tPAD tPRD
20
Address setup to ALE, PROG, or PRD falling edge Address hold after ALE, PROG, or PRD falling edge Address, data setup to PROG or PRD Address, data hold after PROG or PRD PMSEL setup to PROG or PRD PMSEL hold after PROG or PRD PROG pulse width for program code byte PROG pulse width for test register write PRD pulse width Address to valid data out PRD to valid data out
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Programming Manual Rev. 1.0
Programming Interface SDA 545XOTP
Parameter Data hold after PRD Data float after PRD
Symbol min.
Limit Values max. 20 0 1 100
Unit ns ns µs ns
tPDH tPDF
PROG high between two consecutive PROG tPWH1 low pulses PRD high between two consecutive PRD low pulses
tPWH2
tPAW
PALE
tPMS
PMSEL1,0 '1', '1'
tPAS
Port 1
(Latched Mode)
tPAH
A8-15
A0-7
tPAS
Port 1
(Page Mode)
tPAH
A0-7
A8-15
Port 0
D0-7
tPWW
PROG
tPWH1
tPCS
tPCH
Notes : PRD must be high during a programming write cycle Latched Mode timing of port 1 is only for test purposes.
Figure 13 : Programming Code Byte - Write Cycle Timing
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Programming Interface SDA 545XOTP
tPAW
PALE
tPMS
PMSEL1,0 '1', '1'
tPAS
Port 1
(Latched Mode)
tPAH
A8-15
A0-7
tPAS
Port 1
(Page Mode)
tPAH
A0-7
A8-15
tPAD
Port 0 D0-7
tPDH
tPRD
PRD
tPDF tPWH2
tPCS tPRW tPCH
Notes : PROG must be high during a programming read cycle Latched Mode timing of port 1 is only for test purposes.
Figure 14 : Verify Code Byte - Read Cycle Timing
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Programming Interface SDA 545XOTP
PMSEL1,0
'1', '0'
Port 0
D0, D1
tPCS tPMS
PROG
tPCH tPMH
tPWW
PRD
Note : PALE should be low during a lock bit write cycle
Figure 15 : Lock Bit Access Timing
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Programming Interface SDA 545XOTP
PMSEL1,0
'0', '0'
'0', '0'
Port 1
Address
Address
tPCH
Port 0 D0-7 D0-7
tPCS tPMS
PROG
tPCH tPMH tPCS tPWW tPMS tPRD tPDH tPDF tPMH
PRD
tPRW
Note : PALE should be low during a test register read/write cycle
Figure 16 : Test Register Access - Write/Read Timing
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