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A B C D E
1 1
U1 - KAL00
Compal Confidential
2 2
Schematics Document
AMD S1g2/ ATI RS780M / SB700
Wednesday, January 16, 2008
3 3
4 4
Security Classification Compal Secret Data
Issued Date 2007/12/12 Deciphered Date 2008/12/12 Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom U1 LA-4381P 0.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sheet 1 of 41
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A B C D E
Compal confidential
Project Code: ANRKAL0000(KAL00) Thermal Sensor Clock Generator
File Name : LA-4381P ADM1032ARM SLG8SP626VTR AMD S1g2 CPU DDR-2 DDR2-SO-DIMM X2
ZZZ1
/ICS9LPRS476BKLFT Turion64 x2 TLxx / Sempron
PCB P/N: page 8,9
1 1
page 6 page 14 page 4,5,6,7
Daul Channel DDR-2
15W_PCB
Up to 800MHz
CRT BUS A-->JDIM2-->UPPER SLOT
HT 16x16 1.6G~3.2GHZ
BUS B-->JDIM1-->LOWER SLOT
page 15
LCD CONN ATI-RS780M
page 15
HDMI CONN page 10,11,12,13
page 16
PCI EXPRESS A-Link Express
4 x PCIE
HD-Interface Audio CKT Audio Jack
2 Broadcom Express Card Mini Card ALC269 2
BCM5784M page 27 page 28
page 25
(New Card) WLAN
page 24 page 24
ATI-SB700 USB 2.0 USB conn x 4
page 32
RJ45 CONN Felica Conn
page 31
page 26 USB 2.0
PCI BUS page 17,18,19,20,21 Hyper Flash
IDE page 23
Crad Reader Controller
Ricoh R5C833
page 22 LPC BUS SATA GEN2
SATA ODD Conn.
3
page 23 3
Media Card
SATA GEN2
page 22 SATA HDD Conn.
page 23
Power On/Off CKT.
page 33
ENE KB926
DC/DC Interface CKT. RTC CKT. page 29
page 34 page 17
Int. KBD
Power Circuit DC/DC Power OK CKT.
page 31
page 35~42 page 33
4
Touch Pad 4
CONN.page 31 SPI BIOS
page 29
Security Classification Compal Secret Data
Issued Date 2007/12/12 Deciphered Date 2008/12/12 Title
Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom U1 LA-4381P 0.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 16, 2008 Sheet 2 of 41
A B C D E
A B C D E
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S4/ S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) ON ON ON S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. ON ON ON
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE0,1 Core voltage for CPU ON OFF OFF
+VDDNB +0.8V~1.1V CPU NBVDD ON ON OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.2V_HT 1.2V switched power rail ON OFF OFF
+0.9V 0.9V switched power rail for DDR terminator ON ON OFF
+1.2VALW 1.2V always on power rail ON ON ON Board ID Table for AD channel
+1.5VS 1.5V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+1.8VS 1.8V switched power rail ON OFF OFF Ra / Rc 100K +/- 5%
+1.8V 1.8V power rail for DDR ON ON OFF Board ID Rb / Rd V AD_BID min V AD_BID typ V AD_BID max
+3VALW 3.3V always on power rail ON ON ON 0 0 0 V 0 V 0 V
+3VS 3.3V switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+5VALW 5V always on power rail ON ON ON 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+5VS 5V switched power rail ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+RTCVCC RTC power ON ON ON 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V
2 2
BOARD ID Table BTO Option Table
External PCI Devices Board ID PCB Revision BTO Item BOM Structure
Device IDSEL# REQ#/GNT# Interrupts 0 0.1 (U1 ES1)
CardBus AD21 0 PIRQE/PIRQF/PIRQG 1 0.2 (U1 ES2)
2 0.3 (U1 PP)
3 0.4 (U1 PPR)
4 1.0 (U1 IRT)
5
6
7
EC SM Bus1 address EC SM Bus2 address
3 3
Device Address Device Address
Smart Battery 0001 011X b? ADM1032 1001 110X b?
EEPROM(24C16/02) 1010 000X b?
(24C04) 1011 000Xb?
SB700 SM Bus address
Device Address
Clock Generator ( 1101 001Xb?
ICS9LPRS476BKLFT)
DDRII DIMM0 1001 000Xb?
DDRII DIMM1 1001 010Xb?
4 4
Security Classification Compal Secret Data
Issued Date 2007/12/12 Deciphered Date 2008/12/12 Title
Notes
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom U1 LA-4381P 0.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 16, 2008 Sheet 3 of 41
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5 4 3 2 1
H_CADIP[0..15] H_CADOP[0..15]
<10> H_CADIP[0..15] H_CADOP[0..15] <10>
H_CADIN[0..15] H_CADON[0..15]
<10> H_CADIN[0..15] H_CADON[0..15] <10>
+1.2V_HT close to CPU Socket
+1.2V_HT
D
1.5A D
1 1 1 1 1 1 1
JCPU1A
C523 C543 C544 C539 C522 C526 C521
180P_0402_50V8J~N
180P_0402_50V8J~N
0.22U_0603_10V7K
0.22U_0603_10V7K
4.7U_0805_6.3V6K~N
4.7U_0805_6.3V6K~N
4.7U_0805_6.3V6K~N
D1 VLDT_A0 HT LINK VLDT_B0 AE2
2 2 2 2 2 2 2
D2 VLDT_A1 VLDT_B1 AE3
D3 VLDT_A2 VLDT_B2 AE4
D4 VLDT_A3 VLDT_B3 AE5
H_CADIP0 E3 AD1 H_CADOP0
H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP2 G3 AB1 H_CADOP2
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
H_CADIP3 G1 AA2 H_CADOP3
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
H_CADIP4 J1 W2 H_CADOP4
H_CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4
K1 L0_CADIN_L4 L0_CADOUT_L4 W3
H_CADIP5 L3 V1 H_CADOP5
H_CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5
L2 L0_CADIN_L5 L0_CADOUT_L5 U1
H_CADIP6 L1 U2 H_CADOP6
H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6
M1 L0_CADIN_L6 L0_CADOUT_L6 U3
H_CADIP7 N3 T1 H_CADOP7
H_CADIN7 L0_CADIN_H7 L0_CADOUT_H7 H_CADON7
N2 L0_CADIN_L7 L0_CADOUT_L7 R1
H_CADIP8 E5 AD4 H_CADOP8
H_CADIN8 L0_CADIN_H8 L0_CADOUT_H8 H_CADON8
F5 L0_CADIN_L8 L0_CADOUT_L8 AD3
H_CADIP9 F3 AD5 H_CADOP9
H_CADIN9 L0_CADIN_H9 L0_CADOUT_H9 H_CADON9
F4 L0_CADIN_L9 L0_CADOUT_L9 AC5
H_CADIP10 G5 AB4 H_CADOP10
H_CADIN10 L0_CADIN_H10 L0_CADOUT_H10 H_CADON10
H5 L0_CADIN_L10 L0_CADOUT_L10 AB3
H_CADIP11 H3 AB5 H_CADOP11
C H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11 C
H4 L0_CADIN_L11 L0_CADOUT_L11 AA5
H_CADIP12 K3 Y5 H_CADOP12
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12
K4 L0_CADIN_L12 L0_CADOUT_L12 W5
H_CADIP13 L5 V4 H_CADOP13
H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
H_CADIP14 M3 V5 H_CADOP14
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 L0_CADIN_L14 L0_CADOUT_L14 U5
H_CADIP15 N5 T4 H_CADOP15
H_CADIN15 L0_CADIN_H15 L0_CADOUT_H15 H_CADON15
P5 L0_CADIN_L15 L0_CADOUT_L15 T3
H_CLKIP0 J3 Y1 H_CLKOP0
<10> H_CLKIP0 L0_CLKIN_H0 L0_CLKOUT_H0 H_CLKOP0 <10>
H_CLKIN0 J2 W1 H_CLKON0
<10> H_CLKIN0 L0_CLKIN_L0 L0_CLKOUT_L0 H_CLKON0 <10>
H_CLKIP1 J5 Y4 H_CLKOP1
<10> H_CLKIP1 L0_CLKIN_H1 L0_CLKOUT_H1 H_CLKOP1 <10>
H_CLKIN1 K5 Y3 H_CLKON1
<10> H_CLKIN1 L0_CLKIN_L1 L0_CLKOUT_L1 H_CLKON1 <10>
H_CTLIP0 N1 R2 H_CTLOP0
<10> H_CTLIP0 L0_CTLIN_H0 L0_CTLOUT_H0 H_CTLOP0 <10>
H_CTLIN0 P1 R3 H_CTLON0
<10> H_CTLIN0 L0_CTLIN_L0 L0_CTLOUT_L0 H_CTLON0 <10>
H_CTLIP1 P3 T5 H_CTLOP1
<10> H_CTLIP1 L0_CTLIN_H1 L0_CTLOUT_H1 H_CTLOP1 <10>
H_CTLIN1 P4 R5 H_CTLON1
<10> H_CTLIN1 L0_CTLIN_L1 L0_CTLOUT_L1 H_CTLON1 <10>
FOX_PZ6382A-284S-41F_TURION
+5VS
FAN1 Control and Tachometer
1
D27
1SS355TE-17_SOD323-2 @
B @ B
2
2 1
D26 BAS16_SOT23-3
C541
10U_0805_10V4Z~N
2 1
@ +5VS
C527 @
1000P_0402_50V7K~N 1 2
2 1 C545 10U_0805_10V4Z~N
@
U25
1 VEN GND 8
2 VIN GND 7
FAN1_POWER 3 6
EN_DFAN1 VO GND
<28> EN_DFAN1 4 VSET GND 5
G993P1UF_SOP8
+3VS
40mil JFAN1
1
1
R364 2
10K_0402_5% 3
4 G
5 G
2
ACES_85205-0300N~N
<28> FAN_SPEED1
CONN@
2
C540
FAN1
A A
0.01U_0402_16V7K
1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/12/12 Deciphered Date 2008/12/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Griffin HT I/F & FAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom U1 LA-4381P 0.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 16, 2008 Sheet 4 of 41
5 4 3 2 1
A B C D E
VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
Processor DDR2 Memory Interface
+0.9V
0.75A
JCPU1B JCPU1C
MEM:DATA
<9> DDR_B_D[63..0] DDR_A_D[63..0] <8>
D10 W10 DDR_B_D0 C11 G12 DDR_A_D0
VTT1 MEM:CMD/CTRL/CLK VTT5 DDR_B_D1 MB_DATA0 MA_DATA0 DDR_A_D1
KEEP TRACE TO RESISTORS C10 VTT2 VTT6 AC10 A11 MB_DATA1 MA_DATA1 F12
B10 AB10 DDR_B_D2 A14 H14 DDR_A_D2
4 LESS THAN 1" FROM CPU PIN VTT3 VTT7 DDR_B_D3 MB_DATA2 MA_DATA2 DDR_A_D3 4
AD10 VTT4 VTT8 AA10 B14 MB_DATA3 MA_DATA3 G14
+1.8V A10 DDR_B_D4 G11 H11 DDR_A_D4
VTT9 MB_DATA4 MA_DATA4
1 R346 2 39.2_0603_1% M_ZP AF10 MEMZP
DDR_B_D5 E11 MB_DATA5 MA_DATA5 H12 DDR_A_D5
1 R353 2 39.2_0603_1% M_ZN AE10 MEMZN VTT_SENSE Y10 1 R64 2 VTT_SENSE_FB TP6 DDR_B_D6 D12 MB_DATA6 MA_DATA6 C13 DDR_A_D6
0_0402_5% DDR_B_D7 A13 E13 DDR_A_D7
TP22 DDR_B_D8 MB_DATA7 MA_DATA7 DDR_A_D8
H16 RSVD_M1 MEMVREF W17 +CPU_M_VREF