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5 4 3 2 1
THERMAL YONAH CLK GEN
SENSEER uFCPGA 478PIN
PAGE 2
PAGE 5 PAGE 3,4
D AGTL+ D
FSB_533/667MHz
4X Data VCC3M/VCC5M
2X Address (MAX1901)
PAGE 41
LVDS
LCD PAGE 15
SO-DIMM DRAM
Dual Channel DDR2 CALISTOGA
DIMMS*2 533/667MHz 945GM
2R5M/1R2AUX
(MAX8563)
PAGE 10 VGA
PAGE 6,7,8,9 CRT PAGE 16 PAGE 42
DMI VCC1R5M/VCC1R05B
(MAX1540)
PAGE 43
CARD BUS CARD BUS PCI BUS IDE Ultra 133/100/66 ODD
C SLOT PCI1520 PAGE 17 C
PAGE 26 PAGE 25
VCC1R8A/VCC0R9B
(MAX8632)
PAGE 44
ICH7-M SATA
PCIE-LAN HDD
RJ45 CON BCM5751 PAGE 27
PAGE 24 PAGE 22,23
VCCCPUCORE
(ADP3207)
HEAD PHONE PAGE 45,46,47
AD1981
AZALIA
MINI PCIE PCIE-LAN AMP(MAX9750) MIC JACK
CON
PAGE 19,20 PAGE21 CHARGER(MAX8765)
PAGE 18
PAGE 11,12,13 PAGE 38,39,40
MDC PAGE 25
BIOS SPI USB 2.0 PAGE 24
RJ11
PAGE 28
POWER SEQUENCE
B B
PAGE 51
USB PORT * 4
PAGE 14
LPC BUS
TCPA
PARALLEL SIO (Option) H8 PMH7
PORT PC87391 FWH PAGE 35
PAGE 31 PAGE 31 PAGE 27 PAGE 29 PAGE 33,34
FLOPPY PS2 KB FAN
PAGE 29 PAGE 31 PAGE 32 PAGE 5
LENOVO.PND
A
NB system design section A
Title
BLOCK DIAGRAM
Size Document Number
CustomWhistler Rev s1.3
Date: Friday, April 28, 2006 Sheet 1 of 52
"PROPERTY NOTE: this document contains information confidential and property to
LENOVO PND and shall not be reproduced or transferred to other documents or
disclosed to others or used for any purpose other than that for which it was obtained
without the expressed written consent of LENOVO PND."
5 4 3 2 1
5 4 3 2 1
VCC3B
VCC3B
FB2
1
FB1 1
MMZ1608S121AT
C1 C2 C3 C4 C5 MMZ1608S121AT C7 C8 C9 C10 C11
10uF/10V
10uF/10V
0.01UF/16V
C6
0.047UF/16V
0.047UF/16V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
0.1UF/10V
D R1 0.047UF/16V D
C12 C13 C14 C15 C16 C17
2.2 +-5% R2
10uF/10V 10uF/10V 0.047UF/16V 0.047UF/16V 0.1UF/10V 0.1UF/10V C18 2.2 +-5%
C_0805 C_0805 C_0402 C_0402 C_0402 C_0402 0.01UF/16V
C19
0.047UF/16V
C_0402
change 33ohm to 22ohm
43
54
48
60
10
17
29
36
65
CLK_CPU_BCLK R3 49.9 +-1%
REF_VDD
PCI_VDD1
PCI_VDD
48_VDD
SRC_VDD
SRC_VDD1
SRC_VDD2
CPU_VDD
GND
NS
CLK_CPU_BCLK# R5 49.9 +-1%
NS
R4 33 +-5% RN1 CLK_MCH_BCLK R7 49.9 +-1%
12 CLK48_USB BSEL0 R6 2.2K +-5% CPU0 NS
58 USB_48MHz/FS_A CPUCLKT0 39 1 2 CLK_CPU_BCLK 3
38 CPU#0 3 4 CLK_MCH_BCLK# R8 49.9 +-1%
BSEL1 CPUCLKC0 22X2 CLK_CPU_BCLK# 3 NS
63 FS_B/TEST_MODE
BSEL2 57 RN2
FS_C/TEST_SEL
CPUCLKT1 35 1 2 CLK_MCH_BCLK 6
16 34 3 4 CLK_PCIE_ICH R9 49.9 +-1%
12 STP_PCI# PCI_STOP# CPUCLKC1 CLK_MCH_BCLK# 6
40 22X2 RN3 NS
12 STP_CPU# CPU_TOP#
32 1 2 VCC3B CLK_PCIE_ICH# R12 49.9 +-1%
R10 0 +-5% CGCLK_SMB CPU2_ITP/SRC7 CPUCLK_ITP_166M 3 NS
10,27 SMB_CLK_3B 41 SCLK CPU2_ITP#/SRC7# 31 3 4 CPUCLK_ITP_166M# 3
R11 0 +-5% CGDAT_SMB 42
10,27 SMB_DATA_3B SDATA
2 22X2 R13 10K +-5%NS
CKGEN_EN# SRCCLKT0 NS R14 10K +-5%R_0603
45 CKGEN_EN# 56 VTT_PWRGD#/PD SRCCLKC0 3
4 R16 10K +-5% R15 10K +-5%R_0603
C OE0# VCC3B C
R_0603
VCC3B R17 10K +-5%R_0603 R912 1K +-1% R18 10K +-5%R_0603 PCIE_CLK_GBE# R20 49.9 +-1%
R19 33 +-5% PCIF0 53 64 R913 NS
12 PCLK_ICH7 ITP_EN/PCICLK_F0 OE1# CLKREQ_GBE# 22
12 0 +-5% NS PCIE_CLK_GBE R22 49.9 +-1%
OE3# CLKREQ_WLAN# 18 NS
OEA# 7 CLKREQ_MCH# 6
27,31 SIOCLK33M R21 24.9 +-1% 52 15 CLK_PCIE_MCH R23 49.9 +-1%
PCICLK0 OE6# NS
OEB# 24 CLKREQ_SATA# 12 CLK_PCIE_MCH# R26 49.9 +-1%
Package change from 0402 to 0603 R24 24.9 +-1% RN4 NS
35 LPCCLK_GA_33M
R25 24.9 +-1% 51 5 3 4
25 PCICLK_CB_33M PCICLK1 SRCCLKT1 PCIE_CLK_GBE 22
SRCCLKC1 6 1 2 PCIE_CLK_GBE# 22
22X2 CLK_SATA_ICH R29 49.9 +-1%
R28 24.9 +-1% 50 8 3 4 RN5 NS
33 LPCCLK_H8_33M PCICLK2 SRCCLKT2 DREFCLKSS_100M 6
9 1 2 CLK_SATA_ICH# R31 49.9 +-1%
SRCCLKC2 RN6 22X2 DREFCLKSS_100M# 6 NS
R27 24.9 +-1% 49 13 3 4
29 LPCCLK_FWH_33M PCICLK3 SRCCLKT3 CLK_PCIE_WLAN 18
14 1 2 CLK_PCIE_WLAN R32 49.9 +-1%
SRCCLKC3 22X2 RN7 CLK_PCIE_WLAN# 18 NS
RN8 CLK_PCIE_WLAN# R33 49.9 +-1%
SRCCLKT5 18 3 4 CLK_SATA_ICH 11
4 3 61 19 1 2 NS
6 DREFCLK_96M DOTT_96MHZ SRCCLKC5 CLK_SATA_ICH# 11
2 1 62 22X2 CPUCLK_ITP_166M R35 49.9 +-1%
6 DREFCLK_96M# DOTC_96MHZ
21 NS
R34 22 +-5% SRCCLKT6 CPUCLK_ITP_166M# R37 49.9 +-1%
12 CLK14_ICH7 47 REF SRCCLKC6 20
22X2 RN10 DREFCLK_96M R38 49.9 +-1%
NS
31 14M_SIO
R36 22 +-5% 22 3 4 NS
Y1 XTAL_IN SRCCLKT8 CLK_PCIE_ICH 12 DREFCLK_96M# R39 49.9 +-1%
45 X1 SRCCLKC8 23 1 2 CLK_PCIE_ICH# 12
44 22X2 NS
1 X2 DREFCLKSS_100M R41 49.9 +-1%
C960 SRCCLKT9 26
R40 2.2K +-5% XTAL_OUT 25 NS
18PF/50V 14.31818MHZ SRCCLKC9 DREFCLKSS_100M# R42 49.9 +-1%
B C_0402 R_0402 IREF 33
SRC_GND1 RN11 NS B
C20 C21 IREF
PCI_GND1
SRC_GND
CPU_GND
REF_GND
27 3 4
PCI_GND
SRCCLKT10 CLK_PCIE_MCH 6
GND_48
18PF/50V 18PF/50V R43 28 1 2
C_0402 0 +-5% SRCCLKC10 22X2 CLK_PCIE_MCH# 6
C_0402
FOR EMC
11
30
37
46
55
CY28446LFXC 59
1
VCC1R05B
VCC1R05B
R44
1K +-1%
NS VCC1R05B
R52
R45 R_0402 0 +-5% BSEL2 1K +-1%
3 CPU_BSEL2
NS
R48
1K +-1%
R47 1K +-1% R46 NS R53 R_0402 0 +-5% BSEL0
3 CPU_BSEL0
6 MCH_BSEL2 2.2K +-5% R49 R_0402 0 +-5% BSEL1
R_0402 3 CPU_BSEL1
R55 1K +-1% R54
NS LENOVO.PND
6 MCH_BSEL0 2.2K +-5%
R_0402
NB system design section
A R51 1K +-1% R50 A