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M 9F1 Block Diagram R1.0
D D
TI Charger
BQ24753ARHDR P.36
Inputs Outputs
DCBATOUT
DC_IN BT+
LVDS 10.1" LCD PANEL
P18 P12~P13 P28
DDRII CPU
CLOCK GEN. DDRII 667
SODIMM PineView-M System DC/DC
9LRS3165BKLFT TPS51125RGER P.37
Inputs Outputs
+3VALW
+5VALW
+5VALW_LDO
VGA D-Sub
DCBATOUT
+ECVCC
22mm x 22mm
P26
P6~P11
System DC/DC
TPS51124RGER P.38
C DMI x 2 Inputs Outputs C
+1_8VSUS
DCBATOUT
VCCGFX
HDP JACK
USB#3 USB#2 USB#1 USB#0
3G CON CON CON
P30 P27 P27 P27 AUDIO CODEC MIC JACK CPU DC/DC
P.39
USB2.0 Tiger Point HDA Int. DMIC
MAX8796GTJ+
USB#7 USB#6 USB#5 USB#5 REALTEK INPUTS OUTPUT
MM-SIM CAMERA BT WiFi ALC269Q DCBATOUT VHCORE
P30 P28 P31 P31
USB 2.0 (8 ports) P23
Speaker
SATA (2 Ports)
PCIE x 1 AZALIA HD AUDIO System DC/DC
G2998BP11U P.40
3 X1 PCIE IF
Inputs Outputs
1 PCI
LPC I/F +1_8VSUS +0_9VRUN
Transformer LAN + 4 in 1
B
Carder Reader 17mm x 17mm
SATA B
RJ45P22 10/100Mb PCIE Interface SATA
P22 JMC261 P21
HDD P25 System DC/DC
P14~P17 G9731F11U P.40
Inputs Outputs
+1_8VSUS +1_5VRUN
3 in 1
LPC,33MHZ
Card Slot
P21
System DC/DC
SM Bus G9731F11U P.40
EC Thermal Sensor
Inputs Outputs
NUVOTON NPCE783LA0DX P19 EMC1412-1 P33 +1_8VSUS +1_05VRUN
SPI SM Bus Battery Pack
P36
A BIOS TOUCH KBD A
P20
PAD P20 P20
CCPBG
Title
Block Diagram
Size Document Number Rev
A2 M9F1 0.1
Date: Wednesday, March 17, 2010 Sheet 1 of 44
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CPUC0/CPUT0 CLK_CPU_BCLK# BCLKN
CLK_CPU_BCLK BCLKP Pineview
D D
CPUC1/CPUT1 CLK_MCH_BCLK# HPL_CLKINN DDR_A_CK0 M_CLK_DDR#0 CK0/CK0#
CLK_MCH_BCLK HPL_CLKINP DDR_A_CK#0 M_CLK_DDR0
CLK_PCIE_LAN# SRCC6/SRCT6 SO-DIMM
LAN DDR_A_CK1 M_CLK_DDR#1 CK1/CK1#
25MHz CLK_PCIE_LAN SRCC4/SRCT4 EXP_CLKIN# EXP_CLKINN
DDR_A_CK#1 M_CLK_DDR1
EXP_CLKIN EXP_CLKINP
SRCC1/SRCT1 DREFSSCLK# DPL_REFSSCLKINN
DREFSSCLK DPL_REFSSCLKINP
CLK_PCIE_WLAN# SRCC9/SRCT9
Wireless CLK_PCIE_WLAN
C
SRCC0/SRCT0 DREFCLK# DPL_REFCLKINN C
DREFCLK DPL_REFCLKINP
CLK_PCIE_3G# SRCC10/SRCT10
3G CLK_PCIE_3G
CPUC2/CPUT2 CLK_ICH_DMI# DMI_CLKINN
32.768KHz
CLK_ICH_DMI DMI_CLKINP
SRCC2/SRCT2 CLK_ICH_SATA# SATA_CLKINN
CLK_ICH_SATA SATA_CLKINP
USB_48MHz CLK_ICH48 CLK48
TPT
B
PCI_F5 CLK_ICH_PCI PCICLK B
HDA_BIT_CLK HDA_CODEC_BITCLK BCLK
REF0 CLK_ICH14 CLK14
HD Audio
CK-505
14.318MHz LPCCLK
PCI4 CLK_KBCPCI
32.768KHz
EC
A A
CCPBG
Title
Clock distribution
Size Document Number Rev
A3 M9F1 0.1
Date: Wednesday, March 17, 2010 Sheet 2 of 44
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Pine Trail Power Flowchart for M9F1
D Voltage Rails O MEANS ON X MEANS OFF D
power +5VALW_LDO +5VALW +5VRUN
plane +ECVCC +3VALW +3VSUS +3VRUN
+1_8VSUS +1_8VRUN
+1_5VRUN
+1_05VRUN
+0_9VRUN
VCCGFX
VHCORE
State
S0
O O O O
S3
C O O O X C
S5/AC, S4
O O X X
S5 Battery only
O X X X
S5 S4/AC & Battery
don't exist (G3) X X X X
S3 : STR
S4 : STD
S5 : SOFT OFF
G3 : ME OFF
B B
A A
CCPBG
Title
Power Flowchart
Size Document Number Rev
A3 M9F1 0.1
Date: Wednesday, March 17, 2010 Sheet 3 of 44
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Pine Trail Power On Sequence REV : 2009/08/17
S4/S5 State S3 State S0 State
D D
DC_IN/BT+
DCBATOUT
+5VALW_LDO/+ECVCC
G3 to S5
+3VALW/+5VALW
ALW_PWRGD
PM_RSMRST#
PWRSW#
C C
PWRBTN#
PM_SLP_S4#
SUS_ON
+3VSUS/+5VSUS/+1_8VSUS
PM_SLP_S3#
RUN_ON
+3VRUN/+5VRUN
+0_9VRUN/+1_5VRUN
+1_5V_PWRGD
B +1_05VRUN
S5 to S0 B
+1_05V_PWRGD
+1_8VRUN/VCCGFX
ALL_SYS_PWRGD
IMVP_VR_ON
VHCORE
CK_PWRGD
DELAY_VR_PWRGD
H_PWRGD
A PLT_RST# A
CCPBG
Power On Sequence(1)
Title
Size Document Number Rev
Custom M9F1 0.1
Date: Wednesday, March 17, 2010 Sheet 4 of 44
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REV : 2009/08/18
Pine Trail Power On Sequence
D
-1 2 Battery Only
D
G3 to S5
-1 4 AC Mode
Reset IC
RN5VD30CA 5
Power On Button S5 to S0 4 19
2
ECRST#
DCBATOUT
BAT
-1 0
DCBATOUT 1 +ECVCC 7 PM_SLP_S4#
AC +5VALW_LDO
+ECVCC 10 PM_SLP_S3#
8
SUS_ON
6 PWRBTN#
C
11 RUN_ON C
+5VALW EC 18 H_PWRGD
3b ALW_PWRGD CPUPWRGD
3a ALW_ON NPCE783L 4 PM_RSMRST#
+3VALW
19
Tigerpoint
PLT_RST#
9
+3VSUS DDR_PWRGD
ALL_SYS_PWRGD
17 SYS_PWRGD_TPT
CPUPWRGOOD
PWROK
14 19 PLT_RST#
8 SUS_ON +1_8VSUS RSTIN#
14 CPU
Pineview
GFX_PWRGD
15 PWROK
B
IMVP_VR_ON VRMPWRGD B
+5VRUN
11 RUN_ON +3VRUN
13 17
+0_9VRUN DELAY_VR_PWRGD
+1_5VRUN +1_5V_PWRGD
12
+1_5V_PWRGD +1_05VRUN
13
+1_05V_PWRGD VCCGFX
+1_8VRUN
IMVP 16 IMVP_CLK_EN# 16 CK_PWRGD
CLK Gen.
VHCORE CK505
A A
CCPBG
Power On Sequence(2)
Title
Size Document Number Rev
Custom M9F1 0.1
Date: Wednesday, March 17, 2010 Sheet 5 of 44
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D D
U1A
C C
C4 1 2 0.1U_10V_K 0402_X5R DMI_RXP0_C F3 G2
14 DMI_RXP0 DMI_RXP_0 DMI_TXP_0 DMI_TXP0 14
C1 1 2 0.1U_10V_K 0402_X5R DMI_RXN0_C F2 G1
14 DMI_RXN0 DMI_RXN_0 DMI_TXN_0 DMI_TXN0 14
C2 1 2 0.1U_10V_K 0402_X5R DMI_RXP1_C H4 H3
14 DMI_RXP1 DMI_RXP_1 DMI_TXP_1 DMI_TXP1 14
C3 1 2 0.1U_10V_K 0402_X5R DMI_RXN1_C G3 J2
14 DMI_RXN1 DMI_RXN_1 DMI_TXN_1 DMI_TXN1 14
DMI
N7 L10 EXP_COMP
18 EXP_CLKIN# EXP_CLKINN EXP_RCOMPO
18 EXP_CLKIN N6 L9
EXP_CLKINP EXP_ICOMPI EXP_RBIAS
L8
EXP_RBIAS
R10
R9 RSVD_2 N11 1 26MIL TP1
1
1
RSVD_1 RSVD_TP_2 26MIL TP2
N10 P11 1
RSVD_3 RSVD_TP_1 R1 R2
N9
RSVD_15
750_F 49.9_F
0402 0402
2
2
K2 K3
RSVD_18 RSVD_20
J1 L2
RSVD_17 RSVD_19
M4 M2
RSVD_16 RSVD_14
L3 N2
RSVD_21 RSVD_7
QLJB Pull-down must be placed
null
within 500 mils of the processor.
B B
A A
CCPBG
Title
CPU- Pineview (1)
Size Document Number Rev
A3 M9F1 0.1
Date: Wednesday, March 17, 2010 Sheet 6 of 44
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U1B
12,13 M_A_A[14..0] M_A_DQ[63..0] 12
M_A_A0 AH19 AD3 M_A_DQS0
M_A_A1 AJ18 DDR_A_MA_0 DDR_A_DQS_0 AD2 M_A_DQS#0
M_A_A2 DDR_A_MA_1 DDR_A_DQS#_0 M_A_DM0
AK18 AD4
M_A_A3 DDR_A_MA_2 DDR_A_DM_0
AK16
M_A_A4 DDR_A_MA_3 M_A_DQ0
AJ14 AC4
M_A_A5 DDR_A_MA_4 DDR_A_DQ_0 M_A_DQ1
AH14 AC1
M_A_A6 AK14 DDR_A_MA_5 DDR_A_DQ_1 AF4 M_A_DQ2
M_A_A7 DDR_A_MA_6 DDR_A_DQ_2 M_A_DQ3
AJ12 AG2
M_A_A8 DDR_A_MA_7 DDR_A_DQ_3 M_A_DQ4
D AH13 AB2 M_A_DQS[7..0] 12 D
M_A_A9 DDR_A_MA_8 DDR_A_DQ_4 M_A_DQ5
AK12 AB3
M_A_A10 DDR_A_MA_9 DDR_A_DQ_5 M_A_DQ6
AK20 AE2 M_A_DQS#[7..0] 12
M_A_A11 AH12 DDR_A_MA_10 DDR_A_DQ_6 AE3 M_A_DQ7
M_A_A12 DDR_A_MA_11 DDR_A_DQ_7
AJ11 M_A_DM[7..0] 12
M_A_A13 DDR_A_MA_12 M_A_DQS1
AJ24 AB8
M_A_A14 DDR_A_MA_13 DDR_A_DQS_1 M_A_DQS#1
AJ10 AD7
DDR_A_MA_14 DDR_A_DQS#_1 M_A_DM1
AA9
DDR_A_DM_1
AK22 AB6 M_A_DQ8
12,13 M_A_WE# DDR_A_WE# DDR_A_DQ_8
AJ22 AB7 M_A_DQ9
12,13 M_A_CAS# DDR_A_CAS# DDR_A_DQ_9
AK21 AE5 M_A_DQ10
12,13 M_A_RAS# DDR_A_RAS# DDR_A_DQ_10
AG5 M_A_DQ11
AJ20 DDR_A_DQ_11 AA5 M_A_DQ12
12,13 M_A_BS0 DDR_A_BS_0 DDR_A_DQ_12
AH20 AB5 M_A_DQ13
12,13 M_A_BS1 DDR_A_BS_1 DDR_A_DQ_13
AK11 AB9 M_A_DQ14
12,13 M_A_BS2 DDR_A_BS_2 DDR_A_DQ_14
AD6 M_A_DQ15
DDR_A_DQ_15
AD8 M_A_DQS2
DDR_A_DQS_2 M_A_DQS#2
12,13 M_CS#0 AH22 AD10
DDR_A_CS#_0 DDR_A_DQS#_2 M_A_DM2
12,13 M_CS#1 AK25 AE8
DDR_A_CS#_1 DDR_A_DM_2
AJ21
DDR_A_CS#_2 M_A_DQ16
AJ25 AG8
DDR_A_CS#_3 DDR_A_DQ_16 AG7 M_A_DQ17
DDR_A_DQ_17 M_A_DQ18
12,13 M_CKE0 AH10 AF10
DDR_A_CKE_0 DDR_A_DQ_18 M_A_DQ19
12,13 M_CKE1 AH9 AG11
DDR_A_CKE_1 DDR_A_DQ_19 M_A_DQ20
AK10 AF7
DDR_A_CKE_2 DDR_A_DQ_20 M_A_DQ21
AJ8 AF8
DDR_A_CKE_3 DDR_A_DQ_21 M_A_DQ22
AD11
C DDR_A_DQ_22 M_A_DQ23 C
12,13 M_ODT0 AK24 AE10
DDR_A_ODT_0 DDR_A_DQ_23
12,13 M_ODT1 AH26
DDR_A_ODT_1 M_A_DQS3
AH24 AK5
DDR_A_ODT_2 DDR_A_DQS_3 M_A_DQS#3
AK27 AK3
DDR_A_ODT_3 DDR_A_DQS#_3 AJ3 M_A_DM3
DDR_A_DM_3
AH1 M_A_DQ24
DDR_A_DQ_24 M_A_DQ25
12 M_CLK_DDR0 AG15 AJ2
DDR_A_CK_0 DDR_A_DQ_25 M_A_DQ26
12 M_CLK_DDR#0 AF15 AK6
AD13 DDR_A_CK#_0 DDR_A_DQ_26 AJ7 M_A_DQ27
12 M_CLK_DDR1 DDR_A_CK_1 DDR_A_DQ_27
AC13 AF3 M_A_DQ28
12 M_CLK_DDR#1 DDR_A_CK#_1 DDR_A_DQ_28
AH2 M_A_DQ29
DDR_A_DQ_29 M_A_DQ30
AL5
DDR_A_DQ_30 M_A_DQ31
AC15 AJ6
AD15 DDR_A_CK_3 DDR_A_DQ_31
DDR_A_CK#_3 M_A_DQS4
AF13 AG22
DDR_A_CK_4 DDR_A_DQS_4 M_A_DQS#4
AG13 AG21
DDR_A_CK#_4 DDR_A_DQS#_4 M_A_DM4
AD19
+1_8VSUS DDR_A_DM_4
AE19 M_A_DQ32
DDR_A_DQ_32 M_A_DQ33
AD17 AG19
RSVD_22 DDR_A_DQ_33 M_A_DQ34
AC17 AF22
1
RSVD_23 DDR_A_DQ_34 M_A_DQ35
Place resistors close to MCH PINS ON MCH_VREF, AB15 AD22
R3 RSVD_24 DDR_A_DQ_35 M_A_DQ36
AB17 AG17
Place 0.1uF CAP close to MCH. RSVD_25 DDR_A_DQ_36 AF19 M_A_DQ37