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Model Name: T645HW03 V0
Issue Date : 2010/7/20
( )Preliminary Specifications
( )Final Specifications
Customer Signature Date AUO Date
Approved By Approval By PM Director
Yenting Chiu
_________________________________ ____________________________________
Note Reviewed By RD Director
Eugene Chen
____________________________________
Reviewed By Project Leader
Hank Chiu
____________________________________
Prepared By PM
Ryan Chung
____________________________________
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Contents
No
CONTENTS
RECORD OF REVISIONS
1 GENERAL DESCRIPTION
2 ABSOLUTE MAXIMUM RATINGS
3 ELECTRICAL SPECIFICATION
3-1 DC ELECTRIACL CHARACTERISTICS
3-2 AC ELECTRIACL CHARACTERISTICS
3-3 INTERFACE CONNECTIONS
3-4 SIGNAL TIMING SPECIFICATION
3-5 SIGNAL TIMING WAVEFORM
3-6 COLOR INPUT DATA REFERENCE
3-7 POWER SEQUENCE FOR LCD
3-8 BACKLIGHT SPECIFICATION
4 OPTICAL SPECIFICATION
5 MECHANICAL CHARACTERISTICS
6 RELIABILITY TEST ITEMS
7 INTERNATIONAL STANDARD
7-1 SAFETY
7-2 EMC
8 PACKING
8-1 DEFINITION OF LABEL
8-2 PACKING METHODS
8-3 PALLET AND SHIPMENT INFORMATION
9 PRECAUTION
9-1 MOUNTING PRECAUTIONS
9-2 OPERATING PRECAUTIONS
9-3 ELECTROSTATIC DISCHARGE CONTROL
9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE
9-5 STORAGE
9-6 HANDLING PRECAUTIONS FOR PROTECT FILM
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Record of Revision
Version Date Page Description
1.0 2010/07/20 First release
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1. General Description
This specification applies to the 64.5 inch Color TFT-LCD Module T645HW03 V0. This LCD module has a TFT
active matrix type liquid crystal panel 1920 x 1080 pixels, and diagonal size of 64.5 inch. This module supports
1920 x 1080 mode. Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical
stripes. Gray scale or the brightness of the sub-pixel color is determined with a 10-bit gray scale signal for each
dot.
The T645HW03 V0 has been designed to apply the 10-bit 4 channel LVDS interface method. It is intended to
support displays where high brightness, wide viewing angle, high color saturation, and high color depth are very
important.
* General Information
Items Specification Unit Note
Active Screen Size 64.53 inch
Display Area 1428.48 (H) x 803.52 (V) mm
Outline Dimension 1508.0(H) x 878.0(V) x 60.0(D) mm
Driver Element a-Si TFT active matrix
Display Colors 10 bit, 1.07B Colors
Number of Pixels 1920 x 1080 Pixel
Pixel Pitch 0.744 mm
Pixel Arrangement RGB vertical stripe
Display Operation Mode Normally Black
Surface Treatment HC, 3H
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2. Absolute Maximum Ratings
The followings are maximum values which, if exceeded, may cause faulty operation or damage to the unit
Item Symbol Min Max Unit Conditions
Logic/LCD Drive Voltage VDD -0.3 14 [Volt] Note 1
Input Voltage of Signal Vin -0.3 4 [Volt] Note 1
o
Operating Temperature TOP 0 +50 [ C] Note 2
Operating Humidity HOP 10 90 [%RH] Note 2
o
Storage Temperature TST -20 +60 [ C] Note 2
Storage Humidity HST 10 90 [%RH] Note 2
o
Panel Surface Temperature PST - 65 [ C] Note 3
Note 1: Duration:50 msec.
Note 2 : Maximum Wet-Bulb should be 39 and No condensation.
The relative humidity must not exceed 90% non-condensing at temperatures of 40 or less. At temperatures
greater than 40 , the wet bulb temperature must not exceed 39 .
Note 3: Surface temperature is measured at 50 Dry condition
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3. Electrical Specification
The T645HW03 V0 requires two power inputs. One is employed to power the LCD electronics and to drive the TFT
array and liquid crystal. The second input for BLU is to power inverter.
3.1 Electrical Characteristics
Value
Parameter Symbol Unit Note
Min. Typ. Max
LCD
Power Supply Input Voltage VDD 10.8 12.0 13.2 VDC 1
Power Supply Input Current IDD 0.6 1.2 1.8 A 2
Power Consumption PC 7.92 14.4 19.44 Watt 2
Inrush Current IRUSH -- -- 16 A 3
Input Differential Voltage VID 200 400 600 mVDC 4
LVDS Differential Input High Threshold Voltage VTH +100 -- +300 4 4
Interface Differential Input Low Threshold Voltage VTL -300 -- -100 4 4
Input Common Mode Voltage VICM 1.10 1.25 1.40 VDC 4
VIH
Input High Threshold Voltage 2.7 -- 3.3 VDC --
CMOS (High)
Interface VIL
Input Low Threshold Voltage 0 -- 0.6 VDC --
(Low)
Backlight Power Consumption PBL 380 Watt --
Life Time 50000 -- Hours --
Note :
1. The ripple voltage should be controlled under 10% of VCC
2. VDD = 12.0V, Fv = 120Hz, FCLK = 82MHz , 25 , Test Pattern : White Pattern
>> refer to "Section:3.3 Signal Timing Specification, Typical timing"
3. Measurement condition : Rising time = 400us
9''
*1'
s
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4. VICM = 1.25V
LVDS -
V IC M V TH
|V ID |
V TL
LVDS +
GND
|V ID |
0V
|V ID |
3.2 AC Electrical Characteristics
Value
Parameter Symbol Unit Note
Min. Typ. Max
Input Channel Pair Skew Margin tSKEW (CP) -500 -- +500 ps 1
Receiver Clock : Spread Spectrum Fclk Fclk
Fclk_ss -- MHz 2
Modulation range -3% +3%
LVDS
Interface Receiver Clock : Spread Spectrum
Fss 30 -- 200 KHz 2
Modulation frequency
Receiver Data Input Margin
Fclk = 85 MHz tRMG -0.4 -- 0.4 ns 3
Fclk = 65 MHz -0.5 -- 0.5
1. Input Channel Pair Skew Margin
Note: x = 0, 1, 2, 3, 4
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2. LVDS Receiver Clock SSCG (Spread spectrum clock generator) is defined as below figures
)66
)FONB
)FONBVV PD[
)FON
)FONB
)FONBVV PLQ
3. Receiver Data Input Margin
Rating
Parameter Symbol Unit Note
Min Type Max
Input Clock Frequency Fclk Fclk (min) -- Fclk (max) MHz T=1/Fclk
Input Data Position0 tRIP1 -|tRMG| 0 |tRMG| ns
Input Data Position1 tRIP0 T/7-|tRMG| T/7 T/7+|tRMG| ns
Input Data Position2 tRIP6 2T/7-|tRMG| 2T/7 2T/7+|tRMG| ns
Input Data Position3 tRIP5 3T/7-|tRMG| 3T/7 3T/7+|tRMG| ns
Input Data Position4 tRIP4 4T/7-|tRMG| 4T/7 4T/7+|tRMG| ns
Input Data Position5 tRIP3 5T/7-|tRMG| 5T/7 5T/7+|tRMG| ns
Input Data Position6 tRIP2 6T/7-|tRMG| 6T/7 6T/7+|tRMG| ns
W5,3
W5,3
W5,3
W5,3
W5,3
W5,3
W5,3
/9'6 5[
5[ 5[ 5[ 5[ 5[ 5[ 5[ 5[ 5[ 5[ 5[ 5[
,QSXW 'DWD
/9'6 5[
,QSXW &ORFN 9GLII 9
)FON 7
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T645HW03 V0 Product Specification
Rev. 1.0
3.3 Interface Connections
LCD connector: FI-RE51S-HF (Manufactured by JAE)
Mating connector: FI-RE51S-HL (Manufactured by JAE)
PIN Symbol Description PIN Symbol Description
1 VDD Power Supply, +12V DC Regulated 26 CH4_0+ LVDS Channel 4, Signal 0+
2 VDD Power Supply, +12V DC Regulated 27 CH4_1- LVDS Channel 4, Signal 1-
3 VDD Power Supply, +12V DC Regulated 28 CH4_1+ LVDS Channel 4, Signal 1+
4 VDD Power Supply, +12V DC Regulated 29 CH4_2- LVDS Channel 4, Signal 2-
5 VDD Power Supply, +12V DC Regulated 30 CH4_2+ LVDS Channel 4, Signal 2+
6 GND Ground 31 GND Ground
7 GND Ground 32 CH4_CLK- LVDS Channel 4, Clock -
8 GND Ground 33 CH4_CLK+ LVDS Channel 4, Clock +
9 GND Ground 34 GND Ground
10 CH2_0- LVDS Channel 2, Signal 0- 35 CH4_3- LVDS Channel 4, Signal 3-
11 CH2_0+ LVDS Channel 2, Signal 0+ 36 CH4_3+ LVDS Channel 4, Signal 3+
12 CH2_1- LVDS Channel 2, Signal 1- 37 CH4_4- LVDS Channel 4, Signal 4-
13 CH2_1+ LVDS Channel 2, Signal 1+ 38 CH4_4+ LVDS Channel 4, Signal 4+
14 CH2_2- LVDS Channel 2, Signal 2- 39 GND Ground
15 CH2_2+ LVDS Channel 2, Signal 2+ 40 Reserved AUO Internal Use Only
16 GND Ground 41 Reserved AUO Internal Use Only
17 CH2_CLK- LVDS Channel 2, Clock - 42 Reserved AUO Internal Use Only
18 CH2_CLK+ LVDS Channel 2, Clock + 43 Reserved AUO Internal Use Only
19 GND Ground 44 Reserved AUO Internal Use Only
Open/High(3.3V) for NS,
20 CH2_3- LVDS Channel 2, Signal 3- 45 LVDS_SEL
Low(GND) for JEIDA
21 CH2_3+ LVDS Channel 2, Signal 3+ 46 Reserved AUO Internal Use Only
Open/High(3.3V) for 2D mode display,
22 CH2_4- LVDS Channel 2, Signal 4- 47 3D_SEL
Low(GND) for 3D mode display
Open/High(3.3V) for 10 bits LVDS input,
23 CH2_4+ LVDS Channel 2, Signal 4+ 48 BIT_SEL
Low(GND) for 8 bits LVDS input
24 GND Ground 49 Reserved AUO Internal Use Only
25 CH4_0- LVDS Channel 4, Signal 0- 50 Reserved AUO Internal Use Only
51 Reserved AUO Internal Use Only
9 / 33
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T645HW03 V0 Product Specification
Rev. 1.0
LCD connector: FI-RE41S-HF (Manufactured by JAE)
Mating connector: FI-RE41S-HL (Manufactured by JAE)
PIN Symbol Description PIN Symbol Description
1 VDD Power Supply, +12V DC Regulated 21 CH1_3+ LVDS Channel 1, Signal 3+
2 VDD Power Supply, +12V DC Regulated 22 CH1_4- LVDS Channel 1, Signal 4-
3 VDD Power Supply, +12V DC Regulated 23 CH1_4+ LVDS Channel 1, Signal 4+
4 VDD Power Supply, +12V DC Regulated 24 GND Ground
5 VDD Power Supply, +12V DC Regulated 25 CH3_0- LVDS Channel 3, Signal 0-
6 GND Ground 26 CH3_0+ LVDS Channel 3, Signal 0+
7 GND Ground 27 CH3_1- LVDS Channel 3, Signal 1-
8 GND Ground 28 CH3_1+ LVDS Channel 3, Signal 1+
9 GND Ground 29 CH3_2- LVDS Channel 3, Signal 2-
10 CH1_0- LVDS Channel 1, Signal 0- 30 CH3_2+ LVDS Channel 3, Signal 2+
11 CH1_0+ LVDS Channel 1, Signal 0+ 31 GND Ground
12 CH1_1- LVDS Channel 1, Signal 1- 32 CH3_CLK- LVDS Channel 3, Clock -
13 CH1_1+ LVDS Channel 1, Signal 1+ 33 CH3_CLK+ LVDS Channel 3, Clock +
14 CH1_2- LVDS Channel 1, Signal 2- 34 GND Ground
15 CH1_2+ LVDS Channel 1, Signal 2+ 35 CH3_3- LVDS Channel 3, Signal 3-
16 GND Ground 36 CH3_3+ LVDS Channel 3, Signal 3+
17 CH1_CLK- LVDS Channel 1, Clock - 37 CH3_4- LVDS Channel 3, Signal 4-
18 CH1_CLK+ LVDS Channel 1, Clock + 38 CH3_4+ LVDS Channel 3, Signal 4+
19 GND Ground 39 GND Ground
20 CH1_3- LVDS Channel 1, Signal 3- 40 NC No Connect
41 NC No Connect
Note 1: All GND (ground) pins should be connected together and should also be
connected to the LCD's metal frame.
Note 2: All VDD (power input) pins should be connected together.
Note 3: All Reserved pins should be open without voltage input.
Note 4: All NC pins should be open without voltage input
10 / 33
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T645HW03 V0 Product Specification
Rev. 1.0