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ICL7116, ICL7117
January 1998
3 1/2 Digit, LCD/LED Display, A/D Converter with Display Hold
Description
The Intersil ICL7116 and ICL7117 are high performance, low power, 31/2 digit, A/D converters. Included are seven segment decoders, display drivers, a reference, and a clock. The ICL7116 is designed to interface with a liquid crystal display (LCD) and includes a multiplexed backplane drive. The ICL7117 will directly drive an instrument size, light emitting diode (LED) display. The ICL7116 and ICL7117 have all of the features of the ICL7106 and ICL7107 with the addition of a HOLD Reading input. With this input, it is possible to make a measurement and retain the value on the display indefinitely. To make room for this feature the reference low input has been connected to Common internally rather than being fully differential. These circuits retain the accuracy, versatility, and true economy of the ICL7106 and ICL7107. They feature auto-zero to less than 10µV, zero drift of less than 1µV/oC, input bias current of 10pA maximum, and roll over error of less than one count. The versatility of true differential input is of particular advantage when measuring load cells, strain gauges and other bridge-type transducers. And finally, the true economy of single power supply operation (ICL7116) enables a high performance panel meter to be built with the addition of only eleven passive components and a display.
Features
· HOLD Reading Input Allows Indefinite Display Hold · Guaranteed Zero Reading for 0V Input · True Polarity at Zero for Precise Null Detection · 1pA Typical Input Current · Direct Display Drive - LCD ICL7116 - LED lCL7117 · Low Noise - Less Than 15µVP-P (Typ) · On Chip Clock and Reference · Low Power Dissipation - Typically Less Than 10mW · No Additional Active Circuits Required · Surface Mount Package Available
Ordering Information
PART NUMBER ICL7116CPL ICL7116CM44 ICL7117CPL TEMP. RANGE (oC) 0 to 70 0 to 70 0 to 70 PACKAGE 40 Ld PDIP 44 Ld MQFP 40 Ld PDIP PKG. NO. E40.6 Q44.10x10 E40.6
Pinouts
ICL7116, ICL7117 (PDIP) TOP VIEW
HLDR D1 C1 B1 (1's) A1 F1 G1 E1 D2 C2 (10's) B2 A2 F2 E2 D3 (100's) B3 F3 E3 (1000) AB4 (MINUS) POL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 OSC 1 39 OSC 2 38 OSC 3 37 TEST 36 REF HI 35 V+ 34 CREF+ 33 CREF32 COMMON 31 IN HI 30 IN LO 29 A-Z 28 BUFF 27 INT 26 V25 G2 (10's) 24 C3 23 A3 22 G3 21 BP/GND A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3 (100's) NC NC TEST OSC 3 NC OSC 2 OSC 1 HLDR D1 C1 B1 1 44 43 42 41 40 39 38 37 36 35 34 33 2 32 3 4 5 6 7 8 9 10 31 30 29 28 27 26 25 24 NC G2 C3 A3 G3 BP POL AB4 E3 F3 B3
ICL7116 (MQFP) TOP VIEW
COMMON
REF HI
CREF+
CREF -
IN LO
BUFF
IN HI
A-Z
INT
V+
11 23 12 13 14 15 16 17 18 19 20 21 22
V-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
File Number
3083.2
1
ICL7116, ICL7117
Absolute Maximum Ratings
Supply Voltage ICL7116, V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V ICL7117, V+ to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V ICL7117, V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-9V Analog Input Voltage (Either Input) (Note 1). . . . . . . . . . . . . V+ to VReference Input Voltage (Either Input) . . . . . . . . . . . . . . . . . V+ to VClock Input ICL7116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST to V+ ICL7117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to V+
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (MQFP - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER SYSTEM PERFORMANCE Zero Input Reading Ratiometric Reading Rollover Error Linearity Common Mode Rejection Ratio Noise Leakage Current Input Zero Reading Drift
(Note 3) TA = 25oC, fCLOCK = 48kHz, VREF = 100mV TEST CONDITIONS VIN = 0V, Full Scale = 200mV VlN = VREF , VREF = 100mV -VIN = +VlN 195mV Difference in Reading for Equal Positive and Negative Inputs Near Full Scale Full Scale = 200mV or Full Scale = 2V Maximum Deviation from Best Straight Line Fit (Note 5) VCM = ±1V, VIN = 0V, Full Scale = 200mV (Note 5) VIN = 0V, Full Scale = 200mV (Peak-To-Peak Value Not Exceeded 95% of Time) (Note 5) VlN = 0 (Note 5) VlN = 0, 0oC To 70oC (Note 5) VIN = 199mV, 0oC To 70oC (Note 5) VIN = 0 (Does Not Include LED Current for ICL7117) ICL7117 Only 25k Between Common and Positive Supply (With Respect to + Supply) MIN -000.0 999 2.4 TYP ±000.0 999/ 1000 ±0.2 ±0.2 50 15 1 0.2 1 1.0 0.6 3.0 80 MAX +000.0 1000 ±1 ±1 10 1 5 1.8 1.8 3.2 UNITS Digital Reading Digital Reading Counts Counts µV/V µV pA µV/oC ppm/oC mA mA V ppm/oC
Scale Factor Temperature Coefficient V+ Supply Current V- Supply Current COMMON Pin Analog Common Voltage
Temperature Coefficient of Analog Common 25k Between Common and Positive Supply (With Respect to + Supply) (Note 5) DISPLAY DRIVER (ICL7116 ONLY) Peak-To-Peak Segment Drive Voltage Peak-To-Peak Backplane Drive Voltage DISPLAY DRIVER (ICL7117 ONLY) Segment Sinking Current (Except Pins 19 and 20) Pin 19 Only Pin 20 Only V+ = 5V, Segment Voltage = 3V V+ = to V- = 9V, (Note 4)
4
5.5
6
V
5 10 4
8 16 7
-
mA mA mA
NOTES: 3. Unless otherwise noted, specifications apply to both the ICL7116 and ICL7117. ICL7116 is tested in the circuit of Figure 1. ICL7117 is tested in the circuit of Figure 2. 4. Back plane drive is in phase with segment drive for `off' segment, 180 degrees out of phase for `on' segment. Frequency is 20 times conversion rate. Average DC component is less than 50mV. 5. Not tested, guaranteed by design.
2
ICL7116, ICL7117 Typical Applications and Test Circuits
+
IN
9V
R1 R3 C4 R4 C1 OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 V+ 35 CREF+ 34 CREF- 33
R5 C5 C2 R2
COM 32
IN HI 31
IN LO 30
A-Z 29
BUFF 28
INT 27
V- 26
G2 25
C3 24
A3 23
G3 22
ICL7116
HLDR 20 POL 19 AB4 G1 D2 10 C2 11 B2 12 A2 15 D3 16 B3 D1 C1 B1 A1 E1 14 E2 18 E3 13 F2 17 F3 F1
1
2
3
4
5
6
7
8
9
DISPLAY
FIGURE 1. ICL7116 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE
BP 21
+5V R5 R1 TP5 R3 TP1 TP2 C4 R4 TP3
+ IN
-
C5 C R2 2
C1 OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 V+ 35 CREF+ 34 CREF- 33 COM 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28
INT 27
V- 26
G2 25
C3 24
A3 23
G3 22
ICL7117
HLDR 20 POL 19 AB4 G1 D1 C1 B1 A1 D2 10 C2 11 B2 12 A2 15 D3 16 B3 E1 14 E2 18 E3 F1 13 F2 17 F3
1
2
3
4
5
6
7
8
9
DISPLAY
FIGURE 2. ICL7117 TEST CIRCUIT AND TYPICAL APPLICATION WITH LED DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE
3
GND 21
C3 DISPLAY -5V R6 TO DECIMAL POINT C3 TP4 DISPLAY
+
C1 = 0.1µF C2 = 0.47µF C3 = 22µF C4 = 100pF C5 = 0.01µF R1 = 24k R2 = 47k R3 = 100k R4 = 1k R5 = 1M
C1 = 0.1µF C2 = 0.47µF C3 = 22µF C4 = 100pF C5 = 0.01µF R1 = 24k R2 = 47k R3 = 100k R4 = 1k R5 = 1M R6 = 150
ICL7116, ICL7117 Design Information Summary Sheet
· OSCILLATOR FREQUENCY fOSC = 0.45/RC COSC > 50pF; ROSC > 50k fOSC (Typ) = 48kHz · OSCILLATOR PERIOD tOSC = RC/0.45 · INTEGRATION CLOCK FREQUENCY fCLOCK = fOSC /4 · INTEGRATION PERIOD tINT = 1000 x (4/fOSC) · 60/50Hz REJECTION CRITERION tINT /t60Hz or tlNT /t50Hz = Integer · OPTIMUM INTEGRATION CURRENT IINT = 4µA · FULL SCALE ANALOG INPUT VOLTAGE VlNFS (Typ) = 200mV or 2V · INTEGRATE RESISTOR
V INFS R INT = ---------------I INT
· DISPLAY COUNT
V IN COUNT = 1000 × -------------V REF
· CONVERSION CYCLE tCYC = tCL0CK x 4000 tCYC = tOSC x 16,000 when fOSC = 48KHz; tCYC = 333ms · COMMON MODE INPUT VOLTAGE (V- + 1V) < VlN < (V+ - 0.5V) · AUTO-ZERO CAPACITOR 0.01µF < CAZ < 1µF · REFERENCE CAPACITOR 0.1µF < CREF < 1µF · VCOM Biased between V+ and V-. · VCOM V+ - 2.8V Regulation lost when V+ to V- < 6.8V. If VCOM is externally pulled down to (V + to V -)/2, the VCOM circuit will turn off. · ICL7116 POWER SUPPLY: SINGLE 9V V+ - V- = 9V Digital supply is generated internally VTEST V+ - 4.5V · ICL7116 DISPLAY: LCD Type: Direct drive with digital logic supply amplitude. · ICL7117 POWER SUPPLY: DUAL ±5.0V V+ = +5V to GND V- = -5V to GND Digital Logic and LED driver supply V+ to GND · ICL7117 DISPLAY: LED Type: Non-Multiplexed Common Anode
· INTEGRATE CAPACITOR
( t INT ) ( I INT ) C INT = ------------------------------V INT
· INTEGRATOR OUTPUT VOLTAGE SWING
( t INT ) ( I INT ) V INT = ------------------------------C INT
· VINT MAXIMUM SWING: (V- + 1.0V) < VINT < (V+ - 0.5V), VINT (Typ) = 2V
Typical Integrator Amplifier Output Waveform (INT Pin)
AUTO ZERO PHASE (COUNTS) 2999 - 1000
SIGNAL INTEGRATE PHASE FIXED 1000 COUNTS
DE-INTEGRATE PHASE 0 - 1999 COUNTS
TOTAL CONVERSION TIME = 4000 x tCLOCK = 16,000 x tOSC
4
ICL7116, ICL7117 Pin Descriptions
PIN NUMBER 40 PIN DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 44 PIN FLATPACK 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 34 35 36 37 38 39 40 41 42 43 44 3 4 6 7 NAME HLDR D1 C1 B1 A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3 B3 F3 E3 AB4 POL BP/GND G3 A3 C3 G2 VINT BUFF A-Z IN LO IN HI COMMON CREF CREF+ V+ REF HI TEST OSC3 OSC2 OSC1 Supply Input Output Output Input FUNCTION Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Supply Output Output Input Input Display Hold Control. Driver Pin for Segment "D" of the display units digit. Driver Pin for Segment "C" of the display units digit. Driver Pin for Segment "B" of the display units digit. Driver Pin for Segment "A" of the display units digit. Driver Pin for Segment "F" of the display units digit. Driver Pin for Segment "G" of the display units digit. Driver Pin for Segment "E" of the display units digit. Driver Pin for Segment "D" of the display tens digit. Driver Pin for Segment "C" of the display tens digit. Driver Pin for Segment "B" of the display tens digit. Driver Pin for Segment "A" of the display tens digit. Driver Pin for Segment "F" of the display tens digit. Driver Pin for Segment "E" of the display tens digit. Driver pin for segment "D" of the display hundreds digit. Driver pin for segment "B" of the display hundreds digit. Driver pin for segment "F" of the display hundreds digit. Driver pin for segment "E" of the display hundreds digit. Driver pin for both "A" and "B" segments of the display thousands digit. Driver pin for the negative sign of the display. Driver pin for the LCD backplane/Power Supply Ground. Driver pin for segment "G" of the display hundreds digit. Driver pin for segment "A" of the display hundreds digit. Driver pin for segment "C" of the display hundreds digit. Driver pin for segment "G" of the display tens digit. Negative power supply. Integrator amplifier output. To be connected to integrating capacitor. Input buffer amplifier output. To be connected to integrating resistor. Integrator amplifier input. To be connected to auto-zero capacitor. Differential inputs. To be connected to input voltage to be measured. LO and HI designators are for reference and do not imply that LO should be connected to lower potential, e.g., for negative inputs IN LO has a higher potential than IN HI. Internal voltage reference output. Connection pins for reference capacitor. Power Supply. Display test. Turns on all segments when tied to V+. Device clock generator circuit connection pins. DESCRIPTION
Supply/ Output
5
ICL7116, ICL7117 Detailed Description
Analog Section Figure 3 shows the Analog Section for the ICL7116 and ICL7117. Each measurement cycle is divided into three phases. They are (1) auto-zero (A-Z), (2) signal integrate (INT) and (3) de-integrate (DE). Auto-Zero Phase During auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited only by the noise of the system. In any case, the offset referred to the input is less than 10µV. Signal Integrate Phase During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide common mode range: up to 1V from either supply. If, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establish the correct common mode voltage. At the end of this phase, the polarity of the integrated signal is determined. De-Integrate Phase The final phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the
STRAY CREF
output to return to zero is proportional to the input signal. Specifically the digital reading displayed is:
V IN DISPLAY COUNT = 1000 ---------------- . V REF
Differential Input The input can accept differential voltages anywhere within the common mode range of the input amplifier, or specifically from 0.5V below the positive supply to 1V above the negative supply. In this range, the system has a CMRR of 86dB typical. However, care must be exercised to assure the integrator output does not saturate. A worst case condition would be a large positive common mode voltage with a near full scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. For these critical applications the integrator output swing can be reduced to less than the recommended 2V full scale swing with little loss of accuracy. The integrator output can swing to within 0.5V of either supply without loss of linearity. Differential Reference The reference voltage can be generated anywhere within the power supply voltage of the converter. The main source of common mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called up to de-integrate a positive signal but lose charge (decrease voltage) when called up to de-integrate a negative input signal. This difference in reference for positive or negative input voltage will give a roll-over error. However, by selecting the reference capacitor such that it is large enough in comparison to the stray capacitance, this error can be held to less than 0.5 count worst case. (See Component Value Selection.)
STRAY RINT CAZ A-Z 29 INTEGRATOR
+
CINT INT 27
CREF+ V+ 34
REF HI 36 A-Z
CREF33
BUFFER V+ 28 35
+
-
10µA 31 IN HI INT DEDE+ INPUT HIGH 6.2V A-Z 2.8V
-
+
TO DIGITAL SECTION
A-Z A-Z N 32 COMMON INT A-Z AND DE(±) 26 VINPUT LOW DE+ DE+
COMPARATOR
-
30 IN LO
FIGURE 3. ANALOG SECTION OF ICL7116 AND ICL711
6
ICL7116, ICL7117
Analog COMMON This pin is included primarily to set the common mode voltage for battery operation (ICL7116) or for any system where the input signals are floating with respect to the power supply. The COMMON pin sets a voltage that is approximately 2.8V less than the positive supply. This is selected to give a minimum end-of-life battery voltage of about 6.8V. However, analog COMMON has some of the attributes of a reference voltage. When the total supply voltage is large enough to cause the zener to regulate (>6.8V), the COMMON voltage will have a low voltage coefficient (0.001%/V), low output impedance (15), and a temperature coefficient typically less than 80ppm/oC. The limitations of the on chip reference should also be recognized, however. With the ICL7117, the internal heating which results from the LED drivers can cause some degradation in performance. Due to their higher thermal resistance, plastic parts are poorer in this respect than ceramic. The combination of reference Temperature Coefficient (TC), internal chip dissipation, and package thermal resistance can increase noise near full scale from 25µV to 80µVP-P . Also the linearity in going from a high dissipation count such as 1000 (20 segments on) to a low dissipation count such as 1111 (8 segments on) can suffer by a count or more. Devices with a positive TC reference may require several counts to pull out of an over-range condition. This is because over-range is a low dissipation mode, with the three least significant digits blanked. Similarly, units with a negative TC may cycle between over range and a non-over range count as the die alternately heats and cools. All these problems are of course eliminated if an external reference is used. The ICL7116, with its negligible dissipation, suffers from none of these problems. In either case, an external reference can easily be added, as shown in Figure 4. Analog COMMON is also used as the input low return during auto-zero and de-integrate. If IN LO is different from analog COMMON, a common mode voltage exists in the system and is taken care of by the excellent CMRR of the converter. However, in some applications IN LO will be set at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied to the same point, thus removing the common mode voltage from the converter. The same holds true for the reference voltage. If reference can be conveniently tied to analog COMMON, it should be since this removes the common mode voltage from the reference system. Within the lC, analog COMMON is tied to an N-Channel FET that can sink approximately 30mA of current to hold the voltage 2.8V below the positive supply (when a load is trying to pull the common line positive). However, there is only 10µA of source current, so COMMON may easily be tied to a more negative voltage thus overriding the internal reference.
V V+
REF HI COMMON ICL7116 ICL7117
6.8V ZENER IZ
V-
FIGURE 4A.
V+
V ICL7116 ICL7117 REF HI 20k
6.8k
ICL8069 1.2V REFERENCE
COMMON
FIGURE 4B. FIGURE 4. USING AN EXTERNAL REFERENCE
TEST The TEST pin serves two functions. On the ICL7116 it is coupled to the internally generated digital supply through a 500 resistor. Thus it can be used as the negative supply for externally generated segment drivers such as decimal points or any other annunciator the user may want to include on the LCD display. Figures 5 and 6 show such an application. No more than a 1mA load should be applied.
V+
1M TO LCD DECIMAL POINT
ICL7116 BP TEST 21 37
TO LCD BACKPLANE
FIGURE 5. SIMPLE INVERTER FOR FIXED DECIMAL POINT
The second function is a "lamp test". When TEST is pulled high (to V+) all segments will be turned on and the display should read "-1888". The TEST pin will sink about 5mA under these conditions.
CAUTION: On the ICL7116, in the lamp test mode, the segments have a constant DC voltage (no square-wave) and may burn the LCD display if left in this mode for several minutes.
7
ICL7116, ICL7117 Digital Section
V+ V+ BP
ICL7116
DECIMAL POINT SELECT
TO LCD DECIMAL POINTS
TEST CD4030 GND
Figures 7 and 8 show the digital section for the ICL7116 and ICL7117, respectively. In the ICL7116, an internal digital ground is generated from a 6V Zener diode and a large P-Channel source follower. This supply is made stiff to absorb the relative large capacitive currents when the back plane (BP) voltage is switched. The BP frequency is the clock frequency divided by 800. For three readings/second this is a 60Hz square wave with a nominal amplitude of 5V. The segments are driven at the same frequency and amplitude and are in phase with BP when OFF, but out of phase when ON. In all cases negligible DC voltage exists across the segments. Figure 8 is the Digital Section of the ICL7117. It is identical to the ICL7116 except that the regulated supply and back plane drive have been eliminated and the segment drive has been increased from 2mA to 8mA, typical for instrument size common anode LED displays. Since the 1000 output (pin 19) must sink current from two LED segments, it has twice the drive capability or 16mA. In both devices, the polarity indication is "on" for negative analog inputs. If IN LO and IN HI are reversed, this indication can be reversed also, if desired.
FIGURE 6. EXCLUSIVE `OR' GATE FOR DECIMAL POINT DRIVE
HOLD Reading Input The HLDR input will prevent the latch from being updated when this input is at logic "1". The chip will continue to make A/D conversions, however, the results will not be updated to the internal latches until this input goes low. This input can be left open or connected to TEST (ICL7116) or GROUND (ICL7117) to continuously update the display. This input is CMOS compatible, and has a 70k (See Figure 7) typical resistance to either TEST (ICL7116) or GROUND (ICL7117).
a a b f g e d c b c f
a b g e d c e f
a b g c d
21 BACKPLANE
LCD PHASE DRIVER 7 SEGMENT DECODE 7 SEGMENT DECODE 7 SEGMENT DECODE
TYPICAL SEGMENT OUTPUT V+ 0.5mA SEGMENT OUTPUT 2mA 1000's COUNTER INTERNAL DIGITAL GROUND TO SWITCH DRIVERS FROM COMPARATOR OUTPUT
÷200
LATCH
100's COUNTER
10's COUNTER
1's COUNTER
35 V+
THREE INVERTERS
ONE INVERTER SHOWN FOR CLARITY
CLOCK
÷4
INTERNAL DIGITAL GROUND
LOGIC CONTROL
6.2V 500 TEST
70k
VTH = 1V
37
26 40 OSC 1 OSC 2 39 OSC 3 38 1 HLDR
V-
FIGURE 7. ICL7116 DIGITAL SECTION
8
ICL7116, ICL7117
a a b f g e d c b c f g e d c e d a b f g c a b
7 SEGMENT DECODE TYPICAL SEGMENT OUTPUT V+ 0.5mA TO SEGMENT 8mA DIGITAL GROUND TO SWITCH DRIVERS FROM COMPARATOR OUTPUT V+ CLOCK ÷4 1000's COUNTER 100's COUNTER
7 SEGMENT DECODE
7 SEGMENT DECODE
LATCH
10's COUNTER
1's COUNTER
35 V+ LOGIC CONTROL 500 21 DIGITAL GROUND 37 TEST
THREE INVERTERS
ONE INVERTER SHOWN FOR CLARITY 40 OSC 1 OSC 2 39 OSC 3 38
70k 1 HLDR
FIGURE 8. ICL7117 DIGITAL SECTION
System Timing Figure 9 shows the clocking arrangement used in the ICL7116 and ICL7117. Two basic clocking arrangements can be used: 1. Figure 9A, an external oscillator connected to pin 40. 2. Figure 9B, an R-C oscillator using all three pins. The oscillator frequency is divided by four before it clocks the decade counters. It is then further divided to form the three convert-cycle phases. These are signal integrate (1000 counts), reference de-integrate (0 to 2000 counts) and autozero (1000 counts to 3000 counts). For signals less than full scale, auto-zero gets the unused portion of reference deintegrate. This makes a complete measure cycle of 4,000 counts (16,000 clock pulses) independent of input voltage. For three readings/second, an oscillator frequency of 48kHz would be used. To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz, 331/3kHz, etc. should be selected. For 50Hz rejection, Oscillator frequencies of 200kHz, 100kHz, 662/3kHz, 50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5 readings/second) will reject both 50Hz and 60Hz (also 400Hz and 440Hz).
40 39 38 INTERNAL TO PART
÷4
CLOCK
GND ICL7117 TEST ICL7116
FIGURE 9A. EXTERNAL OSCILLATOR
INTERNAL TO PART
÷4
40 39 R 38 C
CLOCK
FIGURE 9B. RC OSCILLATOR FIGURE 9. CLOCK CIRCUITS
9
ICL7116, ICL7117 Component Value Selection
Integrating Resistor Both the buffer amplifier and the integrator have a class A output stage with 100µA of quiescent current. They can supply 4µA of drive current with negligible nonlinearity. The integrating resistor should be large enough to remain in this very linear region over the input voltage range, but small enough that undue leakage requirements are not placed on the PC board. For 2V full scale, 470k is near optimum and similarly a 47k for a 200mV scale. Integrating Capacitor The integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance buildup will not saturate the integrator swing (approximately. 0.5V from either supply). In the ICL7116 or the ICL7117, when the analog COMMON is used as a reference, a nominal +2V fullscale integrator swing is fine. For the ICL7117 with +5V supplies and analog COMMON tied to supply ground, a ±3.5V to +4V swing is nominal. For three readings/second (48kHz clock) nominal values for ClNT are 0.22µF and 0.1µF, respectively. Of course, if different oscillator frequencies are used, these values should be changed in inverse proportion to maintain the same output swing. An additional requirement of the integrating capacitor is that it must have a low dielectric absorption to prevent roll-over errors. While other types of capacitors are adequate for this application, polypropylene capacitors give undetectable errors at reasonable cost. Auto-Zero Capacitor The size of the auto-zero capacitor has some influence on the noise of the system. For 200mV full scale where noise is very important, a 0.47µF capacitor is recommended. On the 2V scale, a 0.047µF capacitor increases the speed of recovery from overload and is adequate for noise on this scale. Reference Capacitor A 0.1µF capacitor gives good results in most applications. Generally 1µF will hold the roll-over error to 0.5 counts in this instance. Oscillator Components For all ranges of frequency a 100k resistor is recommended and the capacitor is selected from the equation:
0.45 f = ------------ For 48kHz Clock (3 Readings/sec), C = 100pF. RC
FIGURE 10.
have a full scale reading when the voltage from the transducer is 0.682V. Instead of dividing the input down to 200mV, the designer should use the input voltage directly and select VREF = 0.341V. Suitable values for integrating resistor and capacitor would be 120k and 0.22µF. This makes the system slightly quieter and also avoids a divider network on the input. The ICL7117 with ±5V supplies can accept input signals up to ±4V. Another advantage of this system occurs when a digital reading of zero is desired for VIN 0. Temperature and weighing systems with a variable fare are examples. This offset reading can be conveniently generated by connecting the voltage transducer between IN HI and COMMON and the variable (or fixed) offset voltage between COMMON and IN LO. ICL7117 Power Supplies 3. The ICL7117 is designed to work from ±5V supplies. However, if a negative supply is not available, it can be generated from the clock output with 2 diodes, 2 capacitors, and an inexpensive lC. Figure 10 shows this application. See ICL7660 data sheet for an alternative.
V+
CD4009 V+ OSC 1 OSC 2 OSC 3 ICL7117 GND VIN914 + 10 µF
0.047 µF IN914
-
V- = 3.3V
GENERATING NEGATIVE SUPPLY FROM +5V
In fact, in selected applications no negative supply is required. The conditions to use a single +5V supply are: 1. The input signal can be referenced to the center of the common mode range of the converter. 2. The signal is less than ±1.5V. 3. An external reference is used.
Reference Voltage The analog input required to generate full scale output (2000 counts) is: VlN = 2VREF . Thus, for the 200mV and 2V scale, VREF should equal 100mV and 1V, respectively. However, in many applications where the A/D is connected to a transducer, there will exist a scale factor other than unity between the input voltage and the digital reading. For instance, in a weighing system, the designer might like to
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ICL7116, ICL7117 Typical Applications
The ICL7116 and ICL7117 may be used in a wide variety of configurations. The circuits which follow show some of the possibilities, and serve to illustrate the exceptional versatility of these A/D converters. The following application notes contain very useful information on understanding and applying this part and are available from Intersil Corporation.
Application Notes
NOTE # AN016 AN017 AN018 DESCRIPTION "Selecting A/D Converters" "The Integrating A/D Converter" "Do's and Don'ts of Applying A/D Converters" "Low Cost Digital Panel Meter Designs" "Understanding the Auto-Zero and Common Mode Performance of the ICL7136/7/9 Family" "Building a Battery-Operated Auto Ranging DVM with the ICL7106" "Games People Play with Intersil' A/D Converters," edited by Peter Bradshaw "Tips for Using Single Chip 31/2 Digit A/D Converters" AnswerFAX DOC. # 9016 9017 9018
AN023 AN032
9023 9032
AN046
9046
AN047
9047
AN052
9052
Typical Applications
OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 V+ 35 CREF 34 CREF 33 COMMON 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V - 26 G2 25 C3 24 A3 23 G3 22 BP 21
100k SET VREF = 100mV
OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 V+ 35 1k 22k
100k SET VREF = 100mV +5V 1k 0.1µF 1M 0.01µF 0.47µF 47k + IN 22k
100pF
100pF
0.1µF 1M 0.01µF 0.47µF 47k + IN
CREF 34 CREF 33 COMMON 32 IN HI 31
+
IN LO 30 A-Z 29 BUFF 28 INT 27 V - 26 G2 25 C3 24
-
0.22µF
9V
0.22µF
-5V
TO DISPLAY
A3 23 G3 22
TO DISPLAY
TO BACKPLANE
GND 21
Values shown are for 200mV full scale, 3 readings/sec., floating supply voltage (9V battery). FIGURE 11. ICL7116 USING THE INTERNAL REFERENCE
Values shown are for 200mV full scale, 3 readings/sec. IN LO may be tied to either COMMON for inputs floating with respect to supplies, or GND for single ended inputs. (See discussion under Analog COMMON.) FIGURE 12. ICL7117 USING THE INTERNAL REFERENCE
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ICL7116, ICL7117 Typical Applications
OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 V+ 35 CREF 34 CREF 33 COMMON 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V - 26 G2 25 C3 24 A3 23 G3 22 GND 21 TO DISPLAY 0.22µF V 0.01µF 0.047µF 470k 25k 0.1µF 1M + IN 24k V+ 100pF SET VREF = 1.000V
(Continued)
100k
OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 V+ 35 CREF 34 CREF 33 COMMON 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27
100k SET VREF = 100mV +5V 1k 10k 15k 0.1µF 1.2V (ICL8069) 1M 0.01µF 0.47µF 47k + IN
100pF
-
-
-
V - 26 G2 25 C3 24 A3 23 G3 22 GND 21
0.22µF
TO DISPLAY
An external reference must be used in this application, since the voltage between V+ and V- is insufficient for correct operation of the internal reference. FIGURE 13. ICL7116 AND ICL7117: RECOMMENDED COMPONENT VALUES FOR 2.0V FULL SCALE
V+ OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 V+ 35 CREF 34 CREF 33 COMMON 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V - 26 G2 25 C3 24 A3 23 G3 22 GND 21 TO DISPLAY 0.22µF V 0.47µF 47k 0.1µF 100pF 100k
FIGURE 14. ICL7117 OPERATED FROM SINGLE +5V SUPPLY
OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 V+ 35 CREF 34 CREF 33 COMMON 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V - 26 G2 25 C3 24 A3 23 G3 22 BP 21 0.1µF
100k
100pF
SCALE FACTOR ADJUST 22k
100k 1M 100k 220k
0.01µF 0.47µF 47k
ZERO ADJUST
SILICON NPN MPS 3704 OR SIMILAR 9V
0.22µF
TO DISPLAY
TO BACKPLANE
The resistor values within the bridge are determined by the desired sensitivity.
A silicon diode-connected transistor has a temperature coefficient of about -2mV/oC. Calibration is achieved by placing the sensing transistor in ice water and adjusting the zeroing potentiometer for a 000.0 reading. The sensor should then be placed in boiling water and the scale-factor potentiometer adjusted for a 100.0 reading. FIGURE 16. ICL7116 USED AS A DIGITAL CENTIGRADE THERMOMETER
FIGURE 15. ICL7117 MEASUREING RATIOMETRIC VALUES OF QUAD LOAD CELL
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ICL7116, ICL7117 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 1 2 3 N/2
E40.6 (JEDEC MS-011-AC ISSUE B)
40 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 3.18 0.356 0.77 0.204 50.3 0.13 15.24 12.32 MAX 6.35 4.95 0.558 1.77 0.381 53.2 15.87 14.73 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.125 0.014 0.030 0.008 1.980 0.005 0.600 0.485
MAX 0.250 0.195 0.022 0.070 0.015 2.095 0.625 0.580
A
E A2 L A C L
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1
A1 A2
-C-
B B1 C D D1 E
eA eC
C
e
C A B S
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E1 e eA eB L N
0.100 BSC 0.600 BSC 0.115 40 0.700 0.200
2.54 BSC 15.24 BSC 2.93 40 17.78 5.08
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ICL7116, ICL7117 Metric Plastic Quad Flatpack Packages (MQFP/PQFP)
D D1 -D-
Q44.10x10 (JEDEC MO-108AA-2 ISSUE A)
44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE SYMBOL A A1 A2 INCHES MIN 0.004 0.077 0.012 0.012 0.510 0.390 0.510 0.390 0.026 44 0.032 BSC MAX 0.093 0.010 0.083 0.018 0.016 0.530 0.398 0.530 0.398 0.037 MILLIMETERS MIN 0.10 1.95 0.30 0.30 12.95 9.90 12.95 9.90 0.65 44 0.80 BSC MAX 2.35 0.25 2.10 0.45 0.40 13.45 10.10 13.45 10.10 0.95 NOTES 6 3 4, 5 3 4, 5 7 Rev. 1 1/94 NOTES:
0.10 0.004
-AE E1
-B-
B B1 D D1 E
e
PIN 1 SEATING A PLANE
E1 L N e
-H-
0.40 0.016 MIN 0o MIN
5o-16o 0.20 A-B S 0.008 M C A2 A1
-CD S B B1 0.13/0.17 0.005/0.007 BASE METAL WITH PLATING
1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- . 4. Dimensions D1 and E1 to be determined at datum plane -H- . 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. "N" is the number of terminal positions.
0o-7o
L
5o-16o
0.13/0.23 0.005/0.009
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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