Text preview for : Lenovo G50-45 ACLU5 ACLU6 NM-A281.pdf part of Lenovo G50-45 Mainboard schematic
Back to : Lenovo G50-45 ACLU5 ACLU6 | Home
A B C D E
1 1
LCFC Confidential
G Project M/B Schematics Document
2 2
AMD FT3B Beema SOC with DDRIIIL
AMD JET-LE
2014-1-3
3
REV:0.3 3
4 4
Security Classification LC Future Center Secret Data Title
Issued Date 2013/08/15 Deciphered Date 2013/08/15 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
NM-A281 0.3
Date: Thursday, January 02, 2014 Sheet 1 of 60
A B C D E
A B C D E
LCFC confidential
File Name : ACLU5&6
AMD Jet LE/ Topaz XT
S3 Package: 23mmX23mm PCI-Express
Page 18~24
4x Gen2 Memory BUS (DDR3L)
Single Channel DDR3L-SO-DIMM X2
PEG 0~3 Page 14,15
VRAM 256/128*16
1
1.35V DDR3L 1600 MT/s 1
DDR3L*4 2GB/1GB UP TO 8G x 2
Page 25~26
HDMI
HDMI Conn. USB Left
Page 34 USB 3.0 1x
AMD FT3b APU USB 2.0 Port8
USB 3.0 Port0
VGA USB 2.0 2x JUSB2
CRT Conn. USB 2.0 Port3
Page 36 JUSB1 Page 41
eDP x2 Lane
eDP Conn
USB2.0 1x
Beema 15W /2.4G USB 2.0 1x Touch Screen
Int. Camera Page 33 USB2.0 Port4
USB2.0 Port5
(Integrated FCH)
2 2
Int. MIC Conn.
Page 33 USB2.0 1x USB Right
USB2.0 Port0
(Debug Port) JUSB3
SATA HDD SATA Gen3 USB2.0 1x
Page 42 SATA Port0 Cardreader Realtek SD/MMC Conn.
BGA-769
RTS5170 USB2.0 Port2
24.5mm*24.5mm USB Board
SATA ODD SATA Gen1
Page 42 SATA Port1
USB 2.0 1x
NGFF Card
LAN Realtek PCIe 1x WLAN&BT
RJ45 Conn. PCIe 1x PCIe Port1
Page 38
RTL8111GUL (1G) Page 40 USB2.0 Port6 Sub-board ( for 14")
RTL8106EUL (10M/100M)
3 3
Page 37 PCIe Port2
SPI BUS SPI ROM 0 POWER BOARD NS-A272
HD Audio
Page 4~9 8MB Page 07
USB Board NS-A271
Codec SPK Conn.
Conexant CX20752 Page 43
Page 43
Sub-board ( for 15")
EC
ITE IT8586E-LQFP POWER BOARD NS-A273
Page 44
HP&Mic Combo Conn. USB Board NS-A275
USB Board
Touch Pad Int.KBD Thermal Sensor ODD Board NS-A274
4 Page 45 Page 45 NCT7718W
Page 39
4
Security Classification LC Future Center Secret Data Title
Issued Date 2013/08/15 Deciphered Date 2013/08/15 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
NM-A281 0.3
Date: Thursday, January 02, 2014 Sheet 2 of 60
A B C D E
A B C D E
Voltage Rails ( O --> Means ON , X --> Means OFF ) Board ID need to be update!
SIGNAL BOARD
+5VS STATE SLP_S3# SLP_S5# +VALW +V +VS Clock Config. GPIOxx GPIOxx GPIOxx Function
+3VS 0 0 0
S0 (Full ON) HIGH HIGH ON ON ON ON
+1.8VS
power +1.5VS S1 (Power On Suspend) HIGH HIGH ON ON ON LOW
plane B+ +5VALW +1.35V +0.95VS
1
S3 (Suspend to RAM) LOW HIGH ON ON OFF OFF 1
(+VSYSMEN) +0.675VS
VL +3VALW S4 (Suspend to Disk) LOW LOW ON OFF OFF OFF
+APU_CORE
+APU_CORE_NB S5 (Soft OFF) LOW LOW ON OFF OFF OFF
+3VL +1.8VALW
+VGA_CORE
State
+0.95VALW +3VGS
+1.8VGS
+1.35VGS
USB Port Table BOM Structure Table
+0.95VGS
3 External BOM Structure BTO Item
USB 2.0 USB 3.0 Port
USB Port
@ Not stuff
S0 O O O O 0 RIGHT USB (2.0) Connector
ME@
1 N/A For 14" part
14@
S3
2 Card Reader For 15" part
O O O X 3 LEFT USB (2.0)
15@
EHCI UMA@ UMA SKU ID part
4 Touch Screen Discrete GPU SKU ID part
S5 S4/AC
PX@
2 O O X X 5 Camera 8106EUL LAN part 2
8106EUL@
6 Blue Tooth 8111GUL LAN Part
8111GUL@
S5 S4/ Battery only
7 N/A Giga LAN Part
O X X X GIGA@
0 8 LEFT USB (3.0) Touch Screen part
xHCI TS@
1 9 N/A Zero Power ODD part
S5 S4/AC & Battery
ZODD@
don't exist X X X X AOAC@ AOAC support part
HDT@ HDT Debug part
Kabini@ Kabini APU part
SMBUS Control Table PCIE PORT LIST SDV@ SDV PWR part
Port Device
SOURCE GPU BATT IT8586E SODIMM
WLAN Thermal APU Charger 0 N/A
Sensor
1 WLAN
EC_SMB_CK1
GPP
IT8586E IT8586E X 2 LAN
EC_SMB_DA1 X V X X X APU_SIC V 3 N/A
+3VALW +3VALW APU_SID
0
3 3
EC_SMB_CK2 1
IT8586E V X IT8586E
X X V V X GFX GPU
EC_SMB_DA2 APU_SIC
+3VS +3VS_VGA +3VS APU_SID
2
3
APU_SCLK0 APU
APU
APU_SDATA0 +3VS X X X V V X X S2G@ X76 SAMSUNG 2G
+3VS
M2G@ X76 MICRON 2G
H2G@ X76 HYNIX 2G
VRAM X76 SAMSUNG 1G
S1G@
M1G@ X76 MICRON 1G
EC SM Bus1 address EC SM Bus2 address H1G@ X76 HYNIX 2G
Device Address Device Address
Battery 0X16 Thermal Sensor 1001_100xb
Charger 0001 0010 b GPU 0x41(default)
APU Thermal Diode TBU
4
APU SM Bus address 4
Device Address
DDR DIMMA 1001 000Xb
DDR DIMMB 1001 010Xb
Security Classification LC Future Center Secret Data Title
WLAN RSVD
Issued Date 2013/08/15 Deciphered Date 2013/08/15 Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
NM-A281 0.3
Date: Thursday, January 02, 2014 Sheet 3 of 60
A B C D E
5 4 3 2 1
Beema (MEM & PCIE I/F)
D D
UC1A
OK<14,15> DDRA_MA[15..0] MEMORY
DDRA_DQ[63..0] OK
<14,15>
DDRA_MA0 AG38 M_ADD0 M_DATA0 B30 DDRA_DQ0
DDRA_MA1 W35 M_ADD1 M_DATA1 A32 DDRA_DQ1
DDRA_MA2 W38 M_ADD2 M_DATA2 B35 DDRA_DQ2
DDRA_MA3 W34 M_ADD3 M_DATA3 A36 DDRA_DQ3
DDRA_MA4 U38 M_ADD4 M_DATA4 B29 DDRA_DQ4
DDRA_MA5 U37 M_ADD5 M_DATA5 A30 DDRA_DQ5
DDRA_MA6 U34 M_ADD6 M_DATA6 A34 DDRA_DQ6
DDRA_MA7 R35 M_ADD7 M_DATA7 B34 DDRA_DQ7
DDRA_MA8 R38 M_ADD8
DDRA_MA9 N38 M_ADD9 M_DATA8 B37 DDRA_DQ8
DDRA_MA10 AG34 M_ADD10 M_DATA9 A38 DDRA_DQ9
DDRA_MA11 R34 M_ADD11 M_DATA10 D40 DDRA_DQ10
DDRA_MA12 N37 M_ADD12 M_DATA11 D41 DDRA_DQ11
DDRA_MA13 AN34 M_ADD13 M_DATA12 B36 DDRA_DQ12
DDRA_MA14 L38 M_ADD14 M_DATA13 A37 DDRA_DQ13
DDRA_MA15 L35 M_ADD15 M_DATA14 B41 DDRA_DQ14
M_DATA15 C40 DDRA_DQ15 UC1B
OK<14,15> DDRA_BS0# AJ38 M_BANK0 PCIE
DDRA_BS0#
OK<14,15> DDRA_BS1# AG35 M_BANK1 M_DATA16 F40 DDRA_DQ16
DDRA_BS1#
OK<14,15> DDRA_BS2# N34 M_BANK2 M_DATA17 F41 DDRA_DQ17
DDRA_BS2#
OK<14,15> M_DATA18 K40 DDRA_DQ18 R10 P_GPP_RXP0 P_GPP_TXP0 L2 Net name changed to same as ACLU1
DDRA_DM[7..0]
DDRA_DM0 B32 M_DM0 M_DATA19 K41 DDRA_DQ19 R8 P_GPP_RXN0 P_GPP_TXN0 L1
DDRA_DM1 B38 M_DM1 M_DATA20 E40 DDRA_DQ20
DDRA_DM2 G40 M_DM2 M_DATA21 E41 DDRA_DQ21 PCIE_PRX_DTX_P4 R5 P_GPP_RXP1 P_GPP_TXP1 K2 PCIE_PTX_DRX_P4 .1U_0402_10V6-K 1 2 CC21 PCIE_PTX_C_DRX_P4
<40> PCIE_PRX_DTX_P4 PCIE_PTX_C_DRX_P4 <40>
DDRA_DM3 N41 J40 DDRA_DQ22 OK PCIE_PRX_DTX_N4 R4 K1 PCIE_PTX_DRX_N4 .1U_0402_10V6-K 1 2 CC22 PCIE_PTX_C_DRX_N4
DDRA_DM4 AG40
M_DM3
M_DM4
M_DATA22
M_DATA23 J41 DDRA_DQ23 WLAN <40> PCIE_PRX_DTX_N4 P_GPP_RXN1 P_GPP_TXN1
PCIE_PTX_C_DRX_N4 <40>WLAN OK
DDRA_DM5 AN41 M_DM5 PCIE_PRX_DTX_P3 N5 P_GPP_RXP2 P_GPP_TXP2 J2 PCIE_PTX_DRX_P3 .1U_0402_10V6-K 1 2 CC19 PCIE_PTX_C_DRX_P3
<37> PCIE_PRX_DTX_P3 PCIE_PTX_C_DRX_P3 <37>
DDRA_DM6 AY40 M41 DDRA_DQ24 OK PCIE_PRX_DTX_N3 N4 J1 PCIE_PTX_DRX_N3 .1U_0402_10V6-K 1 2 CC20 PCIE_PTX_C_DRX_N3 OK
DDRA_DM7 AY34
M_DM6
M_DM7
M_DATA24
M_DATA25 N40 DDRA_DQ25 LAN <37> PCIE_PRX_DTX_N3 P_GPP_RXN2 P_GPP_TXN2
PCIE_PTX_C_DRX_N3 <37>LAN
TC10 @ 1 T_DDRA_DM8 Y40 M_DM8 M_DATA26 T41 DDRA_DQ26 N10 P_GPP_RXP3 P_GPP_TXP3 H2
U40 DDRA_DQ27 +0.95VS_GFX_APU N8 H1 +0.95VS_GFX_APU
M_DATA27 OK P_GPP_RXN3 P_GPP_TXN3 OK
DDRA_DQS0 B33 M_DQS_H0 M_DATA28 L40 DDRA_DQ28
C DDRA_DQS#0 A33 M_DQS_L0 M_DATA29 M40 DDRA_DQ29 1 2 P_TX_ZVDD W8 P_TX_ZVDD_095 P_RX_ZVDD_095 W7 P_RX_ZVDD 2 1 C
DDRA_DQS1 B40 M_DQS_H1 M_DATA30 R40 DDRA_DQ30 RC7 1.69K_0402_1% 1K_0402_1% RC8
DDRA_DQS#1 A40 M_DQS_L1 M_DATA31 T40 DDRA_DQ31
DDRA_DQS2 H41 M_DQS_H2
DDRA_DQS#2 H40 M_DQS_L2 M_DATA32 AF40 DDRA_DQ36 PCIE_CRX_GTX_P0 L5 P_GFX_RXP0 P_GFX_TXP0 G2 PCIE_CTX_GRX_P0 .1U_0402_10V6-K 1 2 CC11 PX@ PCIE_CTX_C_GRX_P0
OK <14,15> DDRA_DQS[0..7] DDRA_DQS3 P41 M_DQS_H3 M_DATA33 AF41 DDRA_DQ37 swap DQ32/33 and DQ36/37 @ 09/06 PCIE_CRX_GTX_N0 L4 P_GFX_RXN0 P_GFX_TXN0 G1 PCIE_CTX_GRX_N0 .1U_0402_10V6-K 1 2 CC12 PX@ PCIE_CTX_C_GRX_N0
DDRA_DQS[0..7]
DDRA_DQS#3 P40 M_DQS_L3 M_DATA34 AK40 DDRA_DQ34
OK DDRA_DQS#[0..7] DDRA_DQS4 AH41 M_DQS_H4 M_DATA35 AK41 DDRA_DQ35 PCIE_CRX_GTX_P1 J5 P_GFX_RXP1 P_GFX_TXP1 F2 PCIE_CTX_GRX_P1 .1U_0402_10V6-K 1 2 CC13 PX@ PCIE_CTX_C_GRX_P1
<14,15> DDRA_DQS#[0..7]
DDRA_DQS#4 AH40 AE40 DDRA_DQ32 PCIE_CRX_GTX_N1 J4 F1 PCIE_CTX_GRX_N1 .1U_0402_10V6-K 1 2 CC14 PX@ PCIE_CTX_C_GRX_N1
DDRA_DQS5 AP41
M_DQS_L4
M_DQS_H5
M_DATA36
M_DATA37 AE41 DDRA_DQ33
P_GFX_RXN1 P_GFX_TXN1
GPU
DDRA_DQS#5 AP40 M_DQS_L5 M_DATA38 AJ40 DDRA_DQ38 PCIE_CRX_GTX_P2 G5 P_GFX_RXP2 P_GFX_TXP2 E2 PCIE_CTX_GRX_P2 .1U_0402_10V6-K 1 2 CC15 PX@ PCIE_CTX_C_GRX_P2
DDRA_DQS6 BA40 M_DQS_H6 M_DATA39 AJ41 DDRA_DQ39 PCIE_CRX_GTX_N2 G4 P_GFX_RXN2 P_GFX_TXN2 E1 PCIE_CTX_GRX_N2 .1U_0402_10V6-K 1 2 CC16 PX@ PCIE_CTX_C_GRX_N2
DDRA_DQS#6 AY41 M_DQS_L6
DDRA_DQS7 AY33 M_DQS_H7 M_DATA40 AM41 DDRA_DQ40 PCIE_CRX_GTX_P3 D7 P_GFX_RXP3 P_GFX_TXP3 D2 PCIE_CTX_GRX_P3 .1U_0402_10V6-K 1 2 CC17 PX@ PCIE_CTX_C_GRX_P3
DDRA_DQS#7 BA34 M_DQS_L7 M_DATA41 AN40 DDRA_DQ41 PCIE_CRX_GTX_N3 E7 P_GFX_RXN3 P_GFX_TXN3 D1 PCIE_CTX_GRX_N3 .1U_0402_10V6-K 1 2 CC18 PX@ PCIE_CTX_C_GRX_N3
TC15 @ 1T_DDRA_DQS8 AA40 M_DQS_H8 M_DATA42 AT41 DDRA_DQ42
TC16 @ 1T_DDRA_DQS#8 Y41 AU40 DDRA_DQ43 ROUTE PCIE-LINK DIFF PAIR @ 85 OHM +/- 10%
M_DQS_L8 M_DATA43 OK<19> PCIE_CRX_GTX_P[0..3] PCIE_CTX_C_GRX_P[0..3] OK
<19>
M_DATA44 AL40 DDRA_DQ44
FT3 REV 0.53
DDRA_CLK0 AC35 M_CLK_H0 M_DATA45 AM40 DDRA_DQ45 OK<19> OK
<14> DDRA_CLK0 PCIE_CRX_GTX_N[0..3] PCIE_CTX_C_GRX_N[0..3] <19>
DDRA_CLK0# AC34 M_CLK_L0 M_DATA46 AR40 DDRA_DQ46 @ Beema FT3-REV-0P53_BGA769
<14> DDRA_CLK0#
OK SODIMM0 DDRA_CLK1 AA34 M_CLK_H1 M_DATA47 AT40 DDRA_DQ47
<14> DDR