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5 4 3 2 1
Wolverine-KY1-A3 ES66x8 + DV34/502W/S71/SONY310 PICKUP + OUTPUT
Layout---------Wolverine-KY1 REV-A3B3
D D
Background Revision History
This DVD design is based on ESS Vibratto-II ES66x8 single chip DVD mpeg and servo processor. The ES66x8 is built upon Rev-A1
ESS proven Programmable Multimedia Processor architecture with integrated servo DSP. A complete DVD design using Base on Escher-Y1 Rev-A3,
ES6603 RF-Amp can support all major popular optical pickup heads. With ES66x8 unify memory architecture, the whole
system memory is reduced to a minimum. ES66x8 provides the best price performance DVD solution in the industry. 1.Add J8,2x10 output jack for some media crads connection.
[email protected] 2.Add U19(IP1525), supply +3.3V and +2.0V
3.Add UU7(AVS2188),6 channel audio DAC
System Clock Requirement
4.Add UU8(AM5868),motor driver
ES66x8 require a 27MHz clock to operate. This 27MHz can either be generated externally and feed into pin 3 and pin 4 or
thru a 27MHz crystal attached to pin 2 and 3. This 27Mhz will be used for all video processing reference. In addition, internal 5.Add UU1(IP4504),motor driver
multiplier will generate a much higher operating frequency for the internal RISC+DSP code to operate. Audio clock is
generated from ES66x8 by its internal PLL circuitry. 6.Add CN2(SAMSUNG-S71),laser signal input jack
7.Add open/close transistor circuit option.
SDRAM Usage
Rev-A2
ES66x8 support the use of higher density 4Mx16 SDRAM. A sinlge of 4Mx16 SDRAM is sufficient for the whole system to
operate. Base on Wolverine-KY1 Rev-A1
1.Add R103\R104\R109\R110\R112\R114\R116\R118\R99\RR86\RR87
System Configuration
C C
Rev-A3
CHIP FUNCTION
Base on Wolverine-KY1 Rev-A2
ES66x8 Single chip processor that handles all system control, DVD decoding and servo control.
64MBit SDRAM Data storage and frame buffer 1.Add TP1\TP2\TP3\TP4\TP5\TP6\TP7\TP8\TP9\TP10
8Mbit EPROM/FLASH Program storage
2.Add R167\R169\R170\R165\R166\R121\R156\R161\R162\R163\R164
24C01 SERIAL EE System setup configuration storage
WM8728 2-Channel AudioDAC
WM8766/AVS2188 6-Channel AudioDAC
WM8738 2-Channel AudioADC
LCSx# FUNCTION
LCS0# SPARE
LCS1# Connect to J8
LCS2# 74HCT374 (U16) I/O EXPAND CONTROL ROM EMULATOR
LCS3# ROM/FLASH
B B
AUXx FUNCTION EAUXx FUNCTION
AUX0 I2C DATA EAXU40 AUDIODAC MD
AUX1 I2C CLOCK EAUX41 AUDIODAC MC
AUX2 MICMUTE / HSYNC EAUX42 AUDIODAC ML
AUX3 SCARTCTL / VSYNC EAUX43 NC
AUX4 IR
AUX5 VFD DATA
AUX6 VFD CS
AUX7 VFD CLK
XGPIOx FUNCTION
XGPIO4 MOCTL / RS232 DET
XGPIO5 CD_DVDCT
XGPIO6 OUTSW
XGPIO7 CLOSE
XGPIO8 HOMESW
A
XGPIO9 INSW A
ESS TECHNOLOGY, INC.
Title
INDEX
Size Document Number Rev
Wolverine-KY1 A3
Date: Sunday, November 02, 2003 Sheet 1 of 5
5 4 3 2 1
RR1 4.7K
VD33D VCC33 VCC33 VCC33 VCC33
RR2 4.7K JJ1
FLAG0
TXD
1 SERVO MCU MULTI Frequency
TP1
FLAG0
RS232_DET
RXD 2 DEBUG HEADER
PLL3
1
CLK SOURCE
DCLK INPUT
R1
OPEN
R2
OPEN
R3
OPEN
R4
OPEN
PLL2
0
PLL1
0
PLL0
0
DEFAULT
4.25
S-CHIP DEFAULT
4.5 114.75
S-CHIP
121.5
VIDEO OUTPUT TABLE
FLAG1 TP2 VCC 3 0 CRSTAL OSC 0 0 1 reserved 5 NA 135 CVBS + S-VIDEO CVBS + YUV S-VIDEO + RGB CVBS + RGB
FLAG1 4 0 1 0 bypass bypass 27 NA or CVBS + YUV
FLAG2 TP3 5 0 1 1 3.75 4 101.25 108 VDAC CVBS CVBS Y CVBS
SPDIF-IN
FLAG2 1 0 0 4.5 4.25 121.5 114.75 VCCV YDAC Y Y G G
FLAG3 SPDIF
TP4 1 0 1 reserved 4.75 NA 128.25 CDAC V V R R
TBCK
FLAG3 GND 1 1 0 3.5 5.5 94.5 148.5 UDAC U U B B
MCLK
1
DA TP5 1 1 1 4 6 108 162 D1 5DAC C CVBS C CVBS
TSD3
DA RS232 CONNECTOR 2.54MM CC1
SLEGP TSD2
TP6 CC2 1000P
TSD1
SLEGP 1000P CC3 VCCV VCC 1N6263
SLG TSD0 FB1
TP7 RFGND CC4 1000P L1 2.4UH
TWS FERB UDAC
21
SLG 1000P VCCV D2
SWBL TP8 SBAD RR3 3.3K R6
3 SBAD
SWBL FEI RR4 3.3K R7 R8 R9 R10 C1 C2
3 FEI
1
SWBLCLK TP9 CEI RR5 3.3K 4.7K 4.7K 4.7K 4.7K 4.7K D3 1N6263 75 OHM 470PF 470PF
3 CEI
SWBLCLK TEI RR6 3.3K R73
SFGIN 3 TEI
TP10
2
SFGIN CC5 1N6263 GNDV GNDV GNDV GNDV
DIP CC6 0.1U GND GND GND GND GND L2 2.4UH
3 DIP CDAC
21
4700P RR7 10K UDAC1 D4
RFO CC7 CDAC1 VCCV R11
3 RFO YDAC1
C CC8 4.7U C3 C4
1
CC9 VDAC1 1N6263 D5 75 OHM 470PF 470PF
C CC10 FDAC1
DIN CC11 1U
2
3 DIN
SVREF15
4700P CC12 GNDV 1N6263 GNDV GNDV GNDV
DEFCT 1U VCC33V L3 2.4UH
SDEFCT 3 YDAC
21
VCCV D6
SPDON RR8 68K R12
SLDC SPDON 3
R13 390R C5 C6
SLDC 3
1
RR9 20K C7 0.1U VCC33V D7 1N6263 75 OHM 470PF 470PF
VCC33 RF33V C8 0.1U
CC13 CC14 CC15 CC16
SVREF09
R14 0 OHM
SVREF21
2
4.7Kx4 RN4 1N6263 GNDV GNDV GNDV GNDV
SWBLCLK
MIRR
8 1 EAUX43 0.1U 0.1U 0.1U C GNDV L4 2.4UH
SPDIF-IN
VS33_PL2
VDAC
VCC33V
21
CDAC1
EAUX40
UDAC1
CC17 D8 VCCV
VCC20
YDAC1
VDAC1
7 2
FDAC1
GND
COMP
SPDIF
FLAG3
FLAG2
FLAG1
FLAG0
MCLK
SWBL
RXD
TBCK
TXD
TSD3
TSD2
TSD1
TSD0
RSET
EAUX42 6800P R15
VREF
TWS
GND
TESTAD
6 3
SLG
5 4 EAUX41 C9 C10
1
RFGND 1N6263 D9 75 OHM 470PF 470PF
RFGND VCC33
2
GNDV 1N6263 GNDV GNDV GNDV
U1 L5 2.4UH
FDAC
156
155
154
153
152
151
150
149
148
147
146
145
144