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8 7 6 5 4 3 2 1
CK ENG
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD APPD
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. REV ZONE ECN DESCRIPTION OF CHANGE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. DATE DATE
B 293301 PRODUCTION RELEASED 09/11/03 ?
D PAGE CONTENTS PAGE CONTENTS D
1 TITLE PAGE AND CONTENTS 22
23
VIDEO CONNECTORS - INVERTER, DVI, S-VIDEO
DUAL-CHANNEL LVDS
LMU, LIGHT SENSOR, BOOTBANGER, SLEEP LED
SCHEM,MLB,PB17"
2 SYSTEM BLOCK DIAGRAM SPIDEY - KBD,TPAD,HALL EFFECT,PWR BUTTON
3 POWER BLOCK DIAGRAM 24 INTERNAL CONNECTORS - DVD,
CARDSLOT, HARD DRIVE, LEFT USB/BLUETOOTH
09/04/2003
4 PCB NOTES AND HOLES 25 FAN CONTROLLER, MODEM, SOUND
SERIAL DEBUG (JOLLY ROGER, PWR/NMI/RESET) BOM OPTIONS STUFF NO STUFF
D3_HOT
5 MPC7450 MAXBUS INTERFACE 26 USB 2.0
D3_COLD
6 MPC7450 DATA 27 MARVELL GIGABIT ETHERNET PHY GPU_SS
GPU_SWITCH
7 CPU PLL AND CONFIGURATION STRAPS 28 FIREWIRE A/B PHY
SERIAL_DEBUG
C 8 INTREPID MAXBUS AND BOOT STRAPS 29 FIREWIRE A/B CONNECTORS, PORT POWER LIMITER VCORE_OFFSET C
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1_8V_MAXBUS
9 INTREPID MEMORY INTERFACE / BOOT ROM 30 PMU (POWER MANAGEMENT UNIT)
1_5V_MAXBUS
10 DDR MEMORY MUXES 31 BATTERY CHARGER AND CONNECTOR NEC_USB
INTREPID_USB
11 200PIN DDR MEMORY SODIMM CONNECTORS 32 12.8V SYSTEM POWER SUPPLY / PMU POWER SUPPLY
BBANG
12 INTREPID AGP 4X/PCI 33 3.3V / 5V SYSTEM POWER SUPPLIES NO_BBANG
13 INTREPID ENET/FW/UATA/EIDE INTERFACES 34 CPU CORE VOLTAGE POWER SUPPLY ATI_MEMIO_HI
ATI_MEMIO_LO
14 INTREPID GPIOS/SERIAL/USB INTERFACES/SSCG 35 1.5V/ 1.8V / 2.5V SYSTEM POWER SUPPLIES
SSCG
15 INTREPID POWER RAILS 36 SIGNAL CONSTRAINTS (1 OF 3) - DIGITAL/CLK NO_SSCG
5V_HD_LOGIC
B 16 INTREPID DECOUPLING 37 SIGNAL CONSTRAINTS (2 OF 3) - DIGITAL/DIFF B
3V_HD_LOGIC
17 CARDBUS CONTROLLER (PCI1510) 38 SIGNAL CONSTRAINTS (3 OF 3) - POWER NETS EXT_TMDS
INT_TMDS
18 M10 AGP & CLOCKS 39 FUNCTIONAL TEST POINTS
NO_4XVCORE
19 M10 LVDS/TMDS/VGA/GPIO & GPU VCORE 40 REVISION HISTORY (1 OF 1)
20 SIL1162 TMDS TRANSMITTER 41-42 SIGNAL NAMES
21 M10 ANALOG, POWER, GND 43-44 COMPONENT LOCATIONS
DIMENSIONS ARE IN MILLIMETERS
METRIC Apple Computer Inc.
XX
A X.XX
DRAFTER DESIGN CK NOTICE OF PROPRIETARY PROPERTY A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
X.XXX PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
ENG APPD MFG APPD
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
ANGLES II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
TABLE_5_HEAD QA APPD DESIGNER TITLE
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION DO NOT SCALE DRAWING
TABLE_5_ITEM
051-6531
820-1524
1
1
SCHEM,MLB,PB17 INCH
PCBF,MLB,PB17 INCH
SCH1
PCB1
TABLE_5_ITEM
RELEASE SCALE
NONE
SCHEM,MLB,PB17 INCH
SIZE DRAWING NUMBER REV.
MATERIAL/FINISH
NOTED AS D 051-6531 B
THIRD ANGLE PROJECTION APPLICABLE SHT 1 OF 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
J18 J24 J22
Ethernet FW - A FW - B
Connector Connector Connector SLEEP
P.30 P.30 LED LMU
P.28 J25 J19
P.26
2 DATA PAIRS
2 DATA PAIRS Battery Power Supply SUTRO (PWR)
4 DATA PAIRS @ 200MHz Connector & Charger
@ 400MHZ Connector
U28 D
D U49 J11 P.32 P.32-36 P.32
FireWire OPTICAL DRIVE
Ethernet PHY J14
PHY Connector U36
P.29 TUBA (SOUND) SMBUS
P.28 P.25
G/MII J13
Connector
P.26
3.3V LMU I2C
3.3V 1394 OHCI ULTRA ATA/100 U39
10/100/1000 3.3V Connector P.24
8BIT TX 8BIT TX/RX
100MHZ P.25
EIDE
I2S I2C
U48/J2/J4
Fan
PMU
8BIT RX
125MHZ I2C Circuit P.31 J10
UIDE P.26 CARDBUS
SERIAL
NOT USED Connector
J3 (SHARE WITH BLUETOOTH) 5V
ETHERNET FIREWIRE P.18
LEFT USB UATA 100 EIDE CARDSLOT I2S I2C J15
10/100/1000 800 MB/S P.14
P.14 P.14 P.14 P.15 J5
P.25 USB 2.0 P.14 P.14 P.15 TRACKPAD Keyboard 33MHZ
C USB PORT A SCCA
Serial Debug
Connector Connector 16/32 BITS C
J12 Connector 3.3V/5V
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P.15 P.15 KB LED U26
RIGHT USB NOT USED USB PORT B P.26
LIGHT SENSOR
BACKUP BATTERY
P.33
USB 2.0
P.15
USB PORT C
U44 VIA/PMU
P.15 U17
P.24 TI PCI1510
CardBus
P.15 U52
J3 (SHARE WITH LEFT USB)
BlueTooth NOT USED USB PORT D
INTREPID BOOTROM
P.14
BOOT ROM
1M X 8 USB 2.0
CONTROLLER
Controller
P.18
P.15 P.10
P.25 P.27
USB PORT E PCI
J9 P.15 32BITS PCI BUS
33MHZ 32BITS
Modem Board USB PORT F 33MHZ
P.15 P.13
Connector AGP BUS 3.3V
1.5V/3.3V U43
P.26
32BITS MEMORY MEMORY
MAXBUS J21
66MHZ CH. A CH. C
4X AGP
B INTRPEID
I2C MAXBUS
P.9
DDR MEMORY P.13 ATI M10 (INTERNAL MEM) (INTERNAL MEM) AIRPOPT
Connector
B
1.8V P.10 MEMORY MEMORY
167MHZ
32BIT ADDRESS MEMORY BUS
64MB CH. B CH. D
P.25
64BIT DATA 2.5V P.18-21 (INTERNAL MEM) (INTERNAL MEM)
167MHZ J8
U42 U11/U12/U13/U14 64BITS
EDID (I2C)
COMPOSITE
Inverter
S-VIDEO
CPU PLL 2:1 DDR MUXES Connector
APOLLO
(DDC TOO)
Config P.22
LVDS
TMDS
RGB
P.11
CPU P.7
J7 J17 J16
(MPC7457) PMU
P.5-6 LCD Panel S-Video DVI-I
J20/J23 Connector Connector Connector
DDR SDRAM DIMM 0 P.22 P.22 P.22 SYSTEM BLOCK DIAGRAM
A NOTICE OF PROPRIETARY PROPERTY
A
DDR SDRAM DIMM 1 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
SO-DIMM Connector I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
P.12 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6531 B
SCALE SHT OF
NONE 2 44
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
POWER SYSTEM ARCHITECTURE
+5V_MAIN
1V20_REF -
>~13.44V TURNS-ON
U21
PG 31
+
BACKLIGHT VCC MAP31 DDR I/O DCDC_EN
<~13.44V SHUTS-OFF
INVERTER MAP31 DDR CORE SLEEP
MAIN 2.5V/1.5V DDR POWER
+PBUS
D AC RUN/SS D
DC/DC +2.5V_MAIN
ADAPTER INRUSH BUCK MAXBUS
LIMITER +24V_PBUS REGULATOR (MAX1715) SEQUENCING
VCC
IN PG 30
+PBUS (12.8V) PG 35 PGOOD 1_5V_2_5V_OK
(LTC1625)
PG 31 PG 32 SHUTDOWN: STOPPED
14V_PBUS +5V_MAIN SLEEP: RUNNING +1.5V_MAIN
AC: 12.8V RUN: RUNNING
NO AC: BATTERY VOLTAGE INTREPID CORE
1625 NOT RUNNING TURNS ON OUTPUT @ 2.4V AGP I/O +5V_MAIN
ON1/ON2
SHUTDOWN: RUNNING
SLEEP: RUNNING VCC SHDN
RUN: RUNNING
+5V_MAIN
DCDC_EN_L
AFTER PMU IS UP AND RUNNING
DCDC_EN_L WILL PULL ON1/ON2
DC/DC
RC AT 1M*0.047UF @ 24V (MAX1717)
+3V_PMU STARTS 2.0MSEC AFTER DCDC_EN_L BECOMES LOW
LOW IN SHUTDOWN
+BATT
+5V_MAIN
PG 34
LDO +3V_PMU
RUN/SS - 5V EXT_VCC
+4_6V_BU TURNS ON AT >1V +5V_MAIN +PBUS (12.8V) SHUTDOWN: STOPPED
C PG 32
<100UA ALLOWED
INTERNAL ZENER CLAMP TO 6V
VCC DC/DC SLEEP: STOPPED C
(LTC1778) RUN: RUNNING
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MAIN 3V/5V PGOOD 3V_5V_OK
PG 20
GPU_VCORE
DC/DC SHUTDOWN: STOPPED +1.2V/+1.0V
(LTC3707) HOLDS BOTH RUN/SS AT GND
DCDC_EN SLEEP: D3HOT/D3COLD CPU_VCORE
VCC PG 33 STBYMD
WHEN IT'S CONNECTED TO GND
RUN: RUNNING (+1.4V/+1.5V)
TURNS CONTROL TO RUN/SS SLEEP
+PBUS WHEN IT'S OPEN
D3_COLD
TURNS ON AS LOW AS 0.8V/TYP 1.5V
SHUTDOWN: STOPPED INTERNAL 1.2UA CURRENT SOURCE
SLEEP: RUNNING GPU_VCORE RUN/SS
1_5V_2_5V_OK WILL NOT PULL LOW UNTIL
RUN: RUNNING SEQUENCING
BACKUP 12.8V CHARGES BACKUP BATTERY
INTERNAL ZENER CLAMP TO 6V
+3.3V_MAIN
+5V_MAIN TURNS ON
HOWEVER, 5V SHOULD TURN ON ~2.23MS AFTER
<100UA ALLOWED 1M & 0.1UF @14V, IT TAKES DCDC_EN_L OR PMU_POWERUP_L
BATTERY TURNS ON AT >1V
RUN/SS - 3V
~5.88MS TO START SWITCHER 1_5V_2_5V_OK
D3_HOT
BECOMES '1'; MUCH LESS THAN THE
RC CHARGING AT INT_VCC (5V)
DCDC_EN_L
D3_HOT
24V IS OUTPUT ONLY FROM
BACKUP BATTERY
RC AT 1M*0.1UF @ 24V
CHARGER INPUT STARTS ~4.25MSEC AFTER DCDC_EN_L BECOMES LOW
SHUT-DOWN RUN SLEEP RUN SHUT-DOWN
NO INRUSH PROTECTION
& BOOST OUTPUT WHEN ONLY BATTERY IS CONNECTED SLEEP
B PG 32 +24V_PBUS SLEEP_L_LS5 B
BACKUP BATTERY CIRCUIT CHARGES OFF +PBUS
DCDC_EN
AND PREVENTS +PBUS AND +24V_PBUS FROM DROPPING BELOW 6V DC/DC DCDC_EN_L
(UNTIL DRAINED)
(LTC3411) +5V_MAIN ~11MS
+1.8V_MAIN
BATTERY PG 35 +5V_SLEEP
MAXBUS +3V_MAIN ~13.5MS
CHARGER SHUTDOWN: STOPPED BROADCOM
SLEEP: STOPPED +3V_SLEEP
(MAX1772) RUN: RUNNING 3V_5V_OK 2.4V - ??? MS
PG 31 +2_5V_MAIN 2.6 MS
+2_5V_SLEEP
+BATT +1_5V_MAIN 2.6 MS
NO INRUSH PROTECTION +1_5V_SLEEP
3S 3P PRISMATIC CELLS WHEN ONLY BATTERY IS CONNECTED
1_5V_2_5V_OK
(MAX1715 OUTPUT)
BATTERY VOLTAGE 1_5V_2_5V_OK POWER BLOCK DIAGRAM
A +PBUS
(AT LTC1778 RUN/SS)
A