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1. CSS Bu,
1.1 CSS Bu, Overview
The system bus is an N-port time-division multiplexed transmission switch. AIly of the N ports
(backplane positions/slots) can send (receive) transmissions to (from) any of the N ports,
including itself. Each transmission consists of a source port address, a destination port address, a
transmission type and 8 bytes of "data n. The transmission type determines what the ndata" field
contains. Error detection is provided for the source slot address, destination slot address and
transmission type fields and optionally provided for the "data" field. The design value of N is 14
(ports); the design clock rate is 20 MHz.
Modules installed in bus ports interact with each other by exchanging transmissions over the bus.
There are two types of transmissions, COMMANDS and RESPONSES. A module on the bus
begins an interaction with another module by sending a OOMMAND. The source of the
OOMMAND is the MASTER for that interaction; the destination of the OOMMAND is the
SLAVE. The SLAVE sends a RESPONSE back to the MASTER if required to complete the
interaction.
1.2 CSS BU8 Operation
The OSS bus arbiter controls access to the bus. To transmit on the bus, a module issues a
request, a request modifier and a destination port address to the arbiter. If the request is to send
a COMMAND, the arbiter checks that the destination port has a COMMAND input buffer
available. A port with a COMMAND input buffer available is said to be READY. If the request
is to send a RESPONSE, the destination port is required to have to have enough RESPONSE
buffer space available for the size of the RESPONSE it requested. Ports wanting to send
COMMANDS to destinations that are READY and ports wanting to send RESPONSES arbitrate
for time slots on the bus. Arbitration occurs for each time slot.
Arbitration priority is determined by the port number of requesting port. Port N has the highest
priority, and port 0 the lowest. Computational modules as a group are assigned the lowest
priorities. A bus bandwidth spreading scheme insures that all computational modules get about
the same amount of access to the bus.
A module on the bus is READY to receive a COMMAND when it has at least one COMMAND
buffer free. Each module indicates to the arbiter how many OOMMAND buffers it has free. The
arbiter maintains a count of free OOMMAND buffers for each module and decrements the count
for the destination module as permission to send each COMMAND is GRANTED. Each module
in turn signals the arbiter to increment its free huffer (READY) count whenever one of the
module's COMMAND buffers becomes free.
The bus arbiter also supports interlocked sequences of operations. These sequences are required
to to support the TAS, OAS and CAS2 instructions of the Motorola 68020 and are a
generalization of the READ/MODIFY/WRITE operation. Interlocked sequences are atomic to
each other and are composed of any number of READ and WRITE commands. The signal
LOOK is asserted by the arbiter when an interlocked sequence is in progress. A interlocked
sequence begins when LOCK is not asserted and a port asserting BUS REQUEST and MODIFY
to the arbiter is granted the bus. The sequence ends when the port executing the sequence
de asserts MODIFY to the arbiter. To minimize performance loss, an interlocked sequence does
not lock out commands from ports not asserting MODIFY to the arbiter.
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The arbiter grants access to the bus by asserting GRANT to each module that wins an
arbitration. GRANT is asserted to a module for one time slot (clock cycle). A module receiving a
GRANT may transmit on the bus during the time slot immediately following the time slot in
which that GRANT was received.
When a module is GRANTED the bus to send a RESPONSE, the module may use the bus for up
to four consecutive time slots by asserting BURST to the arbiter during all but the last time slot.
The assertion of BURST during a time slot prevents the arbiter from issuing a GRANT to any
module for use of the bus during the next time slot. Only RESPONSES can be sent in BURST
mode. BURST mode RESPONSES can be to one or more destination ports.
When a module transmits on the bus, it asserts the signal BUS_ACTIVE to indicate the presence
of a transmission.
Each module monitors all bus transmissions. Each transmission is first checked for destination
field errors. A module recognises a transmission as addressed to it if the destination field contains
no detected errors and matches the module's port (slot) number. The transmission is then
checked for source and type field errors and optionally, parity errors in the data field. If the
transmission is a RESPONSE, it must be expected and the source field must be that of the
expected source.
Each transmission received without detected error is indicated by asserting ACK on the bus
during the second time slot after the transmission. Transmissions received with one or more
detected errors are indicated by asserting NACK on the bus during the second time slot. The sole
exception to this are transmissions of type CONTROL WRITE. These transmissions are ACKed
or NACKed based on the detection of errors in the source and type fields. Any detected errors in
~he data filed are ignored.
Only the destination port asserts ACK or NACK for a transmission. Transmissions with
destination field errors or destination fields not matching the port (slot) number of any installed
~odule are neither ACKed nor NACKed.
When a system bus transmission fails, retry is permitted, but not required. If retry is attempted,
the module that issued the COMMAND resulting in the failed transmission restarts the
transaction by reissuing the COMMAND.
1.9 Transmill3ion Format
Each transmission has a destination field, a source field, a type field and a data field. The
destination field contains the destination port number and, for error detection, the compliment of
the port number. The source field contains the source port number and its compliment. The
type field indicates the type of COMMAND or RESPONSE and the forml\t of the O:ltn fielrl. The
type field has a parity bit for single-bit error detection. A parity bit is also defined for each byte
of the data field for single-bit error detection, but implementation is optional. The sOllrce (If a
bus transmission indicates whether data parity bits have been sent.
The data field is organised as 8 bytes of 8 bits each. The bytes are numbered 0 through 7 with
byte 0 the most significant and of lowest address. Bits within a byte are numbered 7 through 0
with bit 7 the most significant. Each bit in the data field has a name of the form
BUS_DATA[B,b] where B is the byte number and b is the bit number within the byte. The
optional parity bit for byte B is BUS_DATA_P ARIB]. Data field parity is even. The bit
BUS_DATAPAR_VLD indicates whether data field parity is implemented.
System addressing is by 4 bits of physicaiport number and 32 bits of offset. The address of an
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operand is the address of its first (most significant and lowest address) byte.
The bus COMMANDS are as follows.
1. READ [sile = 1, 2, 3, 4, 8, 16 or 32 bytes]
The operand oC a READ command Cor 4 bytes or less must not cross a long word (4 byte)
boundary. The operand oC a READ command Cor 8, 18 or 32 bytes must be aligned on an
8, 18 or 32 byte boundary, respectively, and must not crOBS a 4 kilobyte page boundary.
READs oC 8, 16 and 32 bytes are not supported by all module types. The offset address oC
the operand is sent in bytes 4 through 7 of the data field. Bytes 0 through 3 of the data
field are undefined.
The operand is returned in the data field of one or more RESPONSE transmissions. The
operand is aligned in the data field for an 8 byte wide port. Bytes in the data field that are
not part of the requested operand are undefined.
Operands longer than 8 bytes require multiple 8 byte RESPONSE transmissions. Bytes are
returned in order of increasing byte address with the bytes oC lowest address returned first.
Multiple RESPONSE transmissions may be sent one at a time or in one or more bursts.
2. WRITE [size = 1,2,3 or 4 bytes]
The operand oC a WRITE command must not cross a long word boundary. The offset
address of the operand is sent in bytes 4 through 7 of the data field.
The WRITE data is sent in bytes 0 through 3 oC the data field and must be aligned Cor a 4
byte wide port.
3. CONTROL WRITE [signal = 0, 1, 2 or 3J [value = 0 or 1J
The CONTROL command allows one of several control signals in a module to be asserted
or deasserted even in the presence of errors in the "data" field. The specified signal is set to
the specified value. The data field is undefined.
The bus RESPONSES are as follows.
RESPONSE [response type = DATA, ERROR DATA 0, ERROR DATA 1 or ERROR]
1. DATA is the normal response to a READ command. A READ command Cor more than 8
bytes requires more than one RESPONSE transmission.
2. ERROR DATA is the" response to a READ command encountering a detected but
uncorredable data error. It contains the requested data as read or after correction has heen
attempted.
3. ERROR DATA 0 indicates that the error was detected by device responding to the READ.
4. ERROR DATA 1 indicates that the error was a transmission error detected by the 10
MODULE.
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5. ERROR is the response to a READ command that is somehow recognized as hll.ving failed
to read anything. The data field of the response is undefined.
The format of the transmission TYPE field is as follows.
BUSTYPE [5:0] = [3 bit type field],[3 bit modifier field]
BUSTYPE [5:3] type
o RESPONSE
1 Not Used (Reserved)
2 Not Used (Reserved)
3 READ
4 Not Used (Reserved)
5 WRITE
6 CONTROL WRITE
7 Not Used (Reserved)
BUS TYPE [2:0] size response type
o 4 bytes ERROR
1 1 byte
2 2 bytes ERROR DATA 0
3 3 bytes ERROR DATA 1
4 8 bytes DATA
5 16 bytes
6 32 bytes
7
BUSTYPE [2:1] control signal
o Not Used (Reserved)
1 module enable
2 module interface enable
3 Not Used (Reserved)
1.4 Tran8mi88ion ContJention8
With the exception of CONTROL WRITE, the target of a READ or WRITE command is
specified by its system address. Within a module, the range of defined offset addresses Ynri~s'
from 256 bytes to 4 gigabytes.
The offset address range OxFFFF FFOO through OxFFFF FFFF of all modules contains control
and status registers. Some modules also have higher level message buffers in this address range.
Some elements of this address range are found in more than one module and have the same
address in each module in which they appear. For instance, the ID of the module installed in a
bus port can be read at offset OxFFFF FFFF.
For ease of use and testing, any bit that can be written in a control register can be read at the
same byte and bit address and with the same sense. By definition, status registers are read-only.
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The number of offset a.ddress bits decoded depends on the module receiving a command. Memory
modules and i/o modules which support 4 OB olfset address spaces decode all onset address bits.
Computational modules and Service modules which support 256 byte address spaces decode only
the low order 8 offset address bits.
Use of the OxFFFF FFOO through OxFFFF FFFF is as follows.
OxFFFF FFOO-IF Higher level message buffers (Computational, Service & Test)
OxFFFF FFOO-03 Command bulfer
OxFFFF FF20-2F Reserved
OxFFFF FF30-3F Reserved
OxFFFF FF 40-4F Reserved
OxFFFF FF50-5F Reserved
OxFFFF FF60-63 Interrupt request (Service & Test)
OxFFFF FFSO-BF Interrupt acknowledge (Service & Test)
OxFFFF FFC4-C7 Interrupt vector (All)
OxFFFF FFCO-FF Control and Status registers (All)
OxFFFF FFE4-E7 Memory check bits and control (memory)
OxFFFF FFEC-EF Memory error information (memory)
OxFFFF FFF4-F7 Memory error address (memory)
OxFFFF FFFC-FE Memory status register (memory)
OxFFFF FFFC 68020 Interrupt request level (Computational)
OxFFFF FFFF Module ID (All)
1.5 Interface Specification
1.5.1 Bua Signala The bus signals are as follows.
i. BUS_DEST[3:0]
2. BUS_DEST[3:0] *
3. BUS_SRC[3:0]
4. BUS_SRC[3:0] *
5. BUS_TYPE [5:0]
6. BUS_TYPE_P ARITY
7. BUSJ)ATA[O:77]
S. BUS_DATAYAR[0:7]
9. BUS_DATAP AR_VLD
10. BUS_ACTIVE
11. BUS_ACK
12. BUS_NACK
The signals from the arbiter or backplane to each port are as follows.
Bus Clock.
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A delayed version of CLOCK