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W83627DHG
WINBOND LPC I/O
Note: This document is for UBC, UBE and UBF version
except specified descriptions
Date : April 10, 2007 Version : 1.4
W83627DHG
Data Sheet Revision History
WEB
PAGES DATES VERSION MAIN CONTENTS
VERSION
1 N.A. 12/15/2005 0.1 N.A. 1. First published version.
1. Add descriptions of the registers, functions,, AC/DC
2 N.A. 02/22/2006 0.2 N.A.
timing, and top marking
1. Revise Table 8.1 and the timing chart of section 10.3.1
2. Add registers for AMDSI at LDB, CRF5h,CRF6h and
F7h(Bank1)
3. Swap LDB, CRF2h bit 0 and bit 1.
3 N.A. 03/15/2006 0.3 N.A. 4. Modify the default values for LDA, CRFEh
5. Modify the descriptions of LD9, CR30h bit 0 and
CRF7h bit 4.
6. Remove LDA, CRE9h bit4 ~ 3
7. Swap LDC, CRE0h bit3~0 and CRE5h bit7~4
1. Add FDC, UART, Parallel Port and KBC interface
descriptions
2. Remove all the descriptions about AMDSI
3. Modify the diagrams and descriptions for Current Mode
4. Add two control bits for the selections of SYSFANOUT
and CPUFANOUT0 output type at CR[24h]
4 N.A. 05/05/2006 0.4 N.A. 5. Remove the description of the internal pulled-up
resistor of Parallel Port
6. Modify the definitions of edge/level and enable/disable
debounce circuit of GP30, GP31 and GP35
7. Modify the descriptions of LD7, CRF7h and LD9,
CRE6h ~ CRE9h
8. Correct typos and grammatical mistakes
1. Remove the remaining descriptions about AMDSI in
5 N.A 05/15/2006 0.41 N.A
datasheet ver.0.4
1. Add a note for Index# of FDC Interface and pin
83(GP42) of Serial Port & Infrared Port Interface in Pin
Description
2. Reserve the bit 7 of LD0, CRF0h
6 N.A. 05/19/2006 0.42 N.A 3. Modify the descriptions of TRAK0#, WP#, RDATA#
and DSKCHG# of FDC Interface
4. Modify the descriptions for strapping pins: HEFRAS,
PENROM, PENKBC and EN_GTL
5. Modify the DC spec.
1. Remove the note and renew the descriptions for
Index# of FDC Interface.
2. Correct the descriptions of HM Device Bank 0, CR[12h]
7 N.A. 06/23/2006 0.5 N.A. bit0.
3. Add two control bits for AUXFANOUT and
CPUFAOUT1 output type selection.
4. Add a new bit at LDC, CR[E8h] bit 1 for more PECI
Publication Release Date: Aug, 22, 2007
-I- Version 1.4
W83627DHG
WEB
PAGES DATES VERSION MAIN CONTENTS
VERSION
clock selection.
5. Modify the default values of HM Device Bank 0,
CR[43h] bit 5,0 and CR[46h] bit 2~1.
1. Add new chapters for Serial Peripheral Interface,
Configuration Register Access Protocol, Power
Management, Serialized IRQ, Watchdog Timer VID
Inputs and Outputs, and PCI Reset Buffers.
2. Update the feature lists of the W83627DHG in Chapter
2 Features.
3. Add descriptions of PECI and SST and a table of
SMBus in Chapter 5 Pin Description.
4. Add new sections of Caseopen and Beep Alarm
Function in Chapter 7 Hardware Monitor.
5. Add Clock Input Timing, PECI & SST Timing, and SPI
Timing in Chapter 21 Specifications.
6. Remove sections 9.4 and 9.5 (EXTFDD and
EXT2FDD).
7. Modify the descriptions of Hardware Monitor Device,
Bank 0, Index 59h, bits(6..4).
8. Add a beep control bit for VIN4 at Hardware Monitor
Device, Bank 0, Index 57h, bit6.
9. Remove status bit of PME# status of MIDI IRQ event at
8 N.A. 09/29/2006 0.6 N.A. Logical Device A, CRF4, bit 1.
10. Remove control bit of enable/disable PME# of MIDI at
Logical Device A, CRF7, bit 1.
11. Modify the descriptions of Tape Drive Register in
Chapter 10 Floppy Disk Controller.
12. Correct the description of Digital Input Register, bit
(6-4) in Chapter 10 Floppy Disk Controller.
13. Remove the description of "MR pin" in Digital Output
Register in Chapter 10 Floppy Disk Controller.
14. Adapt "Serial Flash Interface" to "Serial Peripheral
Interface".
15. Modify "Absolute Maximum Ratings" in Chapter 21
Specifications.
16. Remove "VDD is 5V