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RTL8181 Wireless LAN Access Point/Gateway Controller
DATA SHEET
ISSUE 4: June 10, 2003
RTL8181
Revision History
Issue Revision Details of Change Originator Issue Date
No
Issue 1 0.1 First Release David Hsu 11/29/2002
1. Add a section about system configuration.
Issue 2 0.2 David Hsu 12/9/2002
2. Add some descriptions about register usages.
3.
1. Add Pin number
Issue 3 0.3 Victor Hsu 03/03/2003
2. Add System config register
1. Add a memory map.
2. Modify some register definitions and function
descriptions.
Issue 4 1.0 Victor/David 2003/06/10
3. Add package information.
4. Remove 32 bits flash interface support
5. Add pin definitions for Maxim RF interface
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RTL8181
Table of Contents
1. OVERVIEW................................................................................................................................... 4
2. PIN DESCRIPTION ................................................................................................................. 5
3. ADDRESS MAPPING ........................................................................................................... 12
4. REGISTER MAPPING......................................................................................................... 13
5. SYSTEM CONFIGURATION.......................................................................................... 16
6. INTERRUPT CONTROLLER ........................................................................................ 17
7. MEMORY CONTROLLER............................................................................................... 18
8. ETHERNET CONTROLLER .......................................................................................... 21
9. UART CONTROLLER ......................................................................................................... 30
10. TIMER & WATCHDOG ................................................................................................... 33
11. GPIO CONTROL ................................................................................................................... 35
12. 802.11B WLAN CONTROLLER ................................................................................. 37
13. PACKAGE INFORMATION ......................................................................................... 48
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RTL8181
1. Overview
RTL8181 is a highly integrated SoC, embedded with a high-performance 32-bit RISC microcontroller, Ethernet and WLAN
controller. It is a cost-effective and high- performance solution for the system of wireless LAN Access Point, wireless SOHO
router, wireless Internet gateway, etc.
System block diagram:
EJTAG Microprocessor 802.11b MAC/BB RF transceiver
Timer MII
Ethernet MAC0
Cache buffer Ethernet PHY LAN
Watchdog
MII
MMU Ethernet MAC1 Ethernet PHY WAN
UART
Memory controller
GPIO PCI Bridge
PCI device
PCI device
Flash SDRAM
The embedded processor of RTL8181 is Lexra LX5280 32bit RISC CPU, with 8K separate instruction and data caches. A
protection unit (MMU) allows the memory be segmented and protected, and this unit is required in the modern operation
system (e.g., Linux).
The processor pipeline is a dual- issues and 6 stage architecture. The dual- issue CPU fetches two instructions per cycle, and
which could allow two instructions are executed concurrently in two pipes via some instructions. Thus, its performance will
achieve up to 30% improvement over uni-scalar architecture.
Besides, it includes two fast Ethernet MACs, one could be used for LAN interface and the other one could connect to WAN
port. An IEEE 802.11b WLAN MAC+Baseband processor is embedded as well. By this build- in wireless controller, it could
save a lot of costs and space comparing with the system designed with an external 802.11b adapter.
The RTL8181 also integrates with memory controller, which allows customers use external SDRAM and Flash memory in
glueless.
A PCI interface is supported as well, which enables customers to plug in a PCI device seamlessly. For example, an IEEE
802.11a device could be connected through this PCI interface to provide the WLAN dual mode service.
Features
Core Processor
? LX5280 32-bit RISC architecture.
? Superscalar architecture, containing 2 execution pipelines with better performance
? Embedded with 8K I-Cache, 8K D-Cache and 4K D-RAM.
? MMU supported
? Up to 200MHZ operating frequency
WLAN Controller
? Integrated IEEE 802.11b complied MAC and DSSS Baseband processor
? Support Tx data rate in 11M, 5.5M, 2M and 1M
? Support long and short preamble
? Support antenna diversity and AGC.
? Embedded with encryption/decryption engine for 64 bits and 1 28 bits WEP
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RTL8181
Fast Ethernet Controller
? Fully compliant with IEEE 802.3/802.3u
? Support MII interface with full and half duplex capability
? Support descriptor-based buffer management with scatter-gather capability
? Support IP, TCP and UDP checksum offload
? Support IEEE 802.1Q VLAN tagging and 802.1P priority queue.
? Support full duplex flow control (IEEE 802.3X)
UART
? 16550 compatible
? 16 bytes FIFO size
? Auto CTS/RTS flow control
Memory Controller
? Support external 16/32-bit SDRAM with 2 banks access, up to 32M bytes
? Support external 16-bit Flash memory, up to 16M bytes
PCI Bridge
? Support two external PCI devices, complied with PCI 2.2
? Support PCI master/slave mode
? 3.3 and 5V I/O tolerance
GPIO
? 16 programmable I/O ports and more 16 port when memory interface is 16 bit mode.
? Individually configurable to input, output and edge transition
Watchdog/Timer/Counter
? A hardware watchdog timer, used to reset processor when system hangs up
? 4 sets of general timers/counters
EJTAG
? Standard P1149.1 JTAG interface for testing and debugging
2. Pin Description
Symbol Typ Pin No(208) Pin No(292) Description
e
Memory Interface
MD[31-0] I/O 198,197,195 P1,P2,N3,N Data for SDRAM, Flash.
,194,193,19 2,N1,M3,M
2,191,190,1 2,M1,L2,L3,
88,187,185, L1,K2,K3,K
184,182,181 1,J2,J1,H2,
,180,179,17 H1,G2,F1,G
7,176,174,1 3,F2,E1,F3,
73,171,170, E2,D1,D2,E
169,168,166 3,A1,B1,B2,
,165,163,16 C3
2,161,160,1
59,158
MA[21-0]/ O 115,116,118 B14,A15,D1 Address for SDRAM, Flash.
DQM[3-0] ,119,121,12 4,C14,A14, MA[15-18] mapping to DQM[3-0] for SDRAM
2,124,125,1 C13,B13,C1
27,128,130, 2,A12,C11,
131,133,134 B11,C10,A1
,135,136,13 1,B10,A10,
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RTL8181
8,139,141,1 C9,A9,B9,A
42,144 7,C7,B7,A6
M_CLK O 152 A5 SDRAM clock
MCS0B O 150 C5 Bank 0 chip select FLASH chip select
MCS1B O 149 B5, Bank 1 chip select FLASH chip select
RASB/OE O 157 D4 Raw address strobe for SDRAM;
B Output enable for Flash
CASB O 156 A2 Column address strobe
MWENB O 154 B4 Write enable for SDRAM and Flash
MCKE O 153 A4 SDRAM Clock enable
MCS2B O 147 D5 Bank 0 chip select for SDRAM
MCS3B O 146 B6 Bank 1 chip select for SDRAM
UART Interface
URTSB O 16 Y8 UART Request to send
UCTSB I 14 W7 UART Clear to send.
USIN I 15 Y7 UART data receive serial input
USOUT O 17 V8 UART data transmit serial output
Power & GND
PP[11-1] P 208,178,164
K4,G4,F4,E I/O power 3.3V (Digital),
,151,137,12
4,D13,D12,
3,83,58,52,3
D11,B18,B1
0,4 7,A19,A18,
K17,P4,P17,
R17,U7,U8,
U14,U15
GP[11-1] P 204,189,167 K12,K11,K I/O 3.3V GND (Digital)
,155,140,12 10,K9,K8,J1
6,80,63,42,2 2,J11,J10,J9
0,1 ,H11,H10,K
13,L8,L9,L1
0,L11,L12,L
13,M9,M10,
M11,N10,N
11
PD[7:5],PS P 183,175,132 N17,M4,L4, Core logic power 1.8V (Digital)
[5:3] ,196,148,74 N4,U10,U1
1
GD[7-5],G P 186,172,129 M8,J13,J8,R Core logic 1.8Ground (Digital)
S[5-3] ,199,145,77 4,R3,J17
PA[6-1] P 111,104,92,1 D16,D15,C1 Wireless LAN power 3.3V(Analog)
13,98,89 5,C17,D20,
G19
GA[6-1],G P 108,107,95, G17,F17,E1 Wireless LAN Ground (Analog), GA7 VSUB
A7 114,100,86, 7,C16,D19,
112 G20,A20
PD[4-1] P 120,72,48,2 J4,H4,D10, Core logic 1.8V power(Digital)
8 D9
GD[4-1] P 117,69,45,2 H13,H12,H Core logic LAN Ground(Digital)
5 9,H8,M12,
M13,N8,N9,
N12,N13
PS[2:1] P 36,7 D6,C6,U4,U Core logic power 1.8V(Digital)
5,U12,L17,
M17
GS[2:1] P 39,10 D8,D7,T4,U Core logic 1.8V GND
6,U13
WLAN Traffic LED Control
WLTXRX O 65 T19 WLAN Tx/Rx traffic indicator or JTAG reset.
LED0B
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RTL8181
WLTXRX O 64 T18 WLAN Tx/Rx traffic indicator or JTAG CLK
LED1B
RF Interface for Intersil
RIFSCK O 66 R20 3-wire Bus Clock
RIFSD O 67 P19 3-wire Bus Data
RFLE O 68 P18 3-wire Bus Enable
IFLE/AGC O 70 N18 IF_LE of the Intersil Chipset: PLL Synthesizer Serial Interface Latch Enable
SET Control. CMOS output.
CALEN/ O 71 P20 CAL_EN of the Intersil Chipset: CMOS output for activation of DC offset adjust
AGCRESE circuit. A rising edge activates the calibration cycle, which completes within a
T programmable time and holds the calibration while this pin is held high. In
applications where the synthesizer is not used, this pin needs to be grounded.
LNA_HL O 73 M19 Drive to the RF AGC Stage Attenuator: CMOS digital.
ANTSELP O 75 M20 Antenna Select +: The antenna selects signal changes state as the receiver
switches from antenna to antenna during the acquisition process in the antenna
diversity mode. This is a complement for ANTSELN for differential drive of
ant enna switches.
ANTSELN O 76 L18 Antenna Select -: The antenna selects signal changes state as the receiver
switches from antenna to antenna during the acquisition process in the antenna
diversity mode. This is a complement for ANTSELP for differential drive of
antenna switches.
TRSWP O 78 L19 Transmit/Receive Control
TRSWN O 79 L20
VCOPDN/ O 81 K20 Output Pin as VCO VCC Power Enable/Disable.
PHITXI
PAPE O 82 K19 Transmit PA Power Enable
PE1/PHIT O 84 K18 The combination of PE1 and PE2 are as follows:
XQ 00: Power Down State, PLL Registers in Save Mode, Inactive PLL, Active Serial
11: Receive State, Active PLL
10: Transmit State, Active PLL
01: Inactive Transmit and Receive States, Active PLL, Active Serial Interface
PE2 O 85 J20 Output Pin as PE2: Refer to PE1 description.
RXIP AI 110 B19 Receive (Rx) In-phase Differential Analog Data
RXIN AI 109 B20
RXQP AI 106 C18,C19 Receive (Rx) Quadrature Differential Analog Data
RXQN AI
RSSI AI 105 D17 Analog Input to the Receive Power A/D Converter for AGC Control
TXDET AI 102 D18 Input to the Transmit Power A/D Converter for Transmit AGC Control
VREFI AI 101 C20 Voltage Reference for ADC and DAC
TXIP AO 97 E19,F18 Transmit (TX) In-phase Differential Analog Data
TXIN AO 96
TXQP AO 94 E20,F20 Trans mit (TX) Quadrature Differential Analog Data
TXQN AO 93
TXAGC AO 91 F19 Analog Drive to the Transmit IF Power Control
RXAGC AO 90 G18 Analog Drive to the Receive IF AGC Control
RF Interface for RFMD
RIFSCK O 66 R20 3-wire Bus Clock: The serial clock output, with resistive dividers on board to
allow programming from +5V levels.
RIFSD O 67 P19 3-wire Bus Data: Serial data output, with resistive dividers on board to allow
programming from +5V levels.
RFLE O 68 P18 3-wire Bus Enable: Enable serial port output, with resistive dividers on board to
allow programming from +5V levels.
IFLE/AGC X* 70 N18 Not used in the RFMD RF chipset.
SET
CALEN/ X 71 P20 Not used in the RFMD RF chipset.
AGCRESE
T
LNA_HL O 73 M19 RF2494 Gain Select: Digital output.
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RTL8181
ANTSELP O 75 M20 Antenna Select +: The antenna selects signal changes state as the receiver
switches from antenna to antenna during the acquisition process in the antenna
diversity mode. This is a complement for ANTSEL- for differential drive of
antenna switches.
ANTSELN X 76 L18 Not used in the RFMD RF chipset.
TRSWP X 78 L19 Not used in the RFMD RF chipset.
TRSWN X 79 L20 Not used in the RFMD RF chipset.
VCOPDN/ O/I 81 K20 Output Pin as VCO VCC Power Enable/Disable.
PHITXI
PAPE O 82 K19 Power Control Output for RF2189 PA: 0V to +3.3V.
PE1/PHIT O 84 K18 This pin is the shutdown control output on board regulator when the RF Module
XQ enters either power-saving or standby mode.
PE2 O 85 J20 Output pin as RF2948 RX EN/ TX EN, RF2494 OE and CE:
Refer to the RF2948 and RF2494 datasheets.
RXIP AI* 110 B19 Receive (Rx) In-phase Analog Data in Single Ended
RXIN X 109 B20 Not used in RFMD RF chipset.
RXQP AI 106 C18 Receive (Rx) Quadrature-phase Analog Data in Single Ended
RXQN X 105 C19 Not used in RFMD RF chipset.
RSSI X 103 D17 Not used in RFMD RF chipset.
TXDET AI 102 D18 To internal ADC which detects transmit power.
VREFI AI 101 C20 Reference voltage for ADC, DAC from VREF1 of RF2948B.
TXIP AO 97 E19 Transmit (TX) In-phase Digital Data: Combining before connecting to TX_I of
TXIN AO 96 F18 RF2948B.
TXQP AO 94 E20 Transmit (TX) Quadrature Digital Data: Combining before connecting to TX_Q
TXQN AO 93 F20 of RF2948B.
TXAGC AO 91 F19 Transmit gain control output to RF2948.
RXAGC AO 90 G18 RF2948 VGC receiver gain control analog output.
RF Interface for Philip
RIFSCK O 66 R20 3-wire Bus Clock: The pin RIFSCK is the "shift clock" output. If the 3-wire bus
is enabled, address or data bits will be clocked out from the RIFSD pin with
rising edges of RIFSCK.
RIFSD O 67 P19 3-wire Bus Data: The pin RIFSD is the output "data" pin. The detail timing is on
11.3.3.
RFLE O 68 P18 3-wire Bus Enable: The pin RFLE is an "enable" signal. It is level sensitive: If
RFLE is of LOW value, the 3-wire bus interface on the SA2400 is enabled. This
means that each rising edge on the RIFSCK pin will be taken as a shift cycle,
and address/data bits are expected on RIFSD. If RFLE is HIGH, the 3-wire bus
interface is disabled. No register settings will change regardless activity on
RIFSCK and RIFSD.
IFLE/AGC I 70 N18 AGCSET of the Philips Chipset: On the digital output pin AGCRESET, a 0 => 1
SET transition clears AGCSET of SA2400 to logic 0 and SA2400 starts the AGC
cycle. At end of AGC cycle, the AGCSET of SA2400 is asserted to logic 1. Then,
AGCRESET will return to logic low.
CALEN/ O 71 P20 AGCRESET of the Philips Chipset: Please refer to the AGCSET description and
AGCRESE Philips SA2400 datasheet.
T
LNA_HL X* 73 M19 Not used in Philips RF chipset.
ANTSELP O 75 M20 Antenna Select +: The antenna selects signal changes state as the receiver
switches from antenna to antenna during the acquisition process in the antenna
diversity mode. This is a complement for ANTSEL- for differential drive of
antenna switches.
ANTSELN O 76 L18 Antenna Select -: The antenna selects signal changes state as the receiver
switches from antenna to antenna during the acquisition process in the antenna
diversity mode. This is a complement for ANTSEL+ for differential drive of
antenna switches.
TRSWP O 78 L19 Transmit and Receive Switch Control: This is a complement for TRSW-.
1:TX
0:RX
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RTL8181
TRSWN O 79 L20 Transmit and Receive Switch Control: This is a complement for TRSW+.
1:RX
0:TX
VCOPDN/ O/I 81 K20 Output Pin as Transmit (TX) In-phase Digital Data of the Philips Chipset. This
PHITXI/ function is valid on Tx digital mode (AnalogPhy = Digital on EEPROM writer
program).
PAPE O 82 K19 Transmit PA Power Enable: Assert high when starting transmission.
PE1/PHIT O 84 K18 Transmit (TX) Quadrature Digital Data of Philips Chipset. This function is valid
XQ on Tx digital mode (AnalogPhy = Digital on EEPROM writer program).
PE2 O 85 J20 Output Pin as TX/RX Control:
1:RX
0:TX
RXIP AI* 110 B19 Receive (Rx) In-phase Analog Data: Positive path of differential pair.
RXIN AI 109 B20 Receive (Rx) In-phase Analog Data: Negative path of differential pair.
RXQP AI 106 C18 Receive (Rx) Quadrature-phase Analog Data: Positive path of the differential
pair.
RXQN AI 105 C19 Receive (Rx) Quadrature-phase Analog Data: Negative path of the differential
pair.
RSSI AI 103 D17 Received Signal Strength Indication: To internal ADC.
TXDET AI 102 D18 Transmit Power Detect: To internal ADC which detects transmit power.
VREFI AI 101 C20 Reference Voltage for ADC & DAC
TXIP AO 97 E19 Transmit (Tx) In-phase Analog Data: Positive path of differential pair. This
function is valid on Tx digital mode (AnalogPhy = Digital on EEPROM writer
program).
TXIN AO 96 F18 Transmit (Tx) In-phase Analog Data: Negative path of differential pair. This
function is valid on Tx digital mode (AnalogPhy = Digital on EEPROM writer
program).
TXQP AO 94 E20 Transmit (Tx) Quadrature-phase Analog Data: Positive path of the differential
pair. This function is valid on Tx digital mode (AnalogPhy = Digital on
EEPROM writer program).
TXQN AO 93 F20 Transmit (Tx) Quadrature-phase Analog Data: Negative path of the differential
pair. This function is valid on Tx digital mode (AnalogPhy = Digital on
EEPROM writer program).
TXAGC X 91 F19 Not used in Philips RF chipset
RXAGC X 90 G18 Not used in Philips RF chipset
RF Interface for Maxim
RIFSCK O 66 R20 3-wire Bus Clock: The serial clock output
RIFSD O 67 P19 3-wire Bus Data: Serial data output
RFLE O 68 P18 3-wire Bus Enable: Enable serial port output
IFLE/AGC X* 70 N18 Not used in the Maxim RF chipset.
SET
CALEN/ X 71 P20 Not used in the Maxim RF chipset.
AGCRESE
T
LNA_HL O 73 M19 LNA Gain Select Logic Output: Logic high for LNA high-gain mode, logic low
for LNA low- gain mode.
ANTSELP O 75 M20 Antenna Select +: The antenna selects signal changes state as the receiver
switches from antenna to antenna during the acquisition process in the antenna
diversity mode. This is a complement for ANTSEL- for differential drive of
antenna switches.
ANTSELN X 76 L18 Antenna Select -: The antenna selects signal changes state as the receiver
switches from antenna to antenna during the acquisition process in the antenna
diversity mode. This is a complement for ANTSEL+ for differential drive of
antenna switches.
TRSWP X 78 L19 Not used in the Maxim RF chipset.
TRSWN X 79 L20 Not used in the Maxim RF chipset.
VCOPDN/ O/I 81 K20 Output Pin as VCO VCC Power Enable/Disable.
PHITXI
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RTL8181
PAPE O 82 K19 Transmit PA Power Enable: Assert high when starting transmission.
PE1/PHIT O 84 K18 Not used in the Maxim RF chipset.
XQ
PE2 O 85 J20 Not used in the Maxim RF chipset now.
RXIP AI* 110 B19 Receive (Rx) In-phase Analog Data: Positive path of differential pair.
RXIN X 109 B20 Receive (Rx) In-phase Analog Data: Negative path of differential pair.
RXQP AI 106 C18 Receive (Rx) Quadrature-phase Analog Data: Positive path of differential pair.
RXQN X 105 C19 Receive (Rx) Quadrature-phase Analog Data: negative path of differential pair.
RSSI X 103 D17 Not used in Maxim RF chipset.
TXDET AI 102 D18 To internal ADC which detects transmit power.
VREFI AI 101 C20 Not used in Maxim RF chipset.
TXIP AO 97 E19 Transmit (TX) In-phase Digital Data: Combining before connecting to TX_I of
TXIN AO 96 F18 RF2948B.
TXQP AO 94 E20 Transmit (TX) Quadrature Digital Data: Combining before connecting to TX_Q
TXQN AO 93 F20 of RF2948B.
TXAGC AO 91 F19 Transmit gain control output to RF2948.
RXAGC AO 90 G18 Analog Drive to the Receive r AGC Control.
Miscellaneous
R10K I/O 99 E18 This pin must be pulled low by a 10K O resistor.
XO O 87 H18 Crystal Feedback Output: This output is reserved for crystal connection. It should
be left open when XI is driven with an external 44 MHz oscillator.
XI I 88 H19 44 MHz OSC Input
PCI Interface
AD31-0 T/S *X A13,B12,A8 PCI address and data multiplexed pins. The address phase is the first clock cycle in
,C8,B8,C4, which FRAMEB is asserted. During the address phase, AD31-0 contains a physical
B3,A3,C2,D address (32 bits). For I/O, this is a byte address, and for configuration and memory, it
3,C1,G1,H3, is a double-word address. Write data is stable and valid when IRDYB is asserted. Read
J3,V2,V1,V data is stable and valid when TRDYB is asserted. Data I is transferred during those
3,W2,V4,w clocks where both IRDYB and TRDYB are asserted.
3,Y3,W6,Y
6,V7,Y14,
W14,Y15,Y
19,U16,R18
,T20,R19
C/BE3-0 T/S *X W20,V19,U PCI bus command and byte enables multiplexed pins. During the address phase
17,V20 of a transaction, C/BE3-0 define the bus command. During the data phase,
C/BE3-0 are used as Byte Enables. The Byte Enables are valid for the entire data
phase and determine which byte lanes carry meaningful data. C/BE0 applies to
byte 0, and C/BE3 applies to byte 3.
CLK O *X N19 PCI clock: This clock input provides timing for all PCI transactions and is input
to the PCI device.
DEVSELB S/T/ *X P3 Device Select: As a bus master, the RTL8181 samples this signal to insure that a
S PCI target recognizes the destination address for the data transfer.
FRAMEB S/T/ *X N20 Cycle Frame: As a bus master, this pin indicates the beginning and duration of an
S access. FRAMEB is asserted low to indicate the start of a bus transaction. While
FRAMEB is asserted, data transfer continues. When FRAMEB is deasserted, the
transaction is in the final data phase.
As a target, the device monitors this signal before decoding the address to check
if the current transaction is addressed to it.
GNTB T/S *X H20 Grant:Grant indicate to the agent that access to the bus has been granted.
REQB T/S *X J18 Request: Request indicates to the ar biter that this agent desires use of the bus.
IDSEL O *X A16 Initialization Device Select: This pin is used as a chip select during configuration
read and write transactions..
INTAB O/D *X A17 Interrupt A: Used to request an interrupt. It is asserted low when an interrupt
condition occurs, as defined by the Interrupt Status, Interrupt Mask.
IRDYB S/T/ *X M18 Initiator Ready: This indicates the initiating agent's ability to complete the
S current data phase of the transaction.
As a bus master, this signal will be asserted low when the RTL8181 is ready to
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RTL8181
complete the current data phase transaction. This signal is used in conjunction
with the TRDYB signal. Data transaction takes place at the rising edge of CLK
when both IRDYB and TRDYB are asserted low. As a target, this signal indicates
that the master has put data on the bus.
TRDYB S/T/ *X J19 Target Ready: This indicates the target agent's ability to complete the current
S phase of the transaction.
As a bus master, this signal indicates that the target is ready for the data during
write operations and with the data during read operations. As a target, this signal
will be asserted low when the (slave) device is ready to complete the current data
phase transaction. This signal is used in conjunction with the IRDYB signal. Data
transaction takes place at the rising edge of CLK when both IRDYB and TRDYB
are asserted low.
PAR T/S *X R2 Parity: This signal indicates even parity across AD31-0 and C/BE3-0 including
the PAR pin. PAR is stable and valid one clock after each address phase. For data
phase, PAR is stable and valid one clock after either IRDYB is asserted on a
write transaction or TRDYB is asserted on a read transaction. Once PAR is valid,
it remains valid until one clock after the completion of the current data phase. As
a bus master, PAR is asserted during address and write data phases. As a target,
PAR is asserted during read data phases.
STOPB S/T/ *X B16 Stop: Indicates that the current target is requesting the master to stop the current
S transaction.
RSTB O *X B15 Reset: Active low signal to reset the PCI device.
MII Interface
LTXC, I 53,31 Y20 TXC is a continuous clock that provides a timing reference for the transfer of
WTXC W11 TXD[3:0], TXE. In MII mode, it uses the 25 MHz or 2.5 MHz supplied by the
external PMD device.
LTXEN, O 59,37 T17 Indicates the presence of valid nibble data on TXD[3:0].
WTXEN
LTXD[3-0] O 57,56,55,54 V18,V17,W Four parallel transmit data lines which are driven synchronous t o the TXC for
, WTXD 35,34,33,32 19,W18 transmission by the external physical layer chip.
[3-0] V12,Y13,W
12,Y12
LRXC, I 51,29 W17,V11 This is a continuous clock that is recovered from the incoming data. MRXC is
WRXC 25MHz in 100Mbps and 2.5Mhz in 10Mbs.
LCOL, I 60,38 U18,V13 This signal is asserted high synchronously by the external physical unit upon
WCOL detection of a collision on the medium. It will remain asserted as long as the
collision condition persists.
LRXDV, I 43,44 W16,W9 Data valid is asserted by an external PHY when receive data is present on the
WRXDV RXD[3:0] lines, and it is deasserted at the end of the packet. This signal is valid
on the rising of the RXC.
LRXD[3-0 I 50,49,47,46 V15,V16,Y This is a group of 4 data signals aligned on nibble boundaries which are driven
], 27,26,24,23 18,Y17,Y11 synchronous to the RXC by the external physical unit
WRXD[3- ,W10,V10,
0] Y10
LRXER, I 44,22 V14,V9 This pin is asserted to indicate that invalid symbol has been detected in 100Mbps
WRXER MII mode. This signal is synchronized to RXC and can be asserted for a
minimum of one receive clock.
LMDC, O 40,18 W15,W8 Management Data Clock: This pin provides a clock synchronous to MDIO,
WMDC which may be asynchronous to the transmit TXC and receive RXC clocks.
LMDIO, I/O 41,19 Y16,Y9 Management Data Input/Output: This pin provides the bi-directional signal used
WMDIO to transfer management information.
GPIO
GPIOB[11- I/O 205,206,207, U1,U2,U3, General purpose I/O pins group B pins 11 to 0. If ICFG[5-4] power on latch
0] 2,3,5,6,8,9,1 W1,Y1,Y2, =[1-0]. GPIO[5-2] mapping to JTAG_TDO(JTAG test data
1,12,13 W4,V5,Y4, output),JTAG_TRSTN(JTAG reset),JTAG_TMS(JTAG test mode
W5,V6,Y5 select),JTAG_TDI(JTAG test data input).
GPIOB[15 I/O 200,201,202, R1,T1,T2,T General purpose I/O pins group B pin 15 to 12.
-12] 203 3
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*A=Analog signal
*X=Not used .
3. Address Mapping
The RTL8181 supports up to 4 gigabytes of address space. The memory map of RTL8181 is managed by MMU, which will
translate the virtual address to physical address. The memory is segmented into four regions by its access mode and caching
capability as shown in following table.
Segment Size Caching Virtual address range Physical address range Mode
KUSEG 2048M cacheable 0x0000_0000-0x7fff_ffff set in TLB user/kernel
KSEG0 512M cacheable 0x8000_0000-0x9fff_ffff 0x0000_0000-0x1fff_ffff kernel
KSEG1 512M uncachable 0xa000_0000-0xbfff_ffff 0x0000_0000-0x1fff_ffff kernel
KSEG2 512M cacheable 0xc000_0000-0xfeff_ffff set in TLB kernel
KSEG2 512M cacheable 0xff00_0000-0xffff_ffff 0xff00_0000-0xffff_ffff kernel
The RTL8181 has two memory mapping modes: direct memory mapping and TLB (Translation Look-aside Buffer) address
mapping. When virtual address is located in the regions KSEG0, KSEG1 or higher half of KSEG2 segments, it physical
address will be mapped directly from virtual address with an offset. If virtual address used is in the regions of KUSEG or
lower half of KSEG2 segment, its physical address will be referred from TLB entry. RTL8181 contains 16 TLB entries, each
of which maps to a page, with read/write access, cache-ability and process id.
In RTL8181, SDRAM is mapped from physical address 0x0000_0000 to maximum 0x01ff_ffff (32M bytes). After reset,
RTL8181 will start to fetch instructions from physical address 0x1fc0_0000, the starting address of flash memory. The flash
memory is mapped from physical address 0x1fc0_0000 to maximum 0x1fff_ffff (4M bytes).
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Memory map (without TLB):
Virtual Address
Physical Address
0x8000_0000
Cacheable
region
0x0000_0000
SDRAM
0x81ff_ffff
(32Mbyte)
0xa000_0000
None
cacheable 0x01ff_ffff
region
0xa1f f_ffff
0xbfc0_0000 0x1fc0_0000
None
cacheable Flash
region (4Mbyte)
0xbfff_ffff 0x1fff_ffff
The memory map of RTL8181 I/O devices and registers are located in KSEG1 segment (uncacheable region). The following
table illustrates the address map:
Virtual address range Size (bytes) Mapped device
0xBD01_0000