Text preview for : System_90_Hardware_Description_Sep88.pdf part of arete_arix System 90 Hardware Description Sep88 . Rare and Ancient Equipment arete_arix s90 System_90_Hardware_Description_Sep88.pdf
Back to : System_90_Hardware_Descri | Home
- 1-
Arix Corporation
System90 Hardware Description
19 September 1988
II 8
C~5
Arix Corporation - CON"IDENTIAL
- 1-
1. Arix System90 Hardware Description
1.1 General
This document is intended as a technical overview of the Arix System90. It identifies the
major hardware components of the system and describes their function. Additional
documents detail the function and operation of the major system components.
1.2 System90 Overview
The Arix System90 is a high performance general purpose computer system. The system is
intended to enhance Arix's position as a vendor of high performance on-line multi-
processor UNIX systems.
The system logic is composed of a computational subsystem and an 110 subsystem. The
computational subsystem is newly designed specifically for the System90 while the 110
subsystem is largely retained from the AlOOO family.
The system is packaged in a series of 22" wide modular cabinets. The primary cabinet
contains the computational subsystem. Additional cabinets contain either 110 subsystems
or peripherals.
Arix Corporation - CONFIDENTIAL
-2-
1.3 Related Documents
The following related documents detail the hardware operation of various major system
components.
S90 System Busses - Functional Description
S90 Service Processor Module - Functional Description
S9068020 Processor Module - Functional Description
S90 Memory Module - Functional Description
S90 110 Module - Functional Description
S90 AlOOO 110 Adaptor - Functional Description
Arix Corporation ~ CONFIDENTIAL
-3-
2. Computational Suh!llystem
The System90 Computational Subsystem (CSS) consists of a cluster of tightly coupled
processors and memory modules on a high speed system bus. Also in the CSS are 110
modules which adapt the main system bus to 110 buses.
The major components of the CSS are the Processor Modules, Memory Modules, 110
Modules, Service Processor Module, CSS Arbiter, and CSS backplane.
2.1 CSS Bus
The CSS bus is the backbone of the System90. It is a 64 bit wide, high speed synchronous
data transfer bus. It is designed to accommodate up to 16 modules; either Processor
Modules, Memory Modules, or 110 Modules.
TIle CSS bus is implemented as an N-port time division multiplexed transmission switch.
The bus supports read and write operations between all attached modules. Read operations
transfer 64 bits and write operations transfer up to 32 bits. The bus supports concurrent
operations to and from the modules on the bus. This allows overlapping cycles on
individual modules and provides enough bus bandwidth to minimize contention for this
system resource. This allows the support of multiple high performance processors with near
linear incremental performance as each processor is added. The bus is used only for issuing
a command for an operation to occur and for returning a response to that command.
The CSS bus is a synchronous bus that is designed to clock at 20 MHz creating a
fundamental time division of 50 nS.TItis allows 20 million bus operations per second.
A write operation uses a single bus cycle allowing write throughput of 80 Mbytes per
second. The bus supports single and burst transfer deferred read responses. Thirty-two
byte burst read operations use a single bus cycle to initiate a read operation and four cycles
to return the read response. This allows a 128 Mbyte per second read transfer rate.
The CSS bus supports end-ta-end transmission checking on each bus operation.
Transmission checks are performed by the each .destination module to detect errors on
address, data, and control fields.
2.2 CSS Bus Arbiter
The CSS Bus Arbiter is a module that provides the control for the CSS bus. It is
responsible for the arbitration of the CSS bus as well as system clock generation. The CBA
collects requests for use of the bus from all elements and grants use on each bus clock tick.
The CSS Bus Arbiter is implemented as a separate printed circuit card that attaches to the
CSS motherboard.
Arix Corporation - CONFIDENTIAL
-4-
2.3 ess Backplane
The system backplane is the system bus motherboard that distributes bus signals between
modules of the CSS and A1000 I/O controllers. It also provides DC power distribution to
the cards.
There are two types of system backplanes. The first accommodates 16 CSS modules;
either Processor Modules, Memory Modules, or I/O Modules and a Service Processor
Module. The second is a hybrid accommodating 8 CSS modules; either Processor Modules,
Memory Modules, or I/O Modules and a Service Processor Module ; and also
accommodating 11 Al000 I/O controllers.
2.4 68020 Processor Module
The Processor Module (PM) is the main computational element within the CSS. It is
based on a 25 MHz Motorola 68020 32 bit microprocessor and 12.5 through 25 MHz
68881 noating point unit (FPU).
The PM includes a proprietary memory management unit (MMU) which is well suited for
demand paged virtual memory implementation in a multiple processor environment. The
MMU is optimized for rapid context switching in a multi-processor environment by sharing
system memory resident page maps and caching entries in a 1024 entry TLB. 11le MMU
support access permission enforcement and paging statistics on each page.
The PM also includes a 64KB on-board virtual cache memory. It is organized as a single
direct mapped set organized as 4096 sixteen byte lines. 111is cache provides no-wait-state
performance. A 98% read hit ratio is anticipated.
2.5 Memory Module
The Memory Module (MM) is the main system storage element of the CSS. It provides
from 8 to 32 MB of storage by populating one, two, or four banks.
The MM supports single or burst mode 64 bit reads. Burst sizes are 16 and 32 bytes. It
also supports 8. 16. 24. and 32 bit writes.
The board provides high throughput by allowing two way interleaving between banks. Also
page interleaving across multiple memory modules. to further enhance throughput. is
supported.
The MM is designed with 1 Mbit dynamic RAM but will also accommodate 4 Mbit
devices as they become readily available. It uses VLSI error detection and correction using
a modified 7 bit hamming code which corrects all single bits errors and detects all double
bit and many multiple bit errors.
Arix Corporation - J~()NFIDENTIAL