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DP1 (Pebble) Power Sequence
Insert AC adapter only,
then without press power
button
Power Plan:
PS_ID 0. RTC power plane.
1. Always power plane.
2. SUS power plane.
3. RUN power plane.
PS_ID is to confirm that insertion of ACPI Power State:
AC adapter 65W or 90W 1. S0: System Full On, All power planes are ON.
2. S3: Suspend to RAM, RUN power off.
3. S4: Suspend to Disk, RTC and Always power
ON.(AC)
4. S5: Soft Off, power state like S4.
PWR_SRC
+RTCSRC is generated by
PWR_SRC
through D40
+RTCSRC
Pin 1 Pin 1
U9 U13
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+RTCSRC will be input of MAXIM 1615,
then +RTC_PWR is the output of
MAXIM 1615
+RTCSRC will be input of MAXIM 1615,
then +3.3VRTC is the output of MAXIM
1615
Pin 3 Pin 3
+3.3VRTC
+RTC_PWR
If no ALW power, what
With either LIVE_ON_BATT or should we do?
A: Check all ACAV_IN
With either LIVE_ON_BATT or
ACAV_IN existed, +RTC_PWR can relate circuit. ACAV_IN existed, +3.3VRTC can
convert to +5VALW through Q61 convert to +3VALW through Q62
+3VALW
+5VALW X7 XTAL 32.768K will
oscillate after
+3.3VRTC comes up Macallen
high & U37.2 should 32 K Hz
driven high after
Go!
+3VALW comes up.
If Macallen is working.
CN8 pin2 will have 1,2,3,4
Q: If no debug out pulse?
1. Macallen.
pulse when AC adapter
2. BIOS ROM. attached( DEBUG_OUT )
DP1 (Pebble) Power Sequence
Insert AC adapter only, then
press power
button
POWER_SW#
After +3VALW , +5VALW, If Macallen do not driven SUS_ON high
1. Re-heat Macallen.
DEBUG_OUT were all come out. 2. Change one new Macallen.
Macallen should assert SUS_ON. 3. Still no SUS_ON, check BIOS ROM.
SUS_ON Digitally signed by
fdsf
DN: cn=fdsf,
o=fsdfsd, ou=ffsdf,
email=fdfsd@fsdff,
SUS_ON and AUX_EN were initial c=US
AUX_EN from trigger for MAX1632. It will result in Date: 2010.02.15
08:10:10 +07'00'
Macallen producing +5VSUS , +3VSRC and
DC_12V
DC_12CV.
+3VSRC Q60
+5VSUS
With
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Q17 RUNPWROK
+5VSUS was initial asserts
+12V
trigger for SC1486. It
will produce
+3VSUS
+2.5VSUS
+3VSUS was initial
trigger for MAX1644. It
will produce +1.5VSUS.
+2.5VSUS
+1.5VSUS
2.5V_PWRGD
1632_3VOK
SUS_ON
Check All SUS power planes
are in correct voltage level?
If these three signal
driven high, then through
U74 ( AND gate ) will
produce SUSPWROK
SUSPWROK
DP1 (Pebble) Power Sequence
If SUSPWROK is OK, it will
drive to ICH4
SUSPWROK
When initialized ICH4, drives
SLP_S3# which causes Macallen to
drive RUN_ON.
RUN_ON
After approximate 10ms soft
start delay, RUN power
switches are turned on and
connecting RUN planes with
SUS planes
SUS POWER PLANES RUN POWER PLANES
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+5VSUS +3VSUS
+5VSUS
+5VSUS was initial
+3VSRC
+3VSUS was initial
trigger for
+1.5VSUS
trigger for MAX1792.It
TPS793475.It will
will produce +1.8VRUN
produce +5VA
+5VRUN
+5VA +1.8VRUN Q55
Q18
4.75V for audio circuit.
+5VRUN
Q69
+5VRUN was initial
trigger for SC1486.It
+3VRUN
will produce
Make sure all RUN power +1.25VRUN
+1.5VRUN
planes are in correct voltage
level.
Delay 10ms
+1.25VRUN
1.25V_PWRGD
If these three signal
assert, then through
U20 ( AND gate ) will
produce RUNPWROK
RUNPWROK
DP1 (Pebble) Power Sequence
10ms after +5VRUN power
plane comes up
RUNPWROK
RUNPWROK was initial trigger RUNPWROK was initial trigger
for MAX1715. It will produce for SC1476. It will produce
+1.2VRUN and VCC_IO VCC_CORE
VCC_CORE
+1.2VRUN
VCC_IO
If no Vcore:
1. Check high/low side MOSFET.
When Macallen is ready to 2. Check U67 SC1476
release the Banias, it will
drive RESET_OUT#
After +1.2VRUN and After VCC_CORE came
RESET_OUT#
VCC_IO came out. out. SC1476 will
MAX1715 will produce produce
1715PWROK VCORE_PWRGD
1715PWROK VCORE_PWRGD
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10ms after VCC_CORE
and VCC_IO are within
regulation.
VCORE_PWRGD is driven
to ICH4 ( VGATE )
VCORE_PWRGD_D
VGATE
If CPU power is OK and CPURST# de-assertion.
Delay 10ms 1. CPU: re-heat, change one new.
2. Change BIOS ROM.
CK408_IMVP_PWRGD
( TO CLOCK GEN )
All clocks
DELAY_IMVP_PWRGD
DELAY_IMVP_PWRGD is driven
to ICH4 as PWROK allowing Next step should check:
release of the Banias from INIT 1. PCIRST#
and deassertion of PCIRST# 2. CPURST#
3. GTL_ADS#