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November 1998




FDG6321C
Dual N & P Channel Digital FET
General Description Features

These dual N & P-Channel logic level enhancement mode field N-Ch 0.50 A, 25 V, RDS(ON) = 0.45 @ VGS= 4.5V.
effect transistors are produced using Fairchild's proprietary, RDS(ON) = 0.60 @ VGS= 2.7 V.
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance. P-Ch -0.41 A, -25 V,RDS(ON) = 1.1 @ VGS= -4.5V.
This device has been designed especially for low voltage RDS(ON) = 1.5 @ VGS= -2.7V.
applications as a replacement for bipolar digital transistors and
small signal MOSFETS. Since bias resistors are not required, Very small package outline SC70-6.
this dual digital FET can replace several different digital
transistors, with different bias resistor values. Very low level gate drive requirements allowing direct
operation in 3 V circuits(VGS(th) < 1.5 V).
Gate-Source Zener for ESD ruggedness
(>6kV Human Body Model).




SC70-6 SOT-23 SuperSOTTM-6 SOT-8 SO-8 SOIC-14




S2 1 6
G2
D1 .21
2 5
D2
G1
S1 3 4
SC70-6




Absolute Maximum Ratings TA = 25oC unless otherwise noted
Symbol Parameter N-Channel P-Channel Units
VDSS Drain-Source Voltage 25 -25 V
VGSS Gate-Source Voltage 8 -8 V
ID Drain Current - Continuous 0.5 -0.41 A
- Pulsed 1.5 -1.2
PD Maximum Power Dissipation (Note 1) 0.3 W
TJ,TSTG Operating and Storage Temperature Ranger -55 to 150