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SN54/74LS75
4-BIT D LATCH SN54/74LS77
The TTL/MSI SN54 / 74LS75 and SN54 / 74LS77 are latches used as tem-
porary storage for binary information between processing units and input /out-
put or indicator units. Information present at a data (D) input is transferred to
the Q output when the Enable is HIGH and the Q output will follow the data
input as long as the Enable remains HIGH. When the Enable goes LOW, the
information (that was present at the data input at the time the transition oc-
curred) is retained at the Q output until the Enable is permitted to go HIGH. 4-BIT D LATCH
The SN54 / 74LS75 features complementary Q and Q output from a 4-bit
LOW POWER SCHOTTKY
latch and is available in the 16-pin packages. For higher component density
applications the SN54 / 74LS77 4-bit latch is available in the 14-pin package
with Q outputs omitted.
CONNECTION DIAGRAMS DIP (TOP VIEW)
Q0 Q1 Q1 E0