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Copyright AU Optronics, Inc.
January, 2003 All Rights Reserved. T315HW02 V3 - Spec. Ver 0.1
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Document Version : 0.1
Date : 2008/12/08
Product Specifications
31.5" FHD Color TFT-LCD Module
Model Name: T315HW02 V3
() Preliminary Specifications
(*) Final Specifications
Copyright AU Optronics, Inc.
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Contents
No
COVER
CONTENTS
RECORD OF REVISIONS
1 GENERAL DESCRIPTION
2 ABSOLUTE MAXIMUM RATINGS
3 ELECTRICAL SPECIFICATIONS
3-1 ELECTRICAL CHARACTREISTICS
3-2 INTERFACE CONNECTIONS
3-3 SIGNAL TIMING SPECIFICATIONS
3-4 SIGNAL TIMING WAVEFORMS
3-5 COLOR INPUT DATA REFERNECE
3-6 POWER SEQUENCE
4 OPTICAL SPECIFICATIONS
5 MECHANICAL CHARACTERISTICS
6 RELIABLITY
7 INTERNATIONAL STANDARDS
8 PACKING
9 PRECAUTIONS
Copyright AU Optronics, Inc.
January, 2003 All Rights Reserved. T315HW02 V3 - Spec. Ver 0.1
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Record of Revision
Version Date No Old Description New Description Remark
0.0 2008/10/11 First issue
0.1 2008/11/27 6 Drop test condition: 46mm Drop test condition: 38mm
Final spec
Copyright AU Optronics, Inc.
January, 2003 All Rights Reserved. T315HW02 V3 - Spec. Ver 0.1
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1. General Description
This specification applies to the 31.5 inch Color TFT-LCD Module T315HW02 V3. This LCD
module has a TFT active matrix type liquid crystal panel 1920x1080 pixels, and diagonal size of
31.5 inch. This module supports 1920x1080 HDTV mode (Non-interlace).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical
stripes. Gray scale or the brightness of the sub-pixel color is determined with a 10-bit gray scale
signal for each dot.
The T315HW02 V3 has been designed to apply the 10-bit 2 channel LVDS interface method. It is
intended to support displays where high brightness, wide viewing angle, high color saturation, and
high color depth are very important.
The T315HW02 V3 model is RoHS verified which can be distinguished on panel label.
* General Information
Items Specification Unit Note
Active Screen Size 31.51 inches
Display Area 698.4 (H) x 392.85 (V) mm
Outline Dimension 760.0(H) x 450.0(V) x 45(D) mm w/o Inverter
Driver Element a-Si TFT active matrix
Display Colors 16.7M Colors
Number of Pixels 1920x1080 Pixel
Pixel Pitch 0.36375 mm
Pixel Arrangement RGB vertical stripe
Display Mode Normally Black
Surface Treatment SC, 3H
Copyright AU Optronics, Inc.
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2. Absolute Maximum Ratings
The following are maximum values which, if exceeded, may cause permanent damage to the unit.
Item Symbol Min Max Unit Conditions
Logic/LCD Drive Voltage Vcc -0.3 14 [Volt] Note 1
Input Voltage of Signal Vin -0.3 4 [Volt] Note 1
o
Operating Temperature TOP 0 +50 [ C] Note 2
Operating Humidity HOP 10 90 [%RH] Note 2
Storage Temperature TST -20 +60 [oC] Note 2
Storage Humidity HST 10 90 [%RH] Note 2
o
Panel Surface Temperature PST 65 [ C] Note 3
Note 1: Duration:50 msec.
Note 2 : Maximum Wet-Bulb should be 39 and No condensation.
The relative humidity must not exceed 90% non-condensing at temperatures of 40 or less. At temperatures greater
than 40 , the wet bulb temperature must not exceed 39 .
Note 3: Surface temperature is measured at 50 Dry condition
Copyright AU Optronics, Inc.
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3. Electrical Specification
The T315HW02 V3 requires two power inputs. One is employed to power the LCD electronics and to drive the TFT
array and liquid crystal. The second input, which powers the CCFL, is typically generated by an integrated power (I/P)
system.
3-1 Electrical Characteristics
Parameter Values
Unit Notes
Min Typ Max
CD:
Power Supply Input Voltage Vcc 10.8 12 13.2 Vdc 1
Power Supply Input Current Icc - 1.2 A 2
Power Consumption Pc - 14.4 Watt 2
Inrush Current IRUSH - - 4.5 Apeak 3
Differential Input High Threshold
VTH 100 mV 4
Voltage
LVDS
Differential Input Low Threshold
Interface VTL 100 mV 4
Voltage
Common Input Voltage VCIM 1.10 1.25 1.40 V 4
VIH
Input High Threshold Voltage 2.4 3.3 Vdc
CMOS (High)
Interface VIL
Input Low Threshold Voltage 0 0.7 Vdc
(Low)
Life Time 50,000 Hours 6
Note :
1. The ripple voltage should be controlled under 10% of VCC
2. Vcc=12.0V, f v = 60Hz, fCLK=74.25 Mhz , 25 , Test Pattern : White Pattern
3. Measurement condition :
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4. VCIM = 1.2V
5. The performance of the Lamp in LCD panel, for example life time or brightness, is extremely influenced by the
characteristics of balanced board and I/P board. All the parameters should be carefully designed as not to
produce too much leakage current from high-voltage output. While you design or order the balance board,
please make sure unwanted lighting caused by the mismatch of the lamp and the balanced board (no lighting,
flicker, etc) never occurs. After confirmation, the LCD panel should be operated in the same condition as
installed in your instrument.
6. Do not attach a conducting tape to lamp connecting wire. If the lamp wire attach to conducting tape, TFT-LCD
Module have a low luminance and the inverter has abnormal action because leakage current occurs between
lamp wire and conducting tape.
7. The relative humidity must not exceed 80% non-condensing at temperatures of 40 or less. At temperatures
greater than 40
, the wet bulb temperature must not exceed 39 . When operate at low temperatures, the
brightness of CCFL will drop and the life time of CCFL will be reduced.
Copyright AU Optronics, Inc.
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3-2 Interface Connections
- Connector on Panel: JAE FI-RE51S-HF (Manufactured by JAE)
-
PIN No Signal Name Description
1 VDD Operating Voltage Supply, +12V DC Regulated
2 VDD Operating Voltage Supply, +12V DC Regulated
3 VDD Operating Voltage Supply, +12V DC Regulated
4 VDD Operating Voltage Supply, +12V DC Regulated
5 VDD Operating Voltage Supply, +12V DC Regulated
6 GND Ground
7 GND Ground
8 GND Ground
9 GND Ground
10 ORX_0- LVDS Channel Odd, Signal 0-
11 ORX _0+ LVDS Channel Odd, Signal 0+
12 ORX _1- LVDS Channel Odd, Signal 1-
13 ORX _1+ LVDS Channel Odd, Signal 1+
14 ORX _2- LVDS Channel Odd, Signal 2-
15 ORX _2+ LVDS Channel Odd, Signal 2+
16 GND Ground
17 ORX _CLK- LVDS Channel Odd, Clock -
18 ORX _CLK+ LVDS Channel Odd, Clock +
19 GND Ground
20 ORX _3- LVDS Channel Odd, Signal 3-
21 ORX _3+ LVDS Channel Odd, Signal 3+
22 ORX _4- LVDS Channel Odd, Signal 4-
23 ORX _4+ LVDS Channel Odd, Signal 4+
24 GND Ground
25 ERX_0- LVDS Channel Even, Signal 0-
26 ERX_0+ LVDS Channel Even, Signal 0+
27 ERX_1- LVDS Channel Even, Signal 1-
28 ERX_1+ LVDS Channel Even, Signal 1+
29 ERX_2- LVDS Channel Even, Signal 2-
30 ERX_2+ LVDS Channel Even, Signal 2+
31 GND Ground
32 ERX_CLK- LVDS Channel Even, Clock -
33 ERX_CLK+ LVDS Channel Even, Clock +
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34 GND Ground
35 ERX_3- LVDS Channel Even, Signal 3-
36 ERX_3+ LVDS Channel Even, Signal 3+
37 ERX_4- LVDS Channel Even, Signal 4-
38 ERX_4+ LVDS Channel Even, Signal 4+
39 GND Ground
40 NC No Connection
41 NC No Connection
42 NC No Connection
43 NC No Connection
44 HSYNC Customer use only
45 LVDS_SEL Open/High(3.3V) for NS, Low(GND) for JEIDA
46 LVDS_SCL I2C SCL data from LVDS
47 FRC_NRESET Customer use only
48 LVDS_SDA I2C SDA data from LVDS
49 SW_PVCC Customer use only
50 MAIN_CHECK Customer use only
51 NC (reserved) No Connection (AUO internal use)
Note:
1. All GND (ground) pins should be connected together and should also be connected to the LCD's metal frame.
All Vcc (power input) pins should be connected together.
2. For Pin 10, 27 and 28, panel will not damage if negligently connect these pins to high or low
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LVDS_SEL = High/Open, NS mode
ORXCLK+
ORXCLK-
ORX0 OR0 OG0 OR5 OR4 OR3 OR2 OR1 OR0 OG0
ORX1 OG1 OB1 OB0 OG5 OG4 OG3 OG2 OG1 OB1
ORX2 OB2 DE VS HS OB5 OB4 OB3 OB2
ORX3 OR6 OB7 OB6 OG7 OG6 OR7 OR6
ERXCLK+
ERXCLK-
ERX0 ER0 EG0 ER5 ER4 ER3 ER2 ER1 ER0 EG0
ERX1 EG1 EB1 EB0 EG5 EG4 EG3 EG2 EG1 EB1
ERX2 EB2 DE VS HS EB5 EB4 EB3 EB2 DE
ERX3 ER6 EB7 EB6 EG7 EG6 ER7 ER6
Note:
Odd data is the first priority.
First data is odd.
LVDS_SEL = Low (0V) , JEIDA mode
ORXCLK+
ORXCLK-
ORX0 OR2 OG2 OR7 OR6 OR5 OR4 OR3 OR2 OG2
ORX1 OG3 OB3 OB2 OG7 OG6 OG5 OG4 OG3 OB3
ORX2 OB4 DE VS HS OB7 OB6 OB5 OB4
ORX3 OR0 OB1 OB0 OG1 OG0 OR1 OR0
ERXCLK+
ERXCLK-
ERX0 ER2 EG2 ER7 ER6 ER5 ER4 ER3 ER2 EG2
ERX1 EG3 EB3 EB2 EG7 EG6 EG5 EG4 EG3 EB2
ERX2 EB4 DE VS HS EB7 EB6 EB5 EB4 DE
ERX3 ER0 EB1 EB0 EG1 EG0 ER1 ER0
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3-3 Signal Timing Specifications
This is the signal timing required at the input of the User connector. All of the interface signal timing should be satisfied
with the following specifications for it's proper operation.
* Timing Table
DE only Mode
Vertical Frequency:
Signal Item Symbol Min. Typ. Max Unit
Period TV 1125 TH
Active TDISP (V) 1080 TH
Blanking TBLK (V) 45 TH
Vertical Section
Front porch Tfp(V) 5 5 5 TH
Back porch Tbp(V) 31 31 31 TH
V_sync TVsync_wdth 9 9 9 TH
Period TH 2200 2200 2200 TCLK
Active TDISP (H) 1920 TCLK
Blanking TBLK (H) 144 TCLK
Horizontal Section
Front porch Tfp(H) 49 49 49 TCLK
Back porch T(H) 147 147 147 TCLK
V_sync TVsync_wdth 84 84 84 TCLK
Period TCLK 13.47 ns
Clock
Frequency FCLK 74.25 MHz
Vertical Frequency Frequency FV 60 Hz
Horizontal Frequency Frequency FH 67.5 KHz
Notes:
1.) Di splay position is specific by the rise of DE signal only.
Horizontal display position is specified by the falling edge of 1st DCLK right after the rise of ENAB, is displayed on the
left edge of the screen.
Vertical display position is specified by the rise of DE after a "Low" level period equivalent to eight times of horizontal
period. The 1st data corresponding to one horizontal line after the rise the of ENAB is displayed at the top line of screen.
2.) The display position does not fit to the screen if a period of DE "High" and the effective data period do not
synchronize with each other.
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3-4 Signal Timing Waveforms
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3-5 Color Input Data Reference
The brightness of each primary color (red, green and blue) is based on the 10 bit gray scale data input for the color; the
higher the binary input, the brighter the color. The table below provides a reference for color versus data input.
COLOR DATA REFERENCE
Input Color Data
RED GREEN BLUE
Color
MSB LSB MSB LSB MSB LSB
R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red(1023) 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Green(1023) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
Basic
Blue(1023) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
Color
Cyan 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Magenta 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
Yellow 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
White 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
RED(000) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RED(001) 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RED ----
RED(1022) 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RED(1023) 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GREEN(000) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GREEN(001) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
GREEN ----
GREEN(1022) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
GREEN(1023) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
BLUE(000) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BLUE(001) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
BLUE -------
BLUE(1022) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0
BLUE(1023) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
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3-6 Power Sequence for LCD Module
3.6.1 Power Sequence for LCD
Parameter Values Units
Min. Typ. Max.
t1 0.4 --- 30 ms
t2 0.1 --- 50 ms
t3 300 --- --- ms
t4 10 --- --- ms
t5 0.1 --- 50 ms
t6 --- --- 300 ms
t7 500 --- --- s
Note:
The timing controller will not be damaged in case of TV set AC input power suddenly shut down.
Once power reset, it should follow power sequence as spec. definition.
(1) Apply the lamp voltage within the LCD operation range. When the back-light turns on before the LCD operation or
the LCD turns off before the back-light turns off, the display may momentarily become abnormal screen.
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3-7 Backlight Power Specification for LCD Module
3.7.1 Electrical specification
Description Min Typ Max Unit Condition/Note
1. Dimming range is set 100%
2. Base on lamp specification, for each
1 Operating Voltage Vo 1242 1380 1518 Vrms lamp need to be applied at least
minimum operating voltage to ensure
each lamp can be normally worked!
1. Dimming range is set 100%
2. Base on lamp specification, for each
2 Operating Current Io 12 12.5 13 mArms lamp need to be applied at least
minimum operating current to ensure
each lamp can be normally worked!
1. Dimming range is set 100%.
2. In order to get typical light out, the
backlight need to be applied typical
3 BL Total Power Dissipation PBL 73 78 83 Watt power.
3. Input power of JIG BD is about 90 W
(typ) by AUO measure!
At 0 2750 2900 - 1. Base on lamp specification, to ensure
each lamp can be normally ignited,
4 Striking Voltage Vstrike Vrms need to apply at least minimum
At 52 2290 2440 - striking voltage to each lamp
1. To ensure each lamp can be normally
ignited, each lamp need to be applied
5 Striking Time Ts 1000 - 1500 msec at least minimum striking voltage
during minimum striking time.
6 Lamp Type Straight type
7 Number of Lamps 4U pcs
Ta=25 5