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CAT28C512/513
512K-Bit CMOS PARALLEL EEPROM FEATURES
s Fast Read Access Times: 120/150 ns s Low Power CMOS Dissipation: s Automatic Page Write Operation:
Active: 50 mA Max. Standby: 200 µA Max.
s Simple Write Operation:
1 to 128 Bytes in 5ms Page Load Timer
s End of Write Detection:
On-Chip Address and Data Latches Self-Timed Write Cycle with Auto-Clear
s Fast Write Cycle Time:
Toggle Bit DATA Polling DATA
s Hardware and Software Write Protection s 100,000 Program/Erase Cycles s 100 Year Data Retention s Commercial, Industrial and Automotive
5ms Max
s CMOS and TTL Compatible I/O
Temperature Ranges
DESCRIPTION
The CAT28C512/513 is a fast,low power, 5V-only CMOS parallel EEPROM organized as 64K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bits signal the start and end of the self-timed write cycle. Additionally, the CAT28C512/513 features hardware and software write protection. The CAT28C512/513 is manufactured using Catalyst's advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC approved 32-pin DIP, PLCC, 32-pin TSOP and 40-pin TSOP packages.
BLOCK DIAGRAM
ADDR. BUFFER & LATCHES INADVERTENT WRITE PROTECTION ROW DECODER 65,536 x 8 E2PROM ARRAY 128 BYTE PAGE REGISTER
A7A15
VCC
HIGH VOLTAGE GENERATOR
CE OE WE
CONTROL I/O BUFFERS TIMER DATA POLLING AND TOGGLE BIT COLUMN DECODER
I/O0I/O7
A0A6
ADDR. BUFFER & LATCHES
5096 FHD F02
© 2001 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. 1007, Rev. C
CAT28C512/513
PIN CONFIGURATION
DIP Package (P)
NC NC A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE NC A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
PLCC Package (N)
NC VCC WE A12 A15 NC NC
PLCC Package (N)
A14 A15 VCC WE A7 A12 A13
A7 A6 A5 A4 A3 A2 A1 A0 I/O0
4 3 2 1 32 31 30 5 29 6 28 7 27 8 26 CAT28C512 9 25 TOP VIEW 10 24 11 23 12 22 13 21 14 15 16 17 18 19 20
4 3 2 1 32 31 30
A14 A13 A8 A9 A11 OE A10 CE I/O7
A6 A5 A4 A3 A2 A1 A0 NC I/O0
5 6 7 8 9 10 11 CAT28C513 TOP VIEW
29 28 27 26 25 24 23
A8 A9 A11 NC OE A10 CE I/O7 I/O6
12 22 13 21 14 15 16 17 18 19 20
I/O1 I/O2 VSS NC I/O3 I/O4 I/O5
I/O1 I/O2 VSS I/O3 I/O4 I/O5
I/O6
5096 FHD F01
TSOP Package (8mmx20mm) (T)
A11 A9 A8 A13 A14 NC WE VCC NC NC A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CAT28C512
TOP VIEW
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 Vss I/O2 I/O1 I/O0 A0 A1 A2 A3
PIN FUNCTIONS Pin Name A0A15 I/O0I/O7 CE OE Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Pin Name WE VCC VSS NC Function Write Enable 5V Supply Ground No Connect
Doc. No. 1007, Rev. C
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CAT28C512/513
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. 55°C to +125°C Storage Temperature ....................... 65°C to +150°C Voltage on Any Pin with Respect to Ground(2) ........... 2.0V to +VCC + 2.0V VCC with Respect to Ground ............... 2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(3) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND(1) TDR(1) VZAP(1) ILTH(1)(4) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Min 100,000 100 2000 100 Max.
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Units Cycles/Byte Years Volts mA
Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS VCC = 5V ±10%, unless otherwise specified. Limits Symbol ICC ICCC(5) ISB ISBC(6) ILI ILO VIH(6) VIL(5) VOH VOL VWI Parameter VCC Current (Operating, TTL) VCC Current (Operating, CMOS) VCC Current (Standby, TTL) VCC Current (Standby, CMOS) Input Leakage Current Output Leakage Current High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Write Inhibit Voltage 3.5 -10 -10 2 -1 2.4 0.4 Min Typ Max. 50 25 3 200 10 10 VCC +0.3 0.8 Units mA mA mA µA µA µA V V V V V IOH = 400µA IOL = 2.1mA Test Conditions CE = OE = VIL, f=6MHz All I/O's Open CE = OE = VILC, f=6MHz All I/O's Open CE = VIH, All I/O's Open CE = VIHC, All I/O's Open VIN = GND to VCC VOUT = GND to VCC, CE = VIH
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100mA on address and data pins from 1V to VCC +1V. (5) VILC = 0.3V to +0.3V. (6) VIHC = VCC 0.3V to VCC +0.3V.
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Doc. No. 1007, Rev . C
CAT28C512/513
MODE SELECTION Mode Read Byte Write (WE Controlled) Byte Write (CE Controlled) Standby, and Write Inhibit Read and Write Inhibit H X CE L L L X H WE H OE L H H X H I/O DOUT DIN DIN High-Z High-Z Power ACTIVE ACTIVE ACTIVE STANDBY ACTIVE
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol CI/O(1) CIN(1) Test Input/Output Capacitance Input Capacitance Max. 10 6 Units pF pF Conditions VI/O = 0V VIN = 0V
A.C. CHARACTERISTICS, Read Cycle VCC=5V + 10%, Unless otherwise specified 28C512/513-12 28C512/513-15 Symbol tRC tCE tAA tOE tLZ(1) tOLZ(1) tHZ(1)(2) tOHZ(1)(2) tOH(1) Parameter Read Cycle Time CE Access Time Address Access Time OE Access Time CE Low to Active Output OE Low to Active Output CE High to High-Z Output OE High to High-Z Output Output Hold from Address Change 0 0 0 50 50 0 Min. 120 120 120 50 0 0 50 50 Max. Min. 150 150 150 70 Max. Units ns ns ns ns ns ns ns ns ns
Power-Up Timing Symbol tPUR (1) tPUW (2) Parameter Power-up to Read Operation Power-up to Write Operation 5 Min. Max 100 10 Units µs ms
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
Doc. No. 1007, Rev. C
4
CAT28C512/513
A.C. CHARACTERISTICS, Write Cycle VCC=5V+10%, unless otherwise specified 28C512/513-12 28C512/513-15 Min. Max. Min. Max. Units 5 0 50 0 0 100 0 0 100 50 0 5 0.1 10 100 0 50 0 0 100 0 0 100 50 0 5 0.1 10 100 5 ms ns ns ns ns ns ns ns ns ns ns ms µs
Symbol tWC tAS tAH tCS tCH tCW(3) tOES tOEH tWP(3) tDS tDH tINIT(1)
Parameter Write Cycle Time Address Setup Time Address Hold Time CE Setup Time CE Hold Time CE Pulse Time OE Setup Time OE Hold Time WE Pulse Width Data Setup Time Data Hold Time Write Inhibit Period After Power-up
tBLC(1)(4) Byte Load Cycle Time
Figure 1. A.C. Testing Input/Output Waveform(2)
VCC - 0.3V INPUT PULSE LEVELS 0.0 V 0.8 V
5096 FHD F03
2.0 V REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example)
1.3V 1N914
3.3K DEVICE UNDER TEST OUT CL = 100 pF
5096 FHD F04
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Input rise and fall times (10% and 90%) < 10 ns. (3) A write pulse of less than 20ns duration will not initiate a write cycle. (4) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however a transition from HIGH to LOW within tBLC max. stops the timer.
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Doc. No. 1007, Rev . C
CAT28C512/513
DEVICE OPERATION
Read Data stored in the CAT28C512/513 is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state when either CE or OE goes high. This 2-line control architecture can be used to eliminate bus contention in a system environment.
Byte Write A write cycle is executed when both CE and WE are low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 5 ms.
Figure 3. Read Cycle
tRC ADDRESS tCE CE tOE OE VIH WE tLZ tOLZ DATA OUT HIGH-Z tOH DATA VALID tAA
28C512/513 F06
tOHZ tHZ DATA VALID
Figure 4. Byte Write Cycle [WE Controlled]
tWC ADDRESS tAS tCS CE tAH tCH
OE tOES WE tBLC DATA OUT HIGH-Z tWP tOEH
DATA IN
DATA VALID tDS tDH
5096 FHD F06
Doc. No. 1007, Rev. C
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CAT28C512/513
Page Write The page write mode of the CAT28C512/513 (essentially an extended BYTE WRITE mode) allows from 1 to 128 bytes of data to be programmed within a single E2PROM write cycle. This effectively reduces the bytewrite time by a factor of 128. Following an initial WRITE operation (WE pulsed low, for tWP, and then high) the page write mode can begin by issuing sequential WE pulses, which load the address and data bytes into a 128 byte temporary buffer. The page address where data is to be written, specified by bits A7 to A15, is latched on the last falling edge of WE. Each byte within the page is defined by address bits A0 Figure 5. Byte Write Cycle [CE Controlled] CE
ADDRESS tAS tAH tCW CE
to A6 (which can be loaded in any order) during the first and subsequent write cycles. Each successive byte load cycle must begin within tBLC MAX of the rising edge of the preceding WE pulse. There is no page write window limitation as long as WE is pulsed low within tBLC MAX. Upon completion of the page write sequence, WE must stay high a minimum of tBLC MAX for the internal automatic program cycle to commence. This programming cycle consists of an erase cycle, which erases any data that existed in each addressed cell, and a write cycle, which writes new data back into the cell. A page write will only write data to the locations that were addressed and will not rewrite the entire page.
tWC
tBLC
tOEH OE tCS WE HIGH-Z DATA OUT tOES tCH
DATA IN
DATA VALID tDS tDH
Figure 6. Page Mode Write Cycle
OE
CE t WP WE t BLC
ADDRESS t WC I/O BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 LAST BYTE BYTE n+2
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Doc. No. 1007, Rev . C
CAT28C512/513
DATA Polling DATA polling is provided to indicate the completion of write cycle. Once a byte write or page write cycle is initiated, attempting to read the last byte written will output the complement of that data on I/O7 (I/O0I/O6 are indeterminate) until the programming cycle is complete. Upon completion of the self-timed write cycle, all I/O's will output true data during a read cycle.
Toggle Bit In addition to the DATA Polling feature of the CAT28C512/ 513, the device offers an additional method for determining the completion of a write cycle. While a write cycle is in progress, reading data from the device will result in I/ O6 toggling between one and zero. However, once the write is complete, I/O6 stops toggling and valid data can be read from the device.
Figure 7. DATA Polling
ADDRESS
CE
WE tOEH OE tWC I/O7 DIN = X DOUT = X DOUT = X tOE tOES
Figure 8. Toggle Bit
WE
CE tOEH OE tOE tOES
I/O6
(1) tWC
(1)
28C512-513 F11
Note: (1) Beginning and ending state of I/O6 is indeterminate.
Doc. No. 1007, Rev. C
8
CAT28C512/513
HARDWARE DATA PROTECTION The following is a list of hardware data protection features that are incorporated into the CAT28C512/513. (1) VCC sense provides for write protection when VCC falls below 3.5V min. (2) A power on delay mechanism, tINIT (see AC characteristics), provides a 5 to 10 ms delay before a write sequence, after VCC has reached 3.5V min. (3) Write inhibit is activated by holding any one of OE low, CE high or WE high. (4) Noise pulses of less than 20 ns on the WE or CE inputs will not result in a write cycle. SOFTWARE DATA PROTECTION The CAT28C512/513 features a software controlled data protection scheme which, once enabled, requires a data algorithm to be issued to the device before a write can be performed. The device is shipped from Catalyst with the software protection NOT ENABLED (the CAT28C512/513 is in the standard operating mode).
Figure 9. Write Sequence for Activating Software Data Protection
WRITE DATA: ADDRESS: AA 5555
Figure 10. Write Sequence for Deactivating Software Data Protection
WRITE DATA: ADDRESS: AA 5555
WRITE DATA: ADDRESS:
55 2AAA
WRITE DATA: ADDRESS:
55 2AAA
WRITE DATA: ADDRESS:
A0 5555
WRITE DATA: ADDRESS:
80 5555
(1) SOFTWARE DATA (12) PROTECTION ACTIVATED
WRITE DATA: ADDRESS:
AA 5555
WRITE DATA:
XX
WRITE DATA: ADDRESS:
55 2AAA
TO ANY ADDRESS
WRITE LAST BYTE TO LAST ADDRESS
W R I T E DATA :
5096 FHD F08
20 5555
5096 FHD F09
ADDRESS:
Note: (1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within tBLC Max., after SDP activation.
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Doc. No. 1007, Rev . C
CAT28C512/513
To activate the software data protection, the device must be sent three write commands to specific addresses with specific data (Figure 9). This sequence of commands (along with subsequent writes) must adhere to the page write timing specifications (Figure 11). Once this is done, all subsequent byte or page writes to the device must be preceded by this same set of write commands. The data protection mechanism is activated until a deactivate sequence is issued regardless of power on/off transitions. This gives the user added inadvertent write protection on power-up in addition to the hardware protection provided. Figure 11. Software Data Protection Timing
DATA ADDRESS CE AA 5555 55 2AAA
To allow the user the ability to program the device with an EEPROM programmer (or for testing purposes) there is a software command sequence for deactivating the data protection. The six step algorithm (Figure 10) will reset the internal protection circuitry, and the device will return to standard operating mode (Figure 12 provides reset timing). After the sixth byte of this reset sequence has been issued, standard byte or page writing can commence.
A0 5555 BYTE OR PAGE WRITES ENABLED
tWC
tWP WE
tBLC
5096 FHD F13
Figure 12. Resetting Software Data Protection Timing
DATA ADDRESS CE DEVICE UNPROTECTED WE
5096 FHD F14
AA 5555
55 2AAA
80 5555
AA 5555
55 2AAA
20 5555
tWC
SDP RESET
ORDERING INFORMATION
Prefix CAT Device # 28C512 Suffix N I -15 T
Product Number 28C512 28C513 Optional Company ID
Temperature Range Blank = Commercial (0°C to +70°C) I = Industrial (-40°C to +85°C) A = Automotive (-40° to +105°C)* Package P: PDIP N: PLCC T14: TSOP (10mmx14mm) T: TSOP (8mmX20mm) Speed 12: 120ns 15: 150ns
Tape & Reel T: 500/Reel
* -40°C to +125°C is available upon request
Notes: (1) The device used in the above example is a CAT28C512NI-15T (PLCC, Industrial temperature, 150 ns Access Time, Tape & Reel). (2) 28C513 is offered only in PLCC package.
28C512/513 F16
Doc. No. 1007, Rev. C
10
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Publication #: Revison: Issue date: Type:
1007 C 2/11/02 Final